Abstract: The present invention provides an electrical fuse structure for achieving a post-programming resistance distribution with higher resistance values and to enhance the reliability of electrical fuse programming. A partly doped electrical fuse structure with undoped semiconductor material in the cathode combined with P-doped semiconductor material in the fuselink and anode is disclosed and the data supporting the superior performance of the disclosed electrical fuse is shown.

Abstract: This disclosure concerns a method of manufacturing a semiconductor memory device comprising forming a plurality of trenches in a semiconductor substrate; forming a semiconductor layer provided on a cavity by connecting lower spaces of the trenches to one another and closing upper openings of the trenches in a heat treatment under a hydrogen atmosphere; etching the semiconductor layer in an isolation formation area; forming an insulating film on a side surface and a bottom surface of the semiconductor layer; filling the cavity under the semiconductor layer with an electrode material; and forming a memory element on the semiconductor layer.

Abstract: A semiconductor storage device includes: a MOSFET formed on an SOI layer of the transistor forming region; and a MOS capacitor formed on the SOI layer of the capacitor forming region. The MOSFET includes: a gate insulating film formed; a floating gate electrode; a source layer and a drain layer formed; a channel region; a high-concentration diffusion layer, and impurities of a same type as impurities which are diffused in the channel region are diffused at a high concentration in the high-concentration diffusion layer; and a silicide layer covering the high-concentration diffusion layer and the source layer. The MOS capacitor includes a capacitor electrode at the SOI layer. The capacitor electrode of the MOS capacitor is disposed so as to oppose an end portion of the floating gate electrode of the MOSFET, with the gate insulating film therebetween.

Abstract: A metal-insulator-metal (MIM) capacitor having a top electrode, a bottom electrode and a capacitor dielectric layer is provided. The top electrode is located over the bottom electrode and the capacitor dielectric layer is disposed between the top and the bottom electrode. The capacitor dielectric layer comprises several titanium oxide (TiO2) layers and at least one tetragonal structure material layer. The tetragonal structure material layer is disposed between two titanium oxide layers and each tetragonal structure material layer has the same or a different thickness. Leakage path can be cut off through the tetragonal material layer between the titanium oxide layers. In the meantime, the tetragonal structure material layer can induce the titanium oxide layers to transform into a high k rutile phase.

Abstract: A semiconductor device has a substrate with an electronic circuit, a semiconductor element provided at a first surface of the substrate and electrically connected by wire bonding to the electronic circuit, a metallic core layer electrically connected to the semiconductor element. A plurality of conductive bumps provided opposite the first surface of the substrate. A thermal hardenable resin seals at least the semiconductor element, and a metal plate is electrically connected to the metal core layer.

Abstract: A semiconductor integrated circuit device provided with a plurality of power supply wire layers including a first potential power supply wire and a second potential power supply wire formed in different layers. At least one capacitor contact wire extends from one of the first and second potential power supply wires toward the other one of the first and second potential power supply wires so as to form a capacitor between each capacitor contact wire and its surrounding wires.