Patents Examined by Davienne N. Monbleau
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Patent number: 10790318Abstract: A liquid crystal display device with a high aperture ratio is provided. A liquid crystal display device with low power consumption is provided. A display device includes a transistor and a capacitor. The transistor includes a first insulating layer, a first semiconductor layer in contact with the first insulating layer, a second insulating layer in contact with the first semiconductor layer, and a first conductive layer electrically connected to the first semiconductor layer via an opening portion provided in the second insulating layer. The capacitor includes a second conductive layer in contact with the first insulating layer, the second insulating layer in contact with the second conductive layer, and the first conductive layer in contact with the second insulating layer. The second conductive layer includes a composition similar to that of the first semiconductor layer. The first conductive layer and the second conductive layer are configured to transmit visible light.Type: GrantFiled: November 17, 2017Date of Patent: September 29, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kenichi Okazaki, Daisuke Kurosaki, Yasutaka Nakazawa
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Patent number: 10770588Abstract: A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer.Type: GrantFiled: August 1, 2016Date of Patent: September 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Chao-Ching Cheng, Chih-Hsin Ko, Hsingjen Wann
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Patent number: 10741683Abstract: A semiconductor device has a semiconductor layer and a substrate. The semiconductor layer constitutes at least a part of a current path, and is made of silicon carbide. The substrate has a first surface supporting the semiconductor layer, and a second surface opposite to the first surface. Further, the substrate is made of silicon carbide having a 4H type single-crystal structure. Further, the substrate has a physical property in which a ratio of a peak strength in a wavelength of around 500 nm to a peak strength in a wavelength of around 390 nm is 0.1 or smaller in photoluminescence measurement. In this way, the semiconductor device is obtained to have a low on-resistance.Type: GrantFiled: March 12, 2018Date of Patent: August 11, 2020Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shin Harada, Makoto Sasaki, Taro Nishiguchi, Kyoko Okita, Keiji Wada, Tomihito Miyazaki
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Patent number: 10703627Abstract: Methods of forming semiconductor structures comprising one or more cavities, which may be used in the formation of microelectromechanical system (MEMS) transducers, involve forming one or more cavities in a first substrate, providing a sacrificial material within the one or more cavities, bonding a second substrate over a surface of the first substrate, forming one or more apertures through a portion of the first substrate to the sacrificial material, and removing the sacrificial material from within the one or more cavities. Structures and devices are fabricated using such methods.Type: GrantFiled: June 11, 2014Date of Patent: July 7, 2020Assignee: SoitecInventors: Mariam Sadaka, Ludovic Ecarnot
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Patent number: 10679949Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a substrate having a first pad and a second pad thereon. A logic die is mounted on the substrate. The logic die includes a first logic die pad coupled to the first pad. A memory die is mounted on the substrate. The memory die includes a first memory die pad. A first redistribution layer (RDL) trace has a first terminal and a second terminal. The first terminal is coupled to the first pad through the first memory die pad. The second terminal is coupled to the second pad rather than the first pad.Type: GrantFiled: January 20, 2017Date of Patent: June 9, 2020Assignee: MediaTek Inc.Inventors: Sheng-Mou Lin, Duen-Yi Ho
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Patent number: 10672822Abstract: A semiconductor unit includes: a first device substrate including a first semiconductor substrate and a first wiring layer, in which the first wiring layer is provided on one surface side of the first semiconductor substrate; a second device substrate including a second semiconductor substrate and a second wiring layer, in which the second device substrate is bonded to the first device substrate, and the second wiring layer is provided on one surface side of the second semiconductor substrate; a through-electrode penetrating the first device substrate and a part or all of the second device substrate, and electrically connecting the first wiring layer and the second wiring layer to each other; and an insulating layer provided in opposition to the through-electrode, and penetrating one of the first semiconductor substrate and the second semiconductor substrate.Type: GrantFiled: March 13, 2018Date of Patent: June 2, 2020Assignee: SONY CORPORATIONInventors: Satoru Wakiyama, Hiroshi Ozaki
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Patent number: 10666260Abstract: Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.Type: GrantFiled: November 17, 2017Date of Patent: May 26, 2020Assignee: SCHOTTKY LSI, INC.Inventors: Augustine Wei-Chun Chang, Pierre Dermy
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Patent number: 10658494Abstract: Devices and methods of fabricating vertical nanowires on semiconductor devices are provided. One method includes: obtaining an intermediate semiconductor device having a substrate, a first insulator disposed above the substrate, a material layer over the first insulator, a second insulator above the material layer, and a first hardmask; etching a plurality of vertical trenches through the hardmask, the first and second insulators, and the material layer; growing, epitaxially, a set of silicon nanowires from a bottom surface of the plurality of vertical trenches; etching a first set of vertical trenches to expose the material layer; etching a second set of vertical trenches to the substrate; depositing an insulating spacer material on a set of sidewalls of the first and second set of vertical trenches; and forming contacts in the first and second set of vertical trenches.Type: GrantFiled: February 15, 2017Date of Patent: May 19, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Dominic J. Schepis, Alexander Reznicek
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Patent number: 10658501Abstract: A high electron mobility transistor (HEMT) includes a channel semiconductor structure including a stack of layers arranged on top of each other in an order of magnitudes of the polarization of materials of the layers to form multiple carrier channels at heterojunctions formed by each pair of layers in the stack. The stack of layers includes a first layer and a second layer. The magnitude of polarization of the first layer is greater than the magnitude of polarization of the second layer arranged in the stack below the first layer, and the width of the first layer is less than the width of the second layer to form a staircase profile of the semiconductor structure. The HEMT includes a source semiconductor structure including a heavily doped semiconductor material, a drain semiconductor structure including the heavily doped semiconductor material. The HEMT includes a source, a drain, and a gate electrodes to modulate the conductivity of the carrier channels.Type: GrantFiled: February 21, 2018Date of Patent: May 19, 2020Assignee: Mitsubishi Electric Research Laboratories, Inc.Inventors: Koon Hoo Teo, Nadim Chowdhury
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Patent number: 10629724Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first, second, third, and fourth semiconductor regions, and an insulating portion. The first electrode includes first and second electrode portions. The first semiconductor region includes first, second, and third semiconductor portions. The first semiconductor portion is provided between the first electrode portion and the second electrode. The second semiconductor portion is provided between the second electrode portion and the third electrode. The third semiconductor portion is provided between the first and second semiconductor portions. The second semiconductor region is provided between the first semiconductor portion and the second electrode. The third semiconductor region is positioned between the second semiconductor region and the third electrode. The insulating portion includes first and second insulating regions.Type: GrantFiled: February 21, 2018Date of Patent: April 21, 2020Assignee: Kabushiki Kaisha ToshibaInventors: Kenjiro Uesugi, Shigeya Kimura, Masahiko Kuraguchi
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Patent number: 10629756Abstract: A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided.Type: GrantFiled: March 15, 2018Date of Patent: April 21, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo, Ho-Hsiang Chen, Chewn-Pu Jou, Min-Chie Jeng
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Patent number: 10615033Abstract: An electronic device having at least a first portion including a metal oxide that is in contact with a second portion including the said metal oxide, the first portion being semiconducting and the second portion being electrically insulating.Type: GrantFiled: July 23, 2015Date of Patent: April 7, 2020Assignee: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Mohammed Benwadih, Romain Coppard
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Patent number: 10573649Abstract: A semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate, a first fin formed on the first well, and a second fin formed on the second well. The first well includes a first conductivity type, the second well includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The substrate includes a first semiconductor material. The first fin and the second fin include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The first semiconductor material in the first fin includes a first concentration, the first semiconductor material in the second fin includes a second concentration, and the second concentration is larger than the first concentration.Type: GrantFiled: February 17, 2016Date of Patent: February 25, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chien-Hung Chen, Shih-Hsien Huang, Yu-Ru Yang, Chia-Hsun Tseng, Cheng-Tzung Tsai, Chun-Yuan Wu
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Patent number: 10553717Abstract: A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.Type: GrantFiled: April 26, 2016Date of Patent: February 4, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Christopher Boguslaw Kocon, Hideaki Kawahara, Simon John Molloy, Satoshi Suzuki, John Manning Savidge Neilson
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Patent number: 10505053Abstract: An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.Type: GrantFiled: April 26, 2016Date of Patent: December 10, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Thierry Coffi Herve Yao, Gregory James Scott
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Patent number: 10461245Abstract: According to one embodiment, a method of manufacturing a magnetic memory device, includes forming a stack film including a magnetic layer on an underlying area, forming a hard mask on the stack film, forming a stack structure by etching the stack film using the hard mask as a mask, forming a first protective insulating film on a side surface of the stack structure, and performing an oxidation treatment.Type: GrantFiled: March 3, 2015Date of Patent: October 29, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shuichi Tsubata, Masatoshi Yoshikawa, Satoshi Seto, Kazuhiro Tomioka
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Patent number: 10461192Abstract: A semiconductor device may include a substrate, a gate electrode disposed on the substrate, a gate insulation layer disposed on the substrate to cover the gate electrode, an active layer including an oxide semiconductor disposed on the gate insulation layer, an insulating interlayer disposed on the gate insulation layer to cover the active layer, a protection structure including a plurality of metal oxide layers disposed on the insulating interlayer, and a source electrode and a drain electrode disposed on the protection structure.Type: GrantFiled: September 1, 2015Date of Patent: October 29, 2019Assignee: Samsung Display Co., Ltd.Inventors: Je-Hun Lee, Eun-Hyun Kim, Sang-Won Shin, Eun-Young Lee
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Patent number: 10374087Abstract: A semiconductor device includes a substrate, first and second isolation layers, an insulation layer pattern, and a gate structure. The substrate has a cell region and a peripheral region. The first isolation layer is buried in a first upper portion of the substrate in the peripheral region. The second isolation layer is buried in a second upper portion of the substrate in the cell region, and extends along a first direction substantially parallel to a top surface of the substrate. The insulation layer pattern is buried in the first upper portion, and extends along a second direction substantially parallel to the top surface of the substrate and substantially perpendicular to the first direction. The insulation layer pattern has a lower surface higher than a lower surface of the second isolation layer, and applies a stress to a portion of the substrate adjacent thereto.Type: GrantFiled: December 2, 2015Date of Patent: August 6, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Won Kim, Jae-Kyu Lee
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Patent number: 10340369Abstract: A tunneling field effect transistor device disclosed herein includes a substrate, a body comprised of a first semiconductor material being doped with a first type of dopant material positioned above the substrate, and a second semiconductor material positioned above at least a portion of the gate region and above the source region. The first semiconductor material is part of the drain region, and the second semiconductor material defines the channel region. The device also includes a third semiconductor material positioned above the second semiconductor material and above at least a portion of the gate region and above the source region. The third semiconductor material is part of the source region, and is doped with a second type of dopant material that is opposite to the first type of dopant material. A gate structure is positioned above the first, second and third semiconductor materials in the gate region.Type: GrantFiled: September 13, 2017Date of Patent: July 2, 2019Assignee: GLOBALFOUNDRIES Inc.Inventor: Bartlomiej Jan Pawlak
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Patent number: 10319634Abstract: A semiconductor device that provides a pad electrically connected to the metal layer and a capacitor connected to the pad is disclosed. The semiconductor device provides an insulating film between the lower electrode of the capacitor and the pad. Because the insulating film protects and isolates the lower electrode from etching of the substrate via and deposition of the via metal, the lower electrode avoids voids or vacancies during formation of the via and the via metal.Type: GrantFiled: August 28, 2017Date of Patent: June 11, 2019Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Fumio Yamada