Abstract: A processor comprises first and second operation units, a first program memory which contains first microinstructions for controlling the first operation unit and second microinstructions for controlling at least the second operation units, a second program memory which contains microinstructions for controlling the second operation unit, first control means connected to the first program memory for controlling the first operation unit and the second operation unit, and second control means connected to the second program memory for controlling the second operation unit. In a normal mode, all operation units are under control of the first control means and in a multiprogram mode, the first operation unit is under control of the first control means and the second operation unit is under control of the second control means. These two mode operations are selected in accordance with the microinstructions stored in the first or second program memories.

Abstract: According to the present invention, in a data processing unit which executes pipeline processings by developing an instruction into multiple flows through microprogram control, is a method provided where the microinstruction is divided into a part for controlling a first stage of pipeline and a part for controlling second and successive stages. The part for controlling the first stage is read simultaneously with the part for controlling the second and successive stages of the flow prior to the current flow. The present invention thus provides an advantage in that microprogram control can be employed for the first stage of the pipeline and resulting in a data processing unit which is capable of executing more flexible pipeline processings than the prior art can be formed.

Abstract: A method of operating a data processing system using virtual memory in which virtual memory addresses are formed by a base register value and a displacement value and are mapped to real memory addresses includes the steps of adding the base register value content and the displacement value, and simultaneously with the adding operation, performing a translation of the base register value to produce a virtual address corresponding to the base register value.

Abstract: A method for running an expert system on a data processing system in which the Rulebase is segmented into contextual units so that the system memory can accommodate each unit. Portions of the Rulebase containing data or knowledge that is not needed in a particular application may then be eliminated. The segmenting of the Rulebase also allows the contextual units of the application to be paged into and out of the system as needed. The various intersegment relationships are managed by the system as units are paged into and out of memory. A second Rulebase unit may be called by the first unit and executed at any time during the processing of the first Rulebase. Provision is made in the form of a Global attribute to selectively identify and store the data that is relevant to the application and that has been accumulated up to the point where another unit is called so that at some time later in the process, when the system returns to the first unit, it can proceed from the last RULE node that was processed.

Abstract: A data assembler and serializer for use in bit mapped graphics systems where flexible windowing and panning are desired. The unit accepts display memory data as either one 8-bit word or two 4-bit words. Leading and trailing pixels not required in the final bit stream, as indicated by control data, are removed from the words. Remaining pixels are then shifted and concatenated to form a continuous stream of video data. The assembled data words are supplied to a FIFO buffer and from the buffer to a shift register for generating a serial output. Positioned between a display memory and a color palette or monitor, the system supports smooth panning and hardware windows on pixel boundaries.

Abstract: When a disk controller receiving an access from a host computer to a disk device is connected with a disk connection device, if a relevant disk is used by another disk controller, positioning data for seek, set file mask and set sector are queued in a common memory. When the relevant disk becomes free, the disk controller reads the queued information and requires the disk device for positioning. A request of a reconnection with the host computer is issued from the disk controller informed by the disk unit, which has finished positioning at the position specified by the positioning data, search of an aimed record and a read/write operation of transmitted data are effected without any new intervening of an access program of the host computer.

Abstract: In a computer system having at least a bus with at least one central processing unit (CPU), one random access memory (RAM), and a first configuration of a plurality of different types of peripheral units (e.g. tape drives, disk drives, diskette drives, printers, unit record peripherals, etc.) coupled to the bus, an apparatus for controlling the first configuration and also capable of controlling a predetermined number of other configurations of different types of peripheral units when any of that predetermined number of configurations of peripheral units is coupled to the bus.

Abstract: A multi-unit data-collecting/information-generating/instruction-passing/communication-n etwork being a multiplicity of individual microprocessor systems capable of data-collection/presenatation/order-passing associated with instrumentation, process control elements and/or information displays, indicators and recorders on a two or three wire network programmed in a manner to enable(1) each individual information generating system comprised of one data measuring instrument generating a signal connected in juxta-position to an A/D and a microprocessor capable of converting analog signals from the instrumentation to digital signals then to serial digital strings and through a transceiver (T/R) transmit said digital serial strings onto the network,(2) each individual information-passing system comprised of a T/R-microprocessor-A/D juxta-positioned with a process control element, said system capable of recognizing an identifier code within a serial digital string containing instructions for said process control ele

Abstract: The invention relates to a shift register structure and its control. The positioning and/or synchronization of data contained in this register for the purpose of serial operation are essentially obtained by acquisition of data on at least one auxiliary output SA1 of this register R. In particular the invention enables a programmable delay buffer register to be produced very simply.

Abstract: An address extension system is provided for generating a physical address by summing a segment starting point address and an offset. Conventionally, the content of a segment register is shifted by a predetermined amount and summed to the offset, and the address space and the segment starting point address are fixed. In contrast, the present address extension system includes a register for storing shift amount data and the shift amount is set in the register and shifted. An address extension system is also proposed wherein the shift amount is written in a predetermined bit of the segment register. As a result, the address space can be extended and the segment starting point address can be arbitrarily set.

Abstract: A microprocessor has a register in which attributive data corresponding to a memory to be coupled to the microprocessor is written, and a control circuit which controls address signals to be supplied to the memory in accordance with the attributive data. The attributive data is composed of range data for discriminating ranges of address data supplied to an address bus, system data indicative of addressing systems of the memories corresponding to the respective address ranges, and bit number data indicative of numbers of address bits of the memories. Thus, in a case where the memory to be accessed is of an address multiplexing systems as in a dynamic RAM, the address data of the address bus is divided into row address data and column address data, which are then supplied to the memory in time division.

Abstract: In a microprogammed controller, the conventional pipeline register is replaced by a pair of coupled latches: a so-called "transparent" latch is placed between the output of the microprogram memory and the input of one or more system resources including at least the sequencer or address generator, and another latch is placed between the output of each such resource and the destination of its output. The appropriate bits of a microinstruction are supplied from the microinstruction memory to the associated resource via the transparent latch. The clock signal for the sequencer or other resource serves as the enable signal for the output latch (which can be either a transparent latch or an edge-triggered latch resposive to the rising edge of the clock signal), while the inverted sense of the clock signal provides the enable signal for the transparent latch.

Abstract: In a digital data processing system having a resource which is shared between a plurality of users, an arbitration system comprises a plurality of resource requestors (14 to 16) each associated with a respective user, and a resource grantor (10) to which the requestors are connected in parallel via a set of common lines (11 to 13). Each resource requestor is adapted to apply a request signal on a predetermined first one (11) of the lines when the associated user requests the resource, and the resource grantor is responsive to the presence of a request signal on the first line to subsequently apply a grant signal on a predetermined second one (12) of the lines to grant the resource. Each resource requestor requesting the resource is responsive to the grant signal to apply an accept signal on a predetermined third one (13) of the lines after a delay which is different for each resource requestor and which determines the priority of the user associated with the resource requestor.

Abstract: A method and apparatus for adding a low-cost spelling check dictionary feature to document preparation systems such as portable electronic typewriters, the spelling check being performed on a character-by-character basis and an error signal emitted upon the earliest determination that an input character does not conform to that of any word listed in the dictionary. Semiconductor ROM is used for storage of the dictionary listing and for program control of the spelling check. Text compression methods are utilized to permit storage of large vocabularies (about 35,000 words) while minimizing the ROM capacity required (about 3 IC's of 256K bits each).

Abstract: The present invention relates to a system for controlling multiple communications lines, so that a computer system can operate with a single component failure. Two processors are used to control two communications controllers and each of the controllers control up to 15 line controllers. Each line controller has two ports and each port is connected to a communications controller thereby providing two communications paths to each processor. Two power supplies are also used to provide single failure fault-tolerance. A downloadable microprocessor is provided in combination with, but separate from, an interface board that is designed to meet various communication format specifications and the line controller comprises the two boards.

Abstract: Improved methods and operating systems for use with a multi-mode microprocessor enable efficient operation in a multi-mode environment. Preferred embodiments for use with microprocessors which were not designed to switch from each mode to another mode enable multi-tasking of a mixture of programs written for different modes using the mode switching methods of the present invention. Frequently used portions of the operating system are stored in memory at locations which can be commonly addressed in all modes. Means for handling device drivers and interrupts in all modes are also provided. Preferred embodiments for use with computer systems using microprocessors such as the Intel 80286 include means for storing the operating system routines to maximize performance of the system in real mode. Auxiliary protection hardware and I/O masking hardware are also provided in alternate preferred embodiments to enhance protection during real mode operation of such systems.

Abstract: What is disclosed is a time partitioned bus arrangement for use in a computer system wherein different circuits therein are interconnected by a plurality of busses and operation is such that information to be processed can be read out of one circuit, processed in some manner in another circuit, and the processed information be stored in the same or another circuit all within one cycle of a system clock in the computer system, and without the need for bus control circuits and bus interfaces in the circuitry connected to the busses. Some of the circuits have their input/output connected to only a single one of the busses, while other circuits have their input connected to one bus and their output connected to a different bus, and yet other circuits have either their input or output connected to one of the busses and their other input/output connected to circuitry external to the bus arrangement.

Abstract: An address generation system comprising a decoder for decoding an addressing field of a given instruction code, and a control circuit connected to the decoder to cause a register to be read out in accordance with the decoded information. A hold circuit is connected to the decoder to hold an address generation information for generating an address of an operand. A correction number generator is connected to the hold circuit to generate a correction number determined in accordance with the address generation information for the designated register. An adder is provided to receive the correction number and the content read out from the register and to output the content of the register modified by the correction number.

Abstract: An information processing system is disclosed which provides a writer with acceptable replacement phrases to substitute for trite phrases in a manuscript text. The replacement phrases are grammatically equivalent to the trite phrases and can be immediately inserted into the text without further alteration.

Abstract: A unit operative in concurrence with a vector processing for beforehand sequentially generating page addresses containing vector data to be referred to thereafter and a unit for achieving a processing to determine whether or not a page fault occurs in a page in an address translation and responsive to an occurrence of a page fault in a page for executing processing to beforehand transfer the page to a main storage are provided. Even if a vector element existing in the page becomes necessary in the vector processing after the operation described above, another paging processing is not necessary because the page exists in the main storage.