Abstract: A data processing system capable of processing data in a plurality of modes including an input/edit mode is disclosed. The system includes a data name memory, start address memory and edit condition memory wherein the status of data being processed in the input/edit mode is stored when processing in the input/edit mode is interrupted to enable processing in a different mode and based upon which the system resumes processing in the input/edit mode.

Abstract: The subject invention features diagnostic circuitry installed on one or more chips of a board. This diagnostic circuitry is constructed so that during a diagnostic interval it generates a diagnostic output signal if and only if it is supplied with normal voltages on service supply structures (such as ground, B+ supply, clock) distributing service voltages to devices on the board. The diagnostic output is connected to a diagnostic output pin of the chip which may also serve as one of the operating pins of the chip (such as a signal input pin). The receptacle for the diagnostic pin is connected on the board to a diagnostic interface at the periphery of the board.

Abstract: A method and apparatus for performing a bit map search of the allocation state of memory pages in a computing system. A competitive search is accomplished by a pair of dedicated microprocessors, each of which implements a differently optimized search procedure, to find a bit indicating an un-allocated page in the memory. The first processor to find such a bit interrupts the other processor. The first processor then calculates the free page location and informs the computing system of the location. The other processor is responsible for updating the bit map and summary buffers.

Abstract: A multiprocessor data processing system includes a processing unit which, together with other processing units, including input/output units, connects in common to an asynchronous bus network for sharing a main memory. At least one processing unit includes a synchronous private write through cache memory system which includes a main directory and data store in addition to a bus watcher and a duplicate directory. The bus watcher connects to the asynchronous bus network and captures all main memory requests while the duplicate directory maintains a copy of the cache unit's main directory. Independently and autonomously synchronously operated tie-breaker circuits apply requests to the main and duplicate directories. When tie-breaker circuits detect conditions relating to a request which could result in cache incoherency, it initiates uninterrupted sequences of cycles within the corresponding cache main or duplicate directory to complete the processing of that same request.

Abstract: A reduced instruction set computer (RISC) with a Harvard architecture is disclosed. The RISC may be designed to be used simply as a RISC or may be designed to be used to emulate a complex instruction set computer (CISC). Or, it may be designed for use as either. A CISC design methodology is disclosed whereby a RISC is designed and fabricated and whereby RISC emulation code is written concurrently with design and fabrication and also subsequent to fabrication.

Abstract: A special purpose communications protocol processor (CPP) provides more efficient processing of layered communications protocols--e.g. SNA (Systems Network Architecture) and OSI (Open Systems Interconnection)--than contemporary general purpose processors, permitting hitherto unavailable operations relative to high speed communication links. The CPP contains special-purpose circuits dedicated to quick performance (e.g. single machine cycle execution) of functions needed to process header and frame information, such functions and information being of the sort repeatedly encountered in all protocol layers, and uses instructions architected to operate these circuits. The header processing functions given special treatment in this manner include priority branch determination functions, register bit reshaping (rearranging) functions, and instruction address processing functions.

Abstract: A microcomputer is disclosed which provides for a dedicated DMA data and address bus connecting an on-chip DNA controller with on-chip memories, and with on-chip ports for access to external memory and input/output devices. The DMA controller contains a control register which has two start bits, capable of representing four start codes. The four start codes allow for the unconditional starting and aborting of a DMA transfer, as well as for stopping the DMA after the current read or write operation, or after the next write operation (i.e., completion of a data word transfer). The control register also contains two status bits which the DMA controller writes with the status of the DMA operation, and also contains two synchronization bits for synchronizing the DMA operation in the source, destination, or source and destination modes (or not at all). Two interrupt enable registers are provided in the microcomputer, for independently enabling interrupts for the CPU and the DMA.

Abstract: In order to be able to arrange a series of files, which are in a reference relationship, on an arbitrary path, depending on the structure of the file system, a path specifying a particular file, which is in the reference relationship, is specified by a position relative to an object program file in a file system including a program, which is in course of execution, depending on the program, which is in course of execution.

Abstract: A task status word (TSW) is created for each task indicating, the instant location of the task, its priority and a record of synchronizing signals. Task status words are accessible from an addressable memory section for delivery to a TSW register. From the TSW register, a selected TSW effects control functions to synchronize tasks in different processors or computational units as well as input-output processors. A physical memory manager locates TSWs in response to signals, then checks the location of the task and the nature of the signal to determine signal routing to a processor. If a task is not in a processor, an interrupt manager resolves priority and signal significance indicated by the TSW to determine an interrupt.

Abstract: A memory access control apparatus according to the present invention which controls an IC memory of which is under the control of a BIOS in the same manner as in a normal disk unit. External file units including the IC memory, a floppy disk unit, a hard disk unit, and the like are assigned a series of drive numbers. Registers store parameters for using the IC memory as an external file, and an access address and a transfer length of the IC memory are expressed in a sector form. The BIOS receives the access address and the parameters, translates the address into a byte form address, and transfers data to a corresponding area.

Abstract: In a plural processor data processing system, a lock is obtained on a commonly shared storage means that allows for the testing of a control word associated with a selected memory address of a particular data processor wherein each of the data processors of the system is capable of independently requesting a lock on said control word. Lock requests are broadcast to each of the data processors. The lock is then established according to predefined criteria by transmission of the lock requests of all of said processor means at the same time at controlled intervals, and by providing the lock on the control word when the requesting processor is the only processor that is requesting a given control word during a control interval, or when the processor transmits its lock request simultaneously with other processor means of a lower priority.

Abstract: An extended bus controller includes a base module including at least a first peripheral control unit connected to a base bus, a central processing and controlling unit, and a memory unit; an extension module including at least a second peripheral control unit connected to an extended bus; a connection bus interconnecting the base bus of the base module and the extended bus of the extension module; a direct memory access control unit provided for at least one of the base module and the extension module for directly controlling data transfer between the first and second peripheral control units and the memory unit; a first master clock generator unit for supplying first master clocks to the direct memory access control unit and controlling the direct memory access control unit, the first master clocks having a first frequency determined by a data transmission delay time of at least one of the base bus, the connection bus and the extension bus, and by the performance of the first peripheral control unit and the

Abstract: In a system controller having multiple parts including a microprocessor, a main program for execution upon the microprocessor, and at least one clock interrupt handler portion, a method and apparatus for insuring proper operation comprised of providing a main counter and a delay counter in the main program providing a hardware watching timer, and providing in the clock interrupt handler means for starting the hardware watchdog timer and decrementing the main counter of the main program. The hardware watchdog timer reinitializes the main program in the event that the main program fails to respond to the clock interrupt handler and the delay counter reinitializes the main program and the clock interrupt handler in the event that the watchdog timer fails to operate. Therefore, each of the multiple parts of the system controller serve to insure the functionality of the other parts.

Abstract: A system for maintaining a cache in the main memory of a large data processing system for storing many tracks of data received from a large number of disk files where the disk files are non-volatile which is required to store critical customer data. More importantly, the present invention resides in a software system which is a part of the operating system of a large data processing system to maintain this cache.

Abstract: A data processing system for executing operations on electronic data comprises a stack for performing numerical operations functionally situated between the top of the stack and the next storage position in the stack so that operands on which an operation is to be performed are automatically present at inputs of an arithmetic logic unit for performing the operations.

Abstract: A multiprocess computer executes operating system routines and user processes. One specific peripheral apparatus has a preferential status in that it may emit attention interrupts and/or completion interrupts that relate to an I/O-operation. Only those interrupts find preferential treatment in that the associated interrupt has a higher priority level than the one(s) corresponding to the majority of the operating system routines. In contradistinction to all other user process interrupts the above attention and completion interrupts are executed in their own hardware and software context, to which effect the latter context is temporarily activated, and after execution of the interrupt procedure restored to its previous status. In this way dialog with the peripheral may be executed real-time, while the "own" context greatly facilitates programming. An upgraded driver program is also presented.

Abstract: A data processing system including at least one storage device for storing and retrieving data from several rotating tracks where each track includes sequentially located blocks for the storage of data. A storage interface is connected for controlling this storage device. The storage interface includes a data buffer for storing data retrieved from the storage device. A storage driver is provided that receives storage access commands from a processor and provides commands to the interface in response to these commands from the processor. This storage driver further includes the capability to provide commands for requesting data that has not been requested by the processor. This data not requested by the processor is stored in a data buffer. These commnads for data not requested by the processor are issued in accordance to procedure that computes these commands called read ahead commands based on the order of commands received from the processor and also based on the number of storage devices in use.

Abstract: A single instruction stream multiple data steam data flow signal processor and method for implementing macro data flow control, in which a plurality of data processors have contentionless access to global memory data. Data processing tasks for the data processors, such as primitive executions together with graph scheduling processes, are developed asynchronously and in parallel from a command program and a macro data flow control graph.

Abstract: A data processing system includes a plurality of host systems and peripheral subsystems, particularly data storage subsystems. Each of the data storage subsystems includes a plurality of control units attaching a plurality of data storage devices such as direct access storage devices (DASD) for storing data on behalf of the various host systems. Each of the control units have a separate storage path for accessing the peripheral data storage devices using dynamic pathing. The storage paths can be clustered into power clusters. Maintenance personnel acting through maintenance panels on either the control units or the peripheral data storage devices activate the subsystem to request reconfiguration of the subsystem from all of the host systems connected top the subsystem. The host systems can honor the request or reject it based upon diverse criteria. Upon each of the host systems approving the reconfiguration, the subsystem 13 is reconfigured for maintenance purposes.

Abstract: A method for processing address translation exceptions occurring in a virtual memory system employing demand paging and having a plurality of registers and a real storage area, includes the steps of: (a) temporarily storing for each storage operation; (i) the effective storage address for the operation; (ii) exception control word information relative to the ones of the registers involved in the operation and the length and type of the operation; and (iii) any data to be stored during the operation; (b) retrieving the temporarily stored information to form an exception status block if an exception is generated indicating a failed operation; and (c) reinitiating the failed operation based on the information contained in the exception status block.