Abstract: A memory module includes a module error interface, a module data interface, and a plurality of memory device. The module error interface communicates error information a system control path. The module data interface communicates data to and from a main memory path that is separate from the system control path. Each memory device includes a device controller, a device error interface and a device data interface in which the error data interface is separate from the device data interface. Each device controller includes an ECC engine and an ECC controller. The ECC engine corrects an error in data that is read from the corresponding memory device to generate corrected data, generate error information, communicate the error information through the device error interface to the module error interface, and communicate the corrected data through the device data interface to the module data interface. The ECC controller records the error information.

Abstract: A system and method for analyzing big data activities are disclosed. According to one embodiment, a system comprises a distributed file system for the entities and applications, wherein the applications include one or more of script applications, structured query language (SQL) applications, Not Only (NO) SQL applications, stream applications, search applications, and in-memory applications. The system further comprises a data processing platform that gathers, analyzes, and stores data relating to entities and applications. The data processing platform includes an application manager having one or more of a MapReduce Manage, a script applications manager, a structured query language (SQL) applications manager, a Not Only (NO) SQL applications manager, a stream applications manager, a search applications manager, and an in-memory applications manager. The application manager identifies if the applications are one or more of slow-running, failed, killed, unpredictable, and malfunctioning.

Abstract: An embodiment of a system is disclosed, including an interface configured to communicate to a device under test (DUT). The DUT may include a plurality of processor cores. The system also includes a testing apparatus configured to concurrently measure a performance of a portion of each processor core to generate a first set of test values. Each test value of the first set may correspond to a given processor core of the plurality of processor cores. The testing apparatus may also be configured to analyze the first set of test values, and reject the DUT in response to a determination that at least one test value of the first set of test values exceeds a first threshold.

Abstract: Methods and devices are provided in which generation of an error is identified while a function of a program is performed. A message is displayed relating to existence of a solution corresponding to the error.

Abstract: Embodiments of the present disclosure provide a method and apparatus for device testing via an optical interface. In one instance, the apparatus may comprise a test controller to operate a camera to generate an image to capture test data displayed on a screen of a device under test. The test controller may be configured to extract the test data from the image, analyze the test data, and generate feedback information for the device under test, based at least in part on a result of the analysis of the test data. The camera may be included in the apparatus and communicatively coupled with the test controller. Other embodiments may be described and/or claimed.

Abstract: A test device for testing a device under test (DUT) includes an integrated control interface adaptable for a plurality of different communication standards. The integrated control interface can be adapted to be compliant with the communication standard used by a DUT connected to the test device.

Abstract: An aspect includes memory error recovery in a memory system includes detecting an error condition within a memory chip of the memory system. A chip mark is applied to the memory chip to flag the error condition. An address range of the memory chip associated with the error condition is determined. Data are written from the address range of the memory chip to a cache memory. The chip mark is removed based on determining that all of the data from the address range have been written to the cache memory.

Abstract: A storage system maintains a cache and a non-volatile storage. An error recovery component queries a cache component to determine whether modified customer data exists in a memory preserve cache. In response to determining that the modified customer data exists in the memory preserve cache, and in response to a failure beyond a threshold number of times of initial microcode load (IML) attempts to recover the modified customer data, an error notification is transmitted for manual intervention to avoid loss of the modified customer data.

Abstract: Some embodiments include apparatuses and methods having a first interface to communicate with a processing unit, a second interface to communicate with a memory device, and a module coupled to the first and second interfaces. In at least one of the embodiments, the module can be configured to obtain information stored in the memory device and perform at least one of testing and repairing of a memory structure of the memory device based at least in part on the information.

Abstract: An apparatus includes a plurality of drives configured as a redundant array of independent disks (RAID) and drive array controller logic to: calculate a first partial parity log (PPL) value for a first write operation that targets a first active stripe of the plurality of drives; store the first PPL value in a first pre-allocated portion of the plurality of drives that depends on a first number associated with the first active stripe; calculate a second PPL value for a second write operation that targets a second active stripe of the plurality of drives; and store the second PPL value in a second pre-allocated portion of the plurality of drives that depends on a second number associated with the second active stripe.

Abstract: Embodiments herein provide a testing apparatus (whether physical or simulated) for testing a non-core MMU in a processor chip. Unlike core MMUs, non-core MMUs may be located in a part of the processor chip outside of the processing cores in the chip. Instead of being used to perform address translation requests sent by the processing core, the non-core MMUs may be used by other hardware modules in the processor chip such as compression engines, crypto engines, accelerators, etc. In one embodiment, the testing apparatus includes a MMU testor that transmits the translation requests to the non-core MMU which tests its functionality. Using the data provided in the translation requests, the non-core MMU performs virtual to physical address translations. The non-core MMU transmits the results of these translations to the MMU testor which compares these results to expected results to identify any design flaws in the non-core MMU.

Abstract: A system includes a CPU including a primary address decode logic module (PADLM) and a plurality of diagnostic registers, wherein the PADLM includes address bus inputs, and an enable input port. The system further includes a data flip-flop having a data input coupled to a master enable signal line, a set input coupled to an interrupt signal line, an output coupled to the enable input port of the PADLM, and a clock input. Still further, the system includes an address decode logic module having a memory address input and an output indicating whether the memory address is within a predetermined address range of the diagnostic registers, wherein the output of the address decode logic module is coupled to the clock input. Memory mapping is enabled in response to receiving an interrupt signal and determining that the memory address is within a predetermined range of memory addresses for diagnostic registers.

Abstract: Method, apparatus, and system for improving semiconductor device writeability at row/bit level through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage. By virtue of BTI, application of the first array supply voltage may lead to improved writeability of one or more cells of the device.

Abstract: Disclosed are solutions for resolving a redundant array of independent disks (RAID) write hole, or a parity-based fault scenario that occurs when a power failure and a drive failure occur at or close to the same time. Drive array controller logic assigns a sequence number to write operations received from a computing system and converts respective write operations, including corresponding sequence numbers, to a multiple-drive write to a series of RAID drives. A microcontroller at each drive writes, to a history log (HLOG) on the drive, a logical-to-physical address mapping of a prior sector of the drive that was written along with a corresponding sequence number. Upon receipt of a new write to the mapped logical address, the microcontroller removes the HLOG entry for the logical address, and writes a new entry to the HLOG with a new physical address mapping to the logical address with a new sequence number.

Abstract: A system for package management includes an interface and a processor. The interface is to receive an indication to install a package. The processor is to determine a configured package using a set local configuration properties and using the package and to launch, using a metascheduler, a set of subschedulers to install a plurality of applications of the configured package.

Abstract: Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.

Abstract: A computer-implemented method may comprise performing a disaster recovery restore process on a target computing device; accessing a backup server; and selecting a source backup from the backup server. The source backup may comprise one or more volumes, partitions, files and device drivers of a source computing device from which the source backup was created. The selected source backup may then be installed in an offline partition of the target computing device. One or more target device drivers may then be installed in the offline partition. To complete the disaster recovery restore process on the target computing device, the target computing device may then be rebooted. Both the backup of the source computing device and the active partition of the target device may comprise source computing device-dependent hardware device drivers. When carried out in a Windows® environment, Sysprep need not be used and the kernel need not be modified.

Abstract: According to one embodiment, an electronic device includes a receiver and a processing circuit. The receiver is configured to receive first data related to operating statuses of storage from external devices connected through a network. The processing circuit is configured to control the external devices to save data stored in a first area in the storage of a first external device on the storage of each of two or more second external devices based on the first data received by the receiver.

Abstract: Device health metrics may be collected and aggregated on a device before sending to a server for further aggregation. The method may include determining a crash has occurred on a device, and recording the crash and information corresponding to the crash in buffer storage on the device. The method may also include recording a crash type, a crash time, an identification of a component that caused the crash and a state of the device when the crash occurred. The method may also include grouping two or more crash events based on the crash type, generating device health metrics data including metadata corresponding to the two or more crash events, storing the device health metrics data in the buffer storage on the device, and sending the device health metrics data along with device identification information to a server for further aggregation.

Abstract: Methods and apparatus for controlled recovery of error information between two (or more) independently operable processors. The present disclosure provides solutions that preserve error information in the event of a fatal error, coordinate reset conditions between independently operable processors, and implement consistent frameworks for error information recovery across a range of potential fatal errors. In one exemplary embodiment, an applications processor (AP) and baseband processor (BB) implement an abort handler and power down handler sequence which enables error recovery over a wide range of crash scenarios. In one variant, assertion of signals between the AP and the BB enables the AP to reset the BB only after error recovery procedures have successfully completed.