Abstract: A control apparatus comprises a microcontroller, an auxiliary circuit, a delay module and a logical circuit; the microcontroller is connected to a first input end of the logical circuit via the auxiliary circuit and connected to a second input end of the logical circuit via the delay module, and an output end of the logical circuit is connected to a device to be controlled; if the microcontroller is reset in a process of outputting the closing control signal, a delay disabling signal becomes invalid, the delay module is enabled to output the closing control signal within a preset delay time, wherein the delay time is greater than or equal to a reset time. A power supply system is also provided to avoid a risk that an automobile suddenly loses power due to unexpected reset of the microcontroller.

Abstract: A smart light switch includes a control block and heat generating components such as a light actuator, a processor and memory, a data communications module, and an environmental sensor. The processor is operable to receive as an input a measured temperature value from the environmental sensor and a power consumption value from the of heat generating components. The processor is operable to select a temperature offset value from a dataset of temperature offset values that is stored in memory. Each temperature offset value stored in the dataset of temperature offset values is associated with a potential combination of power consumption inputs. The processor is further operable to determine a calibrated temperature value from the measured temperature value adjusted by the temperature offset values selected from the dataset of temperature offset values.

Abstract: The present invention discloses a power supply circuit and a UPS auxiliary power supply system having the same. The power supply circuit comprises a transformer, a primary-side switch unit and a secondary-side switch unit. When the input power supply is powered on, the second switch of the secondary-side switch unit maintains in an off state, the first switch of the primary-side switch unit performs an on-off action, and the input power supply supplies power to the load and the energy storage unit. When the input power supply is powered down, the first switch of the primary-side switch unit maintains in an off state, the second switch of the secondary-side switch unit performs an on-off action, and the energy storage unit supplies power to the load.

Abstract: A multi-source energy harvester system includes a power conversion apparatus. First and second energy harvesters respectively harvest first and second energy and respectively provide first and second input powers. The power conversion apparatus includes an adjustable impedance matching circuit and a power conversion circuit. The impedance matching circuit generates an adjusted power according to the first input power. The power conversion circuit converts a bus power to an output power. The energy harvester system controls a first and a second switch circuits according to the adjusted power and/or the second input power to select and conduct one of the adjusted power or the second input power as the bus power, and adjusts an impedance of the adjustable impedance matching circuit to maximize a voltage of the adjusted power.

Abstract: A signal processing circuit includes a signal receiving circuit for generating a first input signal and a second input signal; a signal output circuit for generating a first output signal and a second output signal according to the first input signal and the second input signal; a negative impedance circuit, for amplifying the first input signal at the first input terminal to generate a first amplified input signal at the second output terminal, and for amplifying the second input signal at the second input terminal to generate a second amplified input signal at the first output terminal; a first capacitor; a second capacitor; wherein the first capacitor and the second capacitor have different DC voltage levels at both terminals, such that the impedance-signal variation rate of the negative impedance circuit is lower than a predetermined level.

Abstract: The preset invention provides a clock buffer including a first circuit, a second circuit and an edge collector, wherein the first circuit is arranged to receive an input clock signal to generate a first clock signal, the second circuit is arranged to receive the input clock signal to generate a second clock signal, and the edge collector is arranged to generate an output clock signal by using a falling edge of the first clock signal and a rising edge of the second clock signal.

Abstract: A power supply system includes: a first battery; a second battery; a heater; a power circuit in which the first battery and the second battery and the heater are provided; a first external charging unit supplying electric power external to a vehicle to the power circuit; and an electronic control unit controlling the power circuit and the first external charging unit. During execution of heater heating control that heats the first battery with the heater by driving the heater with the electric power supplied from the first external charging unit, the electronic control unit executes discharging heating control that heats the first battery by discharging electric power from the first battery to the second battery, and charges the first battery with the electric power supplied from the first external charging unit after a temperature of the first battery becomes equal to or higher than a heating determination temperature.

Abstract: A phase predictor to accurately detect and predict the phase relationship between two clocks running at different frequencies. The phase relationship can be used to record the transmission and reception times of Ethernet frames transmitted over a transmission medium with very high accuracy.

Abstract: Power converter circuits, including DC-DC converter circuits, that conserve IC area by utilizing more area-efficient alternatives for measurement circuitry. Various embodiments include a power converter circuit including a charge pump having a plurality of stack-nodes VCXM and at least one multiplexor for coupling selected stack-nodes VCXM to a corresponding comparator circuit configured to output a signal indicative of a difference between a selected input to the multiplexor and a reference signal. The number of comparator circuits is less than (N?1)×M, where N is the conversion gain of the power converter circuit (i.e., the number of charge pump stages X plus one), and M is the number of parallel charge pump legs. Related methods include measuring voltages at stack-nodes VCXM in a charge pump, wherein the stack-nodes VCXM are selected by means of a multiplexor and an input to a comparator.

Abstract: Disclosed herein are package substrates with integrated components, as well as related apparatuses and methods. For example, in some embodiments, an integrated circuit (IC) package, may include: a substrate having opposing first and second faces, an insulating material disposed between the first and second faces, and a thin film transistor (TFT) disposed between the first and second faces, wherein a conductive portion of the TFT is disposed on a layer of the insulating material, and the conductive portion of the TFT is a gate, source, or drain of the TFT; and a die coupled to the first face of the substrate.

Abstract: A semiconductor device includes a delay code generation circuit configured to adjust a shifting code for delaying a first internal clock, by comparing phases of a second internal clock and a delayed clock, the delayed clock generated by delaying the first internal clock, and configured to generate a first delay code and a second delay code from the shifting code.

Abstract: A DC-DC converter selectively operates in at least a first burst mode having at least one first-mode charge cycle with a first-mode charging phase followed by a first-mode discharging phase or a second burst mode having at least one second-mode charge cycle with a second-mode charging phase followed by a second-mode discharging phase. A first-mode charging phase is terminated when an inductor current flowing through the inductance reaches a first-mode peak-current threshold, and a first-mode discharging phase is terminated when the inductor current reaches a first-mode valley-current threshold.

Abstract: A gate driver for a high-side NMOS power transistor in a DC/DC boost converter includes first and second switches coupled in series between an output pin and the gate of the high-side transistor. A third switch is coupled between the gate and a switch-node between the high-side and low-side transistors, the switch node also being coupled to an input pin. Fourth and fifth switches are coupled in series between the output pin and a clamp pin. Sixth and seventh switch are coupled in series between the output pin and a ground pin. First and second bootstrap capacitors have respective first terminals coupled to a first node between the first and second switches. The first capacitor has a second terminal coupled to a node between the fourth and fifth switches; the second capacitor has a second terminal coupled to a node between the sixth and seventh switches.

Abstract: Systems and methods for improving source-follower-based Sallen-Key architectures are disclosed. In particular, systems and methods for circumventing the non-idealities associated with source-follower-based Sallen-Key biquad filters when used in either baseband signal or radiofrequency paths. The systems and methods disclosed herein present power-efficient, cost-efficient solutions that can be implemented in a reduced area of a circuit.

Abstract: Provided is a gate drive circuit and a gate drive system, with which current unevenness among power devices connected in parallel can be reduced more. A gate drive circuit includes: an objective waveform generation unit configured to generate an objective waveform; a drive waveform generation unit configured to generate a drive waveform from the objective waveform, by referring to on-timing set information and off-timing set information; a drive control unit configured to drive the power device to turn the power device on/off, based on the drive waveform; a state detection unit configured to detect the state of the power device; a predicted waveform generation unit configured to generate a predicted waveform of a voltage; and an update unit configured to update the on-timing set information and the off-timing set information, based on the result of the state detection and the result of comparison to the predicted waveform.

Abstract: According to one embodiment, a first switch controls conduction between first and second nodes according to a potential on a first control node. A second switch controls conduction between the first control node and a first potential node according to a potential on a second control node. A first circuit includes first and second output nodes respectively coupled to the first and second control nodes, and outputs at the second output node a potential that brings the second switch out of conduction while outputting a first potential at the first output node. The first circuit has a high impedance at the first output node while outputting at the second output node a potential that brings the second switch into conduction.

Abstract: A system and method for controlling current-range switching to limit glitching includes a sense array connected between an input and a load. The sense array includes a parallel first and second branch circuits. The first branch circuit includes at least one first transistor, a first sense resistor, and a variable impedance control circuit. The variable impedance control circuit is configured to receive a control signal and generate a gate voltage of the at least one first transistor to establish an impedance of the sense array between the input and the load that is proportional to the control signal, including controlling the gate voltage of the at least one first transistor such that an impedance of the sense array transitions from a first value to a second value when connecting or disconnecting the first branch circuit between the input and the load while the input is connected to the load through the second branch circuit.

Abstract: An illustrative PLL circuit and method for generating a clock signal over a wide frequency range without gaps. In one illustrative embodiment, an extended-range PLL includes: a phase comparator that determines a phase error between a reference clock and a feedback clock; a loop filter that converts the phase error into a control signal; a voltage controlled oscillator (VCO) that provides a generated clock signal having a generated clock frequency determined by the control signal; a divide-by-1.5 block that produces a reduced-frequency clock signal in response to the generated clock signal; and a multiplexer that selects one of the generated clock signal and the reduced-frequency clock signal as a selected clock signal.

Abstract: A semiconductor device includes a transmission circuitry, a reception circuitry, a comparison circuitry, a timer circuitry, and a switch circuitry. The transmission circuitry converts a first signal based on an input signal into a second signal and transmits the second signal. The reception circuitry is electrically insulated from the transmission circuitry, receives the second signal, and outputs a third signal. The comparison circuitry compares a reference voltage and a comparison object signal being one of the input signal and the third signal, and outputs a fourth signal. The timer circuitry outputs, when the fourth signal shifts, a fifth signal based on timing of the shift. The switch circuitry switches and outputs the reference voltage, based on the fifth signal.

Abstract: In a power converter, a regulator that receives a first voltage couples to a switched-capacitor converter that provides a second voltage. Slew-control circuitry controls slew rate within the switched-capacitor converter during operation thereof. A controller controls the operation of both the regulator and the switched-capacitor converter.