Abstract: A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed.

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

Abstract: A switch having a drain, a source, and a control. The switch comprising a depletion-mode transistor including a first, a second, and a control terminal and an enhancement-mode transistor including a first, a second, and a control terminal. The first terminal of the depletion-mode transistor is the drain of the switch and the control of the depletion-mode transistor is coupled to the source of the switch. The control of the enhancement-mode transistor is coupled to the control of the switch, the second terminal of the enhancement-mode transistor is the source of the switch. The switch comprises a clamp circuit to clamp a voltage of the first terminal of the enhancement-mode transistor to a threshold, the clamp circuit comprises a resistor and a pn-junction device coupled between the first and second terminals of the enhancement-mode transistor and between the second terminal and the control of the depletion-mode transistor.

Abstract: A clock signal boost circuit includes a first NMOS transistor having a drain to a power terminal, a source to a first node, and a gate to a first terminal, a second NMOS transistor having a drain to the first node, a source to a GND, and a gate to a second terminal, a third NMOS transistor having a drain to the power terminal, a source to a second node, and a gate to the second terminal, a capacitor between the first node and the second node, a PMOS transistor having a source to the second node, a drain to an output terminal, and a gate to the second terminal, and a fourth NMOS transistor having a drain to the output terminal, a source to the GND, and a gate to the second terminal. The first and the third NMOS transistors are depletion type NMOS transistors.

Abstract: A load control system for a building having a lighting load, a window, and a heating and cooling system comprises a lighting control device, a daylight control device, and a temperature control device operable to be controlled so as to decrease a total power consumption of the load control system in an energy-savings mode. The energy-savings mode can be manually overridden in response to actuation of the actuator of an input control device, such that the load control system enters a manual mode for manually adjusting the loads controlled by the lighting control device, the daylight control device, and the temperature control device. The load control system is operable to automatically return to the energy-savings mode at a time after the load control system entered the manual mode.

Abstract: A dynamic capacitor circuit having a first passive capacitor, a second passive capacitor, a first terminal of the first passive capacitor and a first terminal of the second passive capacitor connected together to receive an input signal through a resistor. The input signal includes a noise signal component. An alternating current (AC) coupled inverting amplifier has an input connecting a second terminal of the second passive capacitor, the second capacitor coupling the input signal to the AC coupled inverting amplifier input. A conductive path couples an output of the AC coupled inverting amplifier to a second terminal of the first passive capacitor to balance out any noise signal component of the input AC signal at the connection. The dynamic capacitor achieves an amount of noise reduction in a reduced space without applying deep trench capacitors (DTCAP) where the DTCAP is a capacitance formed in a plane perpendicular to the substrate.

Abstract: A circuit for providing an adjustable output driver current for use in LiDAR or other similar GaN driver applications. The circuit creates an appropriate gate-to-source voltage, VGS, for a high-current GaN driver FET to obtain a desired, high slew-rate driver current, IDRV. An externally provided reference current is used to create the required VGS for the driver FET, which is stored on an external capacitor. The value of the capacitor far exceeds the relatively low input-capacitance of the GaN driver FET. When a pulse IDRV of desired value is needed, the voltage on the capacitor is impinged upon the gate of the driver FET, thereby creating the desired IDRV. The reference charging circuit replenishes any charge lost on the capacitor, so that the same desired IDRV can be obtained on the next command pulse.

Abstract: The present disclosure provides an IO circuit and an access control signal generation circuit for the IO circuit. In one implementation, the access control signal generation circuit includes: a bias module coupled with an IO port, for generating an access control signal according to an IO port signal and an IO control signal, where a voltage value of the access control signal is a maximum value of a voltage value of an IO port voltage division signal and a voltage value of the IO control signal, and the voltage value of the IO port voltage division signal is a percentage of a voltage value of the IO port signal; an access control module coupled with the bias module, the access control module configured to control cut-off or conduction when receiving the access control signal and the IO port signal and outputting a first interface signal; and a higher-selection module configured to generate a second interface signal according to an IO power source signal and the IO port signal.

Abstract: A DC-DC converter and corresponding method for transitioning between a discontinuous conduction mode, DCM, and a continuous conduction mode, CCM, wherein the DC-DC converter is configured to power a signal processing system within an integrated circuit, is provided. The method comprises receiving input data, wherein the input data is for inputting into the signal processing system; determining an amplitude of the input data; and transitioning between DCM and CCM based on the amplitude of the input data. A DC-DC converter and respective method for transitioning from CCM to DCM comprising determining an estimated current representative of an inductor current through an inductor of the DC-DC converter; and transitioning from CCM to DCM based on the estimated current, is provided.

Abstract: A switching circuit and a method for providing a switch array having an on resistance is presented. The switch array has a plurality of switches, where each switch is arranged to be in different configuration states. The states include an enabled configuration and a disabled configuration. The switching states include an on state and an off state. Each switch is held in the off state when in the disabled configuration. Control circuitry sets the switches to either the enabled configuration or the disabled configuration, and a memory element coupled to the control circuitry and arranged to store configuration data for setting the configuration state of each of the switches. The control circuitry sets the configuration state of the switches based on a signal received from the memory element. The on resistance of the switch array depends on the switching state of the switches and their individual on resistances.

Abstract: One example includes a power supply system. The system includes a switch system comprising a switch that is configured to generate a switching voltage at a switching node in response to an input voltage. The system also includes a non-linear capacitance charge-pump coupled to the switching node and being configured to provide an output current in response to the switching voltage. The output current can have an amplitude that varies non-linearly with respect to an amplitude of the switching voltage. The switch system further includes an output stage configured to generate an output voltage on an output node in response to the output current.

Abstract: A control circuit for signal sampling of an analog RF signal includes: a spectrum monitoring circuit for monitoring the analog RF signal to determine a frequency of the analog RF signal; a tunable clock source for generating a tunable sampling clock for sampling the analog RF signal; a sample clock tuning circuit for controlling the tunable clock source and selecting a sample clock frequency of the tunable sampling clock that provides a predetermined ratio between the sample clock frequency of the tunable sampling clock and a center frequency of the analog RF signal; and an Analog-to-Digital Converter (ADC) for sampling the analog RF signal using the tunable sampling clock.

Abstract: An integrated circuit (IC) including a first synchronous circuit configured to operate in synchronization with a clock signal is provided. The first synchronous circuit includes a selector including a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, and a third input terminal configured to receive a scan enable signal indicating one of a scan test mode and a function operation mode and a latch unit configured to operate as a flip-flop outputting a first output signal corresponding to the first input signal in the scan test mode and to operate as a latch outputting a second output signal corresponding to the second input signal in the function operation mode.

Abstract: A method for installing a user-upgradeable load control network includes mounting backplates to electrical junction boxes throughout a building, where at least some backplates include a cavity to interchangeably accept device control assemblies, electrical contacts, and a translatable cover to shield the electrical contacts from the cavity when translated to a closed position and to expose the electrical contacts to inserted device control assemblies. The method may further include connecting the electrical contacts to electrical loads throughout the building. The method may further include installing device control assemblies into the backplates by inserting the one or more device control assemblies and translating the respective covers to the open positions. Further, an installed device control assembly is upgradeable by translating the cover to the closed position, removing the installed device control assembly, inserting device control assembly, and translating the cover to the open position.

Abstract: A method and an electronic circuit are disclosed. The method includes driving a transistor device in an on-state by applying a drive voltage higher than a threshold voltage of the transistor device to a drive input, and adjusting a voltage level of the drive voltage based on a load signal that represents a current level of a load current through the transistor device, wherein the current level is an actual current level or an expected current level of the load current.

Abstract: Disclosed is a signal generator that includes a memory to store tuning voltage values and offset voltage values. An adder/subtractor circuit is coupled to the memory to produce a sum and a difference of the tuning and offset voltages. A comparator circuit is coupled to the adder/subtractor circuit to receive a digitized voltage controlled oscillator tuning voltage and to compare the digitized voltage controlled oscillator tuning voltage to the sum and difference of the tuning and offset voltages to produce a window bounded by the sum and difference of the tuning and offset voltages. The comparator circuit is further configured to generate control signals. A steering current circuit is coupled to the comparator circuit to receive the control signals from the comparator circuit and to control a steering current based on the control signals.

Abstract: During operation of an analog filter having one or more filter stages is configured to operate in a first configuration. Configuring the analog filter to operate in the first filter configuration includes configuring one or both of i) a filter response of the analog filter and ii) a filter bandwidth of the analog filter. A first set of one or more direct current (DC) offset correction codes corresponding to the first filter configuration are retrieved from a memory. The one or more DC offset correction codes in the first set are converted to one or more first analog DC offset correction signals. While operating the analog filter configured in the first configuration, the one or more first analog DC offset correction signals are applied to the one or more filter stages of the analog filter.

Abstract: An acoustic wave device includes a silicon oxide film, a piezoelectric body made of lithium tantalate, and interdigital transducer electrodes stacked on a supporting substrate made of silicon, in which the values of the wave length-normalized film thickness and the Euler angle of the piezoelectric body made of lithium tantalate, the wave length-normalized film thickness of the silicon oxide film, the wave length-normalized film thickness of the interdigital transducer electrodes in terms of aluminum thickness, the propagation direction of the supporting substrate, and the wave length-normalized film thickness of the supporting substrate are set such that represented by Formula (1) for at least one of responses of first, second, and third higher-order modes is more than about ?2.4, and TSi>20.

Abstract: Several embodiments include a power network system for a data center. The power network system can provide high voltage direct current (HVDC) power to server racks or any IT load racks type. For example, a HVDC converter circuit can provide the HVDC power by converting AC power. The power network system can also include multiple redundant power systems (e.g., a genset, a capacitive backup power system, a turbine-based generator system, or any combination thereof). The capacitive backup power system can provide HVDC power when the AC power fails and/or when the HVDC converter circuit can no longer provide sufficient power. The genset can be turned ON after the AC power fails. However, the genset may not provide stable power until sometime thereafter. Hence, the air turbine-based generator system can provide nearly-instant backup power once turned ON and provide supplemental energy in combination with the capacitive backup power system to smooth out transitions of power sources.

Abstract: A radio frequency switch includes a first transistor and a second transistor coupled together to establish a switchable RF path, and a first compensation network coupled between the body terminal of the first transistor and the drain terminal of the second transistor, wherein the first compensation network establishes a path for current flowing between the body terminal of the first transistor and the drain terminal of the second transistor in a first direction and blocks current flowing in a second direction opposite to the first direction.