Abstract: One embodiment of the present invention provides a system that enforces dependencies between memory references within a load store unit (LSU) in a processor. When a write request is received in the load store unit, the write request is loaded into a store buffer in the LSU. The write request may include a “watch address” specifying that a subsequent load from the watch address cannot occur before the write request completes. Note that the watch address is not necessarily the same as the destination address of the write operation. When a read request is received in the load store unit, the read request is loaded into a load buffer of the LSU. The system determines if the read request is directed to the same address as a matching watch address in the store buffer. If so, the system waits for the write request associated with the matching watch address to complete before completing the read request.

Abstract: In a memory device capable of processing a small amount of data in a high speed, this memory device is suitable for various sorts of systems in which a plurality of access requests for continuous addresses are mixed with each other, and are issued as irregular requests to a memory subsystem. A data array is provided in a memory device having a memory cell. This data array may be arranged as a virtual register array having an arbitrary number of arbitrary word length. The data register array is accessed by employing a virtual register number and a virtual word number, which are supplied from an external circuit provided outside the memory device. In the memory device, both the virtual register number and the virtual word number, which are supplied from the external circuit, are converted into both an absolute register number and an absolute word number by an internally-provided converting circuit so as to access the data register array.

Abstract: Methods for selecting a boot partition from a single drive of a computer are disclosed. In one example, a method includes receiving a boot request and accessing a signature sector of the single drive to ascertain a first serial number for a first boot partition and a second serial number for a second boot partition. The method then proceeds to scanning the single drive to identify the first boot partition using the first serial number and identify the second boot partition using the second serial number. A selection window requesting user selection of either the first boot partition or the second boot partition is then generated. The method then proceeds to modifying a boot flag of the single drive in response to the user selection, and the modifying of the boot flag is configured to identify one of the first boot partition and the second boot partition as a partition containing an operating system for booting the computer.

Abstract: The present invention relates to means, a method and a computer program product of administrating in a computer system a global data element shared by a multitude of exploiters within said computer system for reducing contention among said exploiters. It is suggested to execute a first step by a first exploiter of accumulating one or a multitude of modifications performed by said first exploiter with respect to the current contents of said global data element into a first local data element not shared by other exploiters. In a second step executed by the first exploiter a size of the accumulated modifications in the first local data element with respect to the current contents of the global data element is determined. Moreover it is determined, if said size exceeds a specified quantum. If said size exceeds the specified quantum, the global data element is updated with the accumulated modifications as new contents.

Abstract: A disk controller system includes a microprocessor, a hard disk controller, a disk channel path, a host communications path, and an interface coupled to each of the microprocessor, hard disk controller, disk channel path and host communications path. A unified non-volatile memory is coupled to the interface that has a plurality of memory spaces. A memory space is allocated for each of the microprocessor, hard disk controller, disk channel path and host communications path. Each memory space is separated from another memory space by a programmable memory space boundary. The microprocessor, hard disk controller and the unified memory are all fabricated on a single substrate.

Abstract: A multi-level cache and method for operation therefore includes a first non-blocking cache receiving access requests from a device in a processor, and a first miss queue storing entries corresponding to access requests not serviced by the first non-blocking cache. A second non-blocking cache is provided for receiving access requests from the first miss queue, and a second miss queue is provided for storing entries corresponding to access requests not serviced by the second non-blocking cache. Other queueing structures such as a victim queue and a write queue are provided depending on the particular structure of the cache level within the multilevel cache hierarchy.

Abstract: A magnetic disk processor according to the present invention includes an I/O stream monitor table and an I/O stream monitor which determines whether or not a start address of a certain I/O stream coincides with a sum of a last address of a past I/O stream stored in the I/O stream monitor table and 1 or whether or not the start address is within a range of last address of the past I/O stream plus &agr;. With this construction of the magnetic disk processor, it becomes possible to detect sequential I/O streams issued from a plurality of independent applications and mixed on an I/O channel of a host computer.

Abstract: A multiple changeable addressing mapping circuit is disclosed for converting an input logic address of a field array in a data array into an output physical address. The circuit has multiple address mappers for process the conversion between the input logical address and the output physical address. The circuit also has a mapper selector for selecting an address mapper to output physical address. The circuit further has a control and interface circuit for setting the registers in the address mapper, and controlling the address mapper and mapper selector.

Abstract: When a tape cassette is mounted, a tape drive apparatus judges whether the tape cassette is of a first mode (normal mode) or a second mode (multi-partition mode) based on one or both of management information that is read out from the magnetic tape and management information that is read out from a memory (MIC) incorporated in the tape cassette. The tape drive apparatus then an performs an operation setting in accordance with the mode thus judged.

Abstract: Provided are a system, method, program, and data structure for processing a request for data in a first format that is superimposed on blocks of data stored in a second format in a storage device. A data structure for a storage unit in the first format including the requested data is accessed. There is one data structure for each storage unit in the first format being accessed. Further, at least one cache page storing blocks of data in the second format is needed to store one storage unit in the first format. A determination is made of one or more storage blocks in the second format that include the requested data. A determination is also made as to whether the storage unit data structure includes a pointer to a control block for a cache page that would include the determined storage blocks in the second format.

Abstract: A system and method for rapidly zeroing/clearing a container in a redundant array of independent disks (RAID) provides the writing of a series of logical zeros to each disk in the container using an internal bus driver-level command. The command causes a small data block of all zeroes written to the disk to be duplicated so that the entire container space in each disk is effectively written-to. The bus driver is preferably a small computer system interface (SCSI) architecture that supports a WRITE SAME command. Where the disk device fails to support the WRITE SAME command then an alternative process is employed, in which a single large sized memory block is created and initial sized with all zeroes. A predetermined number of virtual scatter gather elements are created, each pointing to the memory block.

Abstract: An apparatus and method for accessing a cache memory. In a cache memory, an address is received that includes a set field and a partial tag field, the set field and the partial tag field together including fewer bits than necessary to uniquely identify a region of memory equal in size to a cache line of the cache memory. The set field is decoded to select one of a plurality of storage units within the cache memory, each of the plurality of storage units including a plurality of cache lines of the cache memory. The partial tag field is compared to a plurality of previously stored partial tags that correspond to the plurality of cache lines within the selected one of the plurality of storage units to determine if the partial tag field matches one of the plurality of previously stored partial tags. If the one of the previously stored partial tags matches the partial tag field, one of the plurality of cache lines that corresponds to the one of the plurality of previously stored partial tags is output.

Abstract: To achieve high performance at low cost, an integrated digital signal processor uses an architecture which includes both a general purpose processor and a vector processor. The integrated digital signal processor also includes a cache subsystem, a first bus and a second bus. The cache subsystem provides caching and data routing for the processors and buses. Multiple simultaneous communication paths can be used in the cache subsystem for the processors and buses. Furthermore, simultaneous reads and writes are supported to a cache memory in the cache subsystem.

Abstract: A partitioned cache and management method for selectively caching data by type improves the efficiency of a cache memory by partitioning congruence class sets for storage of particular data types such as operating system routines and data used by those routines. By placing values for associated applications into different partitions in the cache, values can be kept simultaneously available in cache with no interference that would cause deallocation of some values in favor of newly loaded values. Additionally, placing data from unrelated applications in the same partition can be performed to allow the cache to rollover values that are not needed simultaneously.

Abstract: A cache flush unit has an MF RAM and an MBT Tag RAM. The MBT Tag RAM stores address information, associated with modified blocks of caches of all processors, in entries in units of cache lines. The MF RAM stores, as information to be used to search for an index of one of the entries on the MBT Tag RAM, which contains an address of at least one modified block, data having a value obtained by ORing modified bits of all processors in the entries together with the index. In cache flush, the address of the modified block can be read out quickly by using the information stored in the MF RAM.

Abstract: A cooperative disk cache management and rotational positioning optimization (RPO) method for a data storage device, such as a disk drive, makes cache decisions that decrease the total access times for all data. The cache memory provides temporary storage for data either to be written to disk or that has been read from disk. Data access times from cache are significantly lower than data access times from the storage device, and it is advantageous to store in cache data that is likely to be referenced again. For each data block that is a candidate to store in cache, a cost function is calculated and compared with analogous cost functions for data already in cache. The data having the lowest cost function is removed from cache and replaced with data having a higher cost function.

Abstract: A fully-associative translation lookaside buffer structure for a computer system includes a first-level TLB0 memory having a plurality of entries and a second-level TLB1 memory operatively coupled to the first level TLB0 memory. The second-level TLB1 memory also has a plurality of entries. Entries are placed in the TLB0 and TLB1 structure as a result of software controlled translation register operations and hardware controlled translation cache operations. Logic controlling TLB0 treats both operations the same way and uses a hardware replacement algorithm to determine the entry index. Logic controlling TLB1 uses a hardware replacement algorithm to determine the entry index for translation cache entries, and use an index provided within the insertion instruction to determine the entry index for translation register operations.

Abstract: A method and apparatus for storing and utilizing set prediction information regarding which set of a set-associative memory will be accessed for enhancing performance of the set-associative memory and reducing power consumption. The set prediction information is stored in various locations including a branch target buffer, instruction cache and operand history table to decrease latency for accesses to set-associative instruction and data caches.

Abstract: A disk drive has a unified bus forming a signal path for transmitting register data, user data and servo sectors. The unified bus is connected between a channel circuit and a disk controller circuit. The channel circuit has an output stream engine which responds to and provides control signals to multiplex data on the unified bus at various times between demodulated user data, servo sector data and register data.

Abstract: One embodiment of the present invention provides a system that prefetches from memory by using an assist processor that executes in advance of a primary processor. The system operates by executing executable code on the primary processor, and simultaneously executing a reduced version of the executable code on the assist processor. This reduced version runs more quickly than the executable code, and generates the same pattern of memory references as the executable code. This allows the assist processor to generate the same pattern of memory references that the primary processor generates in advance of when the primary processor generates the memory references. The system stores results of memory references generated by the assist processor in a store that is shared with the primary processor so that the primary processor can access the results of the memory references. In one embodiment of the present invention, this store is a cache memory.