Abstract: A memory controller for a computer memory which decodes memory requests into individual primitive memory operations which are then queued into separate operation queues. The operation queues independently issue their queued primitive memory operations to the memory in order to initiate the memory request. The operation queues monitor and adhere to timing and ordering dependencies between the primitive memory operations that are queued and those that have already been transmitted to the memory. Once a primitive memory operation is transmitted to the memory, it is dequeued from its respective operation queue. A control queue monitors the progress of the primitive memory operations transmitted to the memory, completes the initiated memory request and provides timing and ordering dependency data to the operation queues.

Abstract: A memory paging method and apparatus using a memory paging register and a memory paging mask register. The invention has particular application in the partition of memory used by more than one software application program. The bits of the memory paging mask register selectably disable bits of the memory paging register to redefine the length and physical characteristics of pages in memory based on the needs of a software program. As a result, the paged partitions in memory may be of variable length and/or may comprise non-contiguous portions of the memory.

Abstract: The present invention provides for a method and an apparatus for encoding coherency tag information for a plurality of busses. A first processor bus is coupled to a host controller. A second processor bus is coupled to a host controller. The host controller is coupled to a single coherency tag bank. Coherency tag data from the first processor bus and the second processor bus is stored into the coherency tag bank. A location of a data set sought by the first processor and the second processor is determined using the coherency tag data.

Abstract: A cache memory device by which a processing speed can be elevated and which comprises a primary cache memory containing two primary ways of WAY0 and WAY1 each retaining a bit LRU0 and a bit LRU1 taking either a value 0 or 1 together with data and an address, a primary old way determining circuit for determining, on the basis of patterns of the bit LRU0 and the bit LRU1, which is an old way retaining data which has not been accessed for the longest period of time in the primary ways WAY0 and WAY1, and a primary cache control circuit inverting only the bits (the bit LRU0 or the bit LRU1) retained in the old way which has been accessed.

Abstract: A direct memory access (DMA) controller provides seven DMA channels configurable for a PC/AT compatible mode or an enhanced mode. In an enhanced mode of the DMA controller, three DMA master channels on a master DMA controller and a DMA channel on a slave DMA controller are individually configurable to be either 8-bit or 16-bit DMA channels. In addition, in the enhanced mode, a memory address can increment or decrement across a memory page boundary. The DMA controller includes a transfer count register selectively configured for 16-bit operation or 24-bit operation. The DMA controller also includes address generation logic selectively configured for 24-bit operation or 28-bit operation. In the PC/AT compatible mode, the DMA controller supports three 16-bit channels and four 8-bit channels. The DMA controller thus provides DMA channel width configurability.

Abstract: The invention relates to a device for testing a reprogramable non-volatile memory having dedicated areas protectable in reading, writing and/or erasing and whose access rights consist of configuration words (MC) saved in a configuration area of the memory, said device comprising message transmission/reception means (10) and a received message logic control unit (11) and access controls to the memory, characterized in that it comprises at least one temporary register ensuring an emulation of these access rights, so as to render access protections reversible or irreversible. The invention also relates to the process performed by said device.

Abstract: An adaptive cache coherent purging protocol includes recognizing system performance, especially latency, is affected by when cache is purged. The occurrence of performance enhancing and degrading events regarding a cache are counted and compared to a threshold. When the threshold is triggered the cache becomes a candidate for purging. In an embodiment, a time out delay is implemented before actual purging occurs. When the threshold is not triggered but a cache event occurs, a fake time out delay is triggered and the count is adaptively either raised, lowered or set to zero in response to performance enhancing and/or degrading events. The effect is to make the actual purging more likely if the history of cache events indicates that the performance would be enhanced thereby or less likely if the history indicates that the performance would be degraded thereby.

Abstract: A drive apparatus wherein a plurality of media each including a memory element can be successively accessed to continuously write and/or read out data into and/or from the media includes a loading device for loading a plurality of storage media such that data are individually written into and/or read out from the storage media, an accessing circuit for accessing the storage media loaded in the loading circuit to write and/or read out the data into and from the storage media, and a controller for controlling, when the plurality of storage media are loaded in the loading circuit, the accessing circuit to continuously perform writing into and/or reading out from the plurality of storage media loaded in the loading circuit.

Abstract: An addressable memory device for storing blocks of varying length, utilizes a write pointer (18) to indicate the address of the next location to which data are to be written and an erase pointer (16) to indicate the address of the next location from which data are to be erased. It has a sector header (20) appended to each group of data containing information (38) indicating the length of the corresponding sector of data, and the location stored by the write pointer (14), which is selected to ensure that there is always at least one erased block adjacent to the current write block.

Abstract: Software executing in a hard disk drive's host computer system increases the perceived efficiency and performance of the hard disk drive. The host computer system implements a “virtual disk” that models physical parameters associated with the actual hard disk drive, such as seek time and physical location of the read/write heads. These parameters are used to implement host based disk drive optimization techniques such as command reordering and read-on-arrival commands.

Abstract: The invention, in one embodiment, is a method of operating a synchronous memory device generally comprising providing a clock signal to the synchronous memory device to time the operation thereof and adapting the timing of at least one of reads from and writes to the synchronous memory device to improve timing parameters for the operation thereof.

Abstract: A middle-tier Web server with a queryable cache that contains items from one or more data sources. Items are included in the cache on the basis of the probability of future hits on the items. When the data source determines that an item that has been included in the cache has changed, it sends an update message to the server, which updates the item if it is still included in the cache. In a preferred embodiment, the data source is a database system and triggers in the database system are used to generate update messages. In a preferred embodiment, the data access layer determines whether a data item required by an application program is in the cache. If it is, the data access layer obtains the item from the cache; otherwise, it obtains the item from the data source. The queryable cache includes a miss table that accelerates the determination of whether a data item is in the cache. The miss table is made up of miss table entries that relate the status of a data item to the query used to access the data item.

Abstract: When a primary data storage subsystem receives updates for local storage and mirroring at a counterpart secondary storage subsystem, the primary subsystem institutes device-specific, fairness-driven update blocking to avoid overrunning the primary subsystem's update buffer with updates destined for any one device. Broadly, the primary subsystem first receives update requests, then logs the updates in an update buffer, then stores the logged updates in primary storage, and finally copies the updates to the secondary storage subsystem. Each update request includes update data and also identifies a targeted logical device, physical device, or other subpart of primary storage. The primary subsystem maintains a counter or other update activity indicator that represents update activity for each storage subpart, such as the number of updates stored in the buffer. For each update request, the primary subsystem determines whether target subpart's update activity exceeds a prescribed level.

Abstract: A system and method for replacing cached data for a computer system utilizing one or more storage devices is disclosed. The storage devices are divided into a plurality of areas or bins. Each bin is preferably the same size. A Bin Access Table (BAT) is an array stored in memory that contains a frequency value for each bin corresponding to the number of times that the bin has been accessed during a predetermined time period. The BAT also contains a time stamp for each bin corresponding to the time that the bin was last accessed. A hot spot algorithm is used to calculate a hot spot factor or value hsf(x) for each bin based on its associated frequency value listed in the BAT. The frequency values may be weighted based on the time the bin was last accessed. Each line in cache will therefore correspond to a specific bin for which a time weighted hotspot factor hsf(x) has been calculated. These time weighted hot spot values are be stored in a hot spot table.

Abstract: According to an embodiment of the invention, a processor comprises a register file and a register stack engine. The register file has a predetermined size and a set of registers in the register file is allocated when a function in a code sequence is called. The register stack engine saves the contents of a set of registers in a reserve storage area responsive to a function call if the function call would overflow the predetermined size of the register file. The register stack engine restores data from the reserve storage area to the register file if a recursive function call occurs.

Abstract: A signal processing apparatus in which an LSI includes a memory and a plurality of blocks for making access to the memory is provided with a trace control block 170 for tracing in a specific region of the memory the history of access by a required memory access block based on a setting by a microcomputer 110 so as to allow easy analysis of the cause in the event a trouble. Also, a quasi mediation block 180 is provided in a mediation block 150, which accepts a memory use request signal from other memory access block while tracing of access history is being performed and sends back a memory use approval signal without actually making access to an internal memory 160. In the event of a trouble, an analysis of the cause can be easily made by reading a specific tracing region of the internal memory 160 out from outside.

Abstract: A data processing apparatus is embodied in a single integrated circuit. The data processing apparatus includes a central processing unit, at least one level one cache, a level two unified cache and a directly addressable memory. The at least one level one cache preferably includes a level one instruction cache temporarily storing program instructions for execution by the central processing unit and a level one data cache temporarily storing data for manipulation by said central processing unit. The level two unified cache and the directly addressable memory are preferably embodied in a single memory selectively configurable as a part level two unified cache and a part directly addressable memory. The single integrated circuit data processing apparatus further includes a direct memory access unit connected to the directly addressable memory and adapted for connection to an external memory. The direct memory access unit controls data transfer between the directly addressable memory and the external memory.

Abstract: A disk storage apparatus includes a logical unit number correspondence memory for storing the correspondence and the logical unit number designated by a host computer and the logical unit number of the disk storage apparatus, a logical unit number conversion program for converting the logical unit number designated by the host computer to the logical unit number of the disk storage apparatus, and a logical unit correspondence setting program for storing the correspondence of the logical unit number designated by the host computer to the logical unit number of the disk storage in the logical unit number correspondence memory thereby, a plurality of host computers sharing at least one disk storage apparatus.

Abstract: An apparatus and method for efficiently transferring a plurality of segmented data with various sizes. An address translation storage unit stores an address translation table which provides a plurality of translation descriptor domains to support a plurality of translation step sizes. Depending on the segment size of each data block to be transferred, a translation descriptor domain selection unit chooses a suitable translation descriptor domain within the address translation table. Data segment mapping is then performed with translation descriptors in the selected translation descriptor domain.

Abstract: During a compressing portion, memory (20) is divided into cache line blocks (500). Each cache line block is compressed and modified by replacing address destinations of address indirection instructions with compressed address destinations. Each cache line block is modified to have a flow indirection instruction as the last instruction in each cache line. The compressed cache line blocks (500) are stored in a memory (858). During a decompression portion, a cache line (500) is accessed based on an instruction pointer (902) value. The cache line is decompressed and stored in cache. The cache tag is determined based on the instruction pointer (902) value.