Abstract: Specific alloys, in particular Ni-based alloys, that can be biaxially textured, with a well-developed, single component texture are disclosed. These alloys have a significantly reduced Curie point, which is very desirable from the point of view of superconductivity applications. The biaxially textured alloy substrates also possess greatly enhanced mechanical properties (yield strength, ultimate tensile strength) which are essential for most applications, in particular, superconductors. A method is disclosed for producing complex multicomponent alloys which have the ideal physical properties for specific applications, such as lattice parameter, degree of magnetism and mechanical strength, and which cannot be in textured form. In addition, a method for making ultra thin biaxially textured substrates with complex compositions is disclosed.

Abstract: A germanium layer 19 is melted on top of a starting polycrystalline silicon ingot 18, at a temperature below the melting point of pure silicon. Silicon is dissolved at the interface and floats to the top of the germanium melt to form a silicon melt layer 11, from which a crystal 20 can be drawn. The process permits the production of large diameter crystal with low oxygen content and no more than one percent germanium.

Abstract: In a dual-damascene processes for multi level interconnection a method for forming trenches and vias in the inter-insulation is accomplished without etching out the inter-insulation layer. A thick sacrificial layer is first deposited and reversed etched to form sacrificial pillars 64 forming the vias and sacrificial bridges 72 forming the trenches. The sacrificial layer can be any material (insulator, semiconductor, or metal), provided it can be easily patterned and selectively removed later over the inter insulator layer. Thereafter a low-k inter-insulation layer is deposited around the sacrificial pillars and bridges. It is these sacrificial pillars and bridges that are etched away leaving behind vias and trenches in the inter-insulation layer. An advantage of the invention is that it replaces a difficult RIE process of vias and trenches with a much easier RIE of sacrificial pillars and bridges.

Abstract: A modified chemical-mechanical polishing apparatus is described. The apparatus includes: (i) a polishing pad 104 providing a surface against which a surface of an integrated circuit substrate 116 is polished; (ii) an anode 103 on which the polishing pad is secured, the anode including an electrolyzable conductive material; and (iii) a voltage source 106 electrically connecting the anode to the integrated circuit substrate in such a way that when a voltage is applied from the voltage source in the presence of slurry 114 admixed with an electrolyte composition on the polishing pad, an electrolytic cell results in which the conductive material deposits on the surface of the integrated circuit substrate. A process of depositing a conductive material on and polishing a surface of an integrated circuit substrate simultaneously is also described.

Abstract: Nanocrystalline phosphors are formed within a bicontinuous cubic phase. The phosphors are doped with an optimum concentration, of manganese, for example, corresponding to about one or less dopant ions per phosphor particle.

Abstract: Bulk, low impurity aluminum nitride:silicon carbide (AlN:SiC) alloy single crystals are grown by deposition of vapor species containing Al, Si, N and C on a crystal growth interface.

Abstract: A method for manufacturing a semiconductor device on a wafer that has a substrate with a front side and a backside, and an accumulation of waste matter on the backside of the substrate. In a method of the invention, a covet layer is deposited over the front side in a normal coating step of a process for fabricating a component on the wafer. The cover layer provides material used in the process for fabricating the component on the front side of the wafer and creates a barrier over the front side. The waste matter is removed from the backside of the wafer by etching the waste matter from the backside of the wafer with a suitable etchant, or by planarizing the backside of the wafer with a chemical-mechanical planarization ("CMP") process. During the removal step, the cover layer protects the front side and any device features on the front side from being damaged while the waste matter is removed from the backside of the wafer.

Abstract: A system and method for forming spherical semiconductor crystals is disclosed. The system includes a receiver tube 18 for receiving semiconductor granules 104. The granules are then directed to a chamber 14 defined within an enclosure 20. The chamber maintains a heated, inert atmosphere with which to melt the semiconductor granules into a molten mass. A nozzle, 40, creates droplets from the molten mass, which then drop through a long drop tube 16. As the droplets move through the drop tube, they form spherical shaped semiconductor crystals 112. The drop tube is heated and the spherical shaped semiconductor crystals may be single crystals. An inductively coupled plasma torch positioned between the nozzle and the drop tube melts the droplets, but leaving a seed in-situ. The seed can thereby facilitate crystallization.

Abstract: A method of forming a plurality of contact holes 70 in a semiconductor wafer uses a single step. The semiconductor wafer includes a dielectric layer 69 overlying a silicon substrate 51, a silicon nitride layer 67a, and a silicon oxynitride layer 63c. First, a photoresist 68 layer is developed on the dielectric layer. Prior to forming the dielectric layer, the silicon oxynitride layer is formed overlying a first conductive layer, and the silicon nitride layer is formed overlying a second conductive layer. Second, an etching step is performed to etch through the silicon oxynitride layer, the silicon nitride layer, a portion of the dielectric layer above the silicon oxynitride layer, and the silicon nitride layer to expose the silicon substrate 51, the first conductive layer 63a, and the second conductive layer 67c. The etching recipe includes a first chemistry and a second chemistry. The first chemistry includes C.sub.2 F.sub.6, C.sub.4 F.sub.8, CH.sub.3 F, and Ar.

Abstract: The present disclosure pertains to our discovery that the use of a particular combination of etchant gases results in the formation of a substantially flat etch front for polysilicon etching applications. In general, the process of the invention is useful for controlling the shape of the etch front during the etchback of polysilicon. Typically, the process comprises isotropically etching the polysilicon using a plasma produced from a plasma source gas comprising a particular combination of reactive species which selectively etch polysilicon. The plasma source gas comprises from about 80% to about 95% by volume of a fluorine-comprising gas, and from about 5% to about 20% by volume of an additive gas selected from a group consisting of a bromine-comprising gas, a chlorine-comprising gas, an iodine-comprising gas, or a combination thereof. One preferred mixture is SF.sub.6, Cl.sub.2 and HBr.

Abstract: A new method of recycling a spin-on-glass control wafer by removing spin-on-glass residue from the control wafer surface is described. A silicon control wafer is provided having a spin-on-glass layer coated thereon. The spin-on-glass layer is removed using a hydrofluoric acid dip wherein a silk-like spin-on-glass residue 15 remains on the silicon control wafer surface. The silicon control wafer surface is cleaned with a Caro's dip whereby the spin-on-glass residue is removed. Thereafter, the silicon control wafer can be reused.

Abstract: This invention anneals a vertical stack of two or more groups of unseparated wafers, with approximately 10 wafers in each group. The invention makes it possible to anneal more wafers in a single annealing operation under a variety of conditions, including: oxygen outer diffusion annealing to form a denuded zone; annealing to control bulk micro defects and provide intrinsic gettering functions; annealing to enhance gate oxide integrity by eliminating crystal-originated particles from the wafer surface and internal grown-in or as-grown defects; and suppression of dislocation and slip in elevated temperature environments.

Abstract: A flat selective silicon epitaxial thin film in which facet formation and loading effect are suppressed is grown by using a conventional LPCVD system which does not require an ultrahigh vacuum environment. Raw material gases for film formation and atomic hydrogen formed in an atomic hydrogen formation chamber 2 installed separately from a reaction chamber is introduced into the reaction chamber, at a growth temperature in the range of 750-900.degree. C. and under a reaction chamber pressure in the range of 1-30 Torr.

Abstract: A crystal plate 1 is grown in a continuous process by first purifying a crystal source material, a crystal melt or powder, in a purification station 3. Valves 7 control the flow of purified crystal melt or source powder 9 to a first hot zone 11, whose temperature is above the melt temperature of the crystal. A dopant source 17 with controller 19 provides dopant to the liquefied crystal 15. The first heater zone 21 surrounding the first hot zone 11 heats the crystal above its melting temperature. The second heater zone 27 produces a temperature in the second zone which is below the melt temperature of the crystal. The liquefied crystal, the liquid solid interface and the first portion of the crystal are supported in a boat-shaped crucible container with a bottom 31 and side walls. As the crystal leaves the support plate 31 it passes on to a conveyor 33. The crystal moves within an enclosure 43, which has a noble gas or noble gas and reactant gas atmosphere 45.

Abstract: An apparatus for etching a glass substrate includes a first bath 13 containing an etchant, at least one porous panel 15 having a plurality of jet holes 16 in the first bath, the porous panel containing the etchant to jet the etchant against the glass substrate 30, a container 20 storing the etchant, and a pump 24 supplying the etchant from the container to the porous panel, the pump being connected to the container and the porous panel.

Abstract: This is a device and method of forming such, wherein the device has an amorphous "TEFLON" (TFE AF) layer. The device comprising: a substrate; a TFE AF 44 layer on top of the substrate; and a semiconductor layer 42 on top of the TFE AF 44 layer. The device may be an electronic or optoelectronic device. The semiconductor layer may be a metal or other substance.

Abstract: A method of fabricating a silicon semiconductor discrete wafer is disclosed that assures excellent finishing accuracy and productivity. The method for fabricating a discrete wafer having a double-layer structure including an impurity diffused layer at one side and an impurity non-diffused layer at the opposite side includes cutting a wafer, having one of the impurity diffused layers formed on both surfaces of the silicon semiconductor wafer and having an oxide film formed on the surface of the diffused layer, into two pieces at the center of thickness with an ID saw slicing machine. Then, both surfaces of the cutting surface are ground to a predetermined thickness with a surface grinding machine, and the grinding surfaces are lapped with abrasive grains having a count of at least #2000 and no more than #6000. The processing surface is wet-etched as the final processing.

Abstract: Novel magnesium dialkylaluminum alkoxide derivative represented by Mg[(.mu.--OR').sub.2 AlR.sub.2 ].sub.2 wherein R and R' are each a C.sub.1-5 alkyl group and R is not the same as R', preferably magnesium dimethylaluminum isopropoxide, is easily prepared by reacting a trialkylaluminum with an alcohol or an aluminum trialkoxide to obtain a dialkylaluminum alkoxide; reacting the dialkylaluminium alkoxide with an alkali metal alkoxide to obtain an alkali metal dialkylaluminum alkoxide; and reacting the alkali metal dialkylaluminum alkoxide with a magnesium halide. The alkoxide derivative of the present invention can be vaporized at a low temperature, below 70.degree. C. and, therefore, effectively employed in the CVD process of a magnesium aluminate film.

Abstract: The first pipe 34 delivers the first solution 21 containing polishing particles. The second pipe 37, containing a liquid mass flow unit 36, delivers the second solution containing a chemical substance. The outlet port of the first pipe and the outlet port of the second pipe are connected to one end portion of the third pipe 31. The third pipe has the other end portion with an inner diameter almost equal to the inner diameter of its one end portion. The first and second solutions introduced into the third pipe are mixed in the third pipe to generate a polishing liquid. The generated polishing liquid is supplied from the other end portion of the third pipe onto a polishing pad 13 to polish a semiconductor wafer 16.

Abstract: Pure silicon feedstock is melted and vaporized in a physical vapor transport furnace. In one embodiment the vaporized silicon 46 is reacted with a high purity carbon member 74, such as a porous carbon disc, disposed directly above the silicon. The gaseous species resulting from the reaction are deposited on a silicon carbide seed crystal 50 axially located above the disc, resulting in the growth of monocrystalline silicon carbide 56. In another embodiment, one or more gases, which may include a carbon-containing gas, are additionally introduced at 84 into the furnace, such as into a reaction zone above the disc, to participate in the growth process.