Abstract: A stress-free wafer comprising a substrate formed of a semiconductor material having front side and back side planar and parallel surfaces and having a thickness ranging from 2 to 7 mils. The front side has electronic circuitry therein with exposed contact pads. The back side is ground and polished so that the wafer is substantially stress free and can withstand bending over a 2" radius without breaking or damaging.

Abstract: A plurality of substrates is closely stacked together in a Rapid Thermal Processing (RTP) chamber, and the stack is processed simultaneously.

Abstract: A pixelated image sensor having comprising a partially pinned photodiode which is formed a semiconductor of a first conductivity type formed on a surface of the sensor with at least one photodiode formed, within the semiconductor near the surface, the photodiode being formed from a second conductivity type opposite the first conductivity type; a pinning layer formed on the surface over at least a portion of the photodiode creating a pinned photodiode region, the pinning layer being formed from the first conductivity type; and an unpinned region formed near the surface in an area outside the portion used to form the pinning layer, the unpinned region is formed as a floating region that is employed as a capacitor. The partially pinned photodiode is useful in expanding the fill factor of photodetectors employing photodiode technology.

Abstract: An improved FET for use as a voltage-controlled resistor includes a p-type control gate and a high-resistance connection to receive a control signal. The bootstrap frequency for the device is much lower than the signal frequency so that the signal frequency is decoupled from the control voltage to reduce distortion.

Abstract: A method for manufacturing a buried-channel pMOSFET device that utilizes a plasma doping technique to form a very shallow P-type channel layer on the top surface of a sub-micron buried-channel pMOSFET. The buried-channel pMOSFET device formed by the method has a higher current drivability and a higher anti-punchthrough resistance.

Abstract: An integrated circuit sensor structure. The integrated circuit sensor structure includes a substrate which includes electronic circuitry. An interconnect structure is adjacent to the substrate. The interconnect structure includes conductive interconnect vias which pass through the interconnect structure. A dielectric layer is adjacent to the interconnect structure. The dielectric layer includes a planar surface, and conductive dielectric vias which pass through the dielectric layer and are electrically connected to the interconnect vias. The dielectric layer further includes an interlayer planarization dielectric layer adjacent to the interconnect structure, and a passivating layer adjacent to the interlayer planarization dielectric layer. The integrated circuit sensor structure further includes sensors adjacent to the dielectric layer. The interconnect vias and the dielectric vias electrically connect the electronic circuitry to the sensors.

Abstract: A method and apparatus for detecting scratches on a wafer surface. The method comprises the use of a monitor wafer which has a substrate, a first layer deposited on the substrate, and a second layer deposited on the first layer. The first and second layers have contrasting work functions such that when short wavelength light is directed on the monitor wafer, scratches through the second layer can be detected.

Abstract: Electron emitters and a method of fabricating emitters which have a concentration gradient of impurities, such that the highest concentration of impurities is at the apex of the emitters, and decreases toward the base of the emitters. The method comprises the steps of doping, patterning, etching, and oxidizing the substrate, thereby forming the emitters having impurity gradients.

Abstract: A submicron level dimension reference for use with a scanning electron microscope in a semiconductor device fabrication apparatus. The reference has a first insulating layer with a first pattern formed on a semiconductor wafer substrate. A plurality of contacts are formed between the first pattern of the first insulating layer such that the contacts directly communicate the wafer substrate. The contacts are capable of carrying an electrical charge. An electrically conductive layer is formed over the contacts and the first insulating layer. A second insulating layer with a second pattern is formed over the conductive layer. Electrical charges generated by radiating the scanning electron microscope on the submicron level dimension reference are transferred from the first and second insulating layers to the wafer substrate via the conductive layer and the plurality of contacts.

Abstract: A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of .delta., includes preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p- well in the substrate; isolating plural device areas on the substrate; forming a FE gate stack surround structure; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2.gtoreq.L1+2.delta.; depositing a first insulating layer over the structure; implanting arsenic or phosphorous ions to form a source region and a drain region; annealing the structure; depositing a second insulating layer; and metallizing the structure.

Abstract: A method for forming a sub-quarter micron MOSFET having an LDD structure is described. An active area is provided in a semiconductor substrate separated from other active areas by isolation regions. Ions are implanted into the semiconductor substrate in the active area wherein a heavily doped region is formed adjacent to the surface of the semiconductor substrate and wherein a lightly doped region is formed underlying the heavily doped region. A first dielectric layer is deposited overlying the semiconductor substrate in the active area. The first dielectric layer is etched away to form an opening to the semiconductor substrate. The semiconductor substrate within the opening is etched through to form a partial trench in the semiconductor substrate. Spacers are formed on the sidewalls of the first dielectric layer within the opening. A layer of conducting material is deposited over the first dielectric layer and the spacers and within the opening.

Abstract: Method for implementing a multi-phase plastic package for electronic components, and packaged electronic components produced according to the method. The principles of the present invention contemplate electrostatically depositing an exceptionally uniform coating on electronic components, especially microchips, and more especially still, on integrated circuits prior to the encapsulation of the electronic components into plastic-packaged components. The coating, for instance applied to a completed leadframe assembly, including die and wire bonds, serves two purposes. It improves adhesion of the molding compound forming the package, thereby reducing the chances for delamination of the package. The coating also isolates the relatively fragile wire bonds, including their attachment points to the chip and the bonding pads and the leads, from chemical and metallurgical attack by the flame retardant found in many molding compounds.

Abstract: A semiconductor device includes a bias circuit for applying a bias to a transistor in which the semiconductor comprises a two-terminal element, connected between an external power source and at least an input of the transistor, having a first conductive contact layer connected to the input of the transistor, a second conductive contact layer connected to the external power source, and a semiconductor layer having a semi-insulation intervened between the first and second conductive contact layers, thereby reducing the thermal runaway caused by temperature rise.

Abstract: A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N- LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.

Abstract: Field effect transistors having tapered gate electrodes include a body region of first conductivity type extending to a surface of a semiconductor substrate. Source and drain regions of second conductivity type are formed in the substrate and a gate electrode is formed on a portion of the surface extending opposite the body region and between the source and drain regions. A gate electrode insulating layer is also disposed between the gate electrode and the surface. To improve the transistor's withstand voltage capability by reducing field crowding, the gate electrode insulating layer is preferably formed to have a tapered thickness which increases in a direction from the source region to the drain region, and to reduce on-state resistance the drain region is formed in a self-aligned manner to the gate electrode.

Abstract: The boundary between the P type silicon base and N.sup.+ buffer layer of an IGBT is intentionally damaged, as by a germanium implant, to create well defined and located damage sites for reducing lifetime in the silicon.

Abstract: The invention relates to a semiconductor configuration for integrated circuits, in which a stacked cell has a contact hole filled with a plug in an insulating layer, a capacitor having a lower electrode, which faces the plug, a paraelectric or ferroelectric dielectric and an upper electrode being provided on the contact hole. A barrier layer is situated between the plug and the lower electrode and is surrounded by a silicon nitride collar, which reliably prevents oxidation of the barrier layer.

Abstract: A fabrication method of a semiconductor laser capable of controlling a polarization mode of output light is disclosed. In the fabrication method, after two laser portions are independently formed, the laser portions are positioned to be optically coupled to each other. In another fabrication method of the laser, after at least portions of two laser portions are separately formed, an irregularly-formed portion at a boundary portion therebetween is removed. The fabrication method can be facilitated and a degree of freedom in the polarization control can be increased, since the two laser portions are separately formed.

Abstract: A method for manufacturing chip stacks in which wafers are stacked one on top of the other. The wafer is provided with an adhesive foil on its bottom, and is subsequently cut into chips so that the adhesive foil remains intact and the chips adhering to the adhesive foil are stacked one on top of the other. A first layer of chips is reversibly attached to a baseplate, the adhesive foil is removed, the next layer of chips is attached to the bottom side of the chips already fastened to the baseplate, the adhesive foil is removed, and the last two steps are repeated until the desired number of chips is stacked one on top of the other.

Abstract: A transistor formed in a semiconductor substrate having improved ESD protection is disclosed. The transistor includes a first ESD implant formed underneath the source region and the drain region of the transistor. The first ESD implant has the same impurity type as the source region and the drain region. Further, a second ESD implant is formed underneath the first ESD implant, the second ESD implant having an impurity type opposite to that of said first ESD implant. The second ESD implant also is spaced apart vertically from the first ESD implant.