Abstract: A photodiode structure augmented with active area photosensitive regions is used for detecting impinging radiation. The photodiode includes a semiconductor base layer doped with impurities of a first carrier type, a field oxide layer disposed upon the base layer with an opening formed therethrough, a plurality of auxiliary oxide layers wherein each is separately disposed upon the base layer, and a semiconductor diffusion layer doped with impurities of a second carrier type arranged upon the base layer and in contact with the oxide layers. When the photodiode is electrically energized, a plurality of integral photosensitive regions is created within the depletion region to facilitate the detection of impinging radiation at an increased quantum efficiency.

Abstract: The present invention relates to a pixel cell and pixel cell array modified to improve performance. One improvement taught by the present invention is implantation of dopant into the silicon to form the base region after formation of polysilicon, resulting in highest base dopant concentrations lying at the thin oxide and emitter interfaces. A second improvement taught by the present invention is a reduction in the size of the heavily doped portion of the emitter to extend no further than the footprint of the emitter contact, thereby inhibiting leakage between the emitter and adjacent polysilicon. A third improvement taught by the present invention is electronic isolation of pixel cells by inter-pixel regions doped with conductivity-altering impurity of a type opposite that of the base rather than by field oxides, thereby eliminating leakage at the field oxide edge.

Abstract: Method and apparatus for improving the high current operation of bipolar transistors while minimizing adverse affects on high frequency response are disclosed. A local implant to increase the doping of the collector at the collector to base interface is achieved by the use of an angled ion implant of collector impurities through the emitter opening. The resulting area of increased collector doping is larger than the emitter opening, which minimizes carrier injection from the emitter to the collector, but is smaller than the area of the base.

Abstract: A multi-layered structure is fabricated in which a microprocessor is configured in different layers and interconnected vertically through insulating layers which separate each circuit layer of the structure. Each circuit layer can be fabricated in a separate wafer or thin film material and then transferred onto the layered structure and interconnected.

Abstract: A semiconductor device which is applied to access transistors of an SRAM cell to improve its operation performance and a method for fabricating the same are disclosed. The semiconductor device includes a gate insulating layer formed on a semiconductor substrate, a gate electrode formed on the gate insulating layer, lightly doped impurity regions having different lengths beneath surface of the semiconductor substrate at first and second sides of the gate electrode, and heavily doped impurity regions formed beneath the surface of the semiconductor substrate, extending from the lightly doped impurity regions.

Abstract: A silicon island portion is formed in a quantum wire so as to be sandwiched between a pair of tunnel barrier portions of a silicon oxide film. On one side of the silicon island portion, a gate electrode for potential control is disposed with a gate insulating film of a silicon oxide film interposed therebetween. On the other side of the silicon island portion, a control electrode for potential control is disposed with an insulating film of a silicon oxide film interposed therebetween. Each of the tunnel barrier portions has a quantum wire constriction structure, which is formed by oxidizing a quantum wire, i.e., a silicon oxide film formed as a field enhanced oxide film with an atomic force microscope or the like, from its surface to a substantially center portion in its section.

Abstract: A method of precisely measuring electrical parameters in integrated circuits in a face down semiconductor device in which a portion of the semiconductor substrate is removed from the semiconductor device and an SEM microprobe is directed onto selected regions of the surface exposed by the removal of the semiconductor substrate. The microprobe is directed to selected regions of the exposed surface by a computer generated mapping system. One of the selected regions that the microprobe is directed to is a region of the exposed surface overlying a depletion region associated with a drain of a transistor in the semiconductor device. The voltage variation on the exposed surface caused by the expansion and shrinking of the depletion region is measured by the microprobe. Another region that the microprobe is directed to is a region of the exposed surface overlying an insulator and the microprobe detects the voltage of a conducting electrode under the insulator is measured via capacitive coupling.

Abstract: An ultra high density flash EEPROM provides increased nonvolatile storage capacity. A memory array includes densely packed memory cells, each cell having a pillar of semiconductor material that extends outwardly from a working surface of a substrate. The pillar includes source/drain and body regions and has a number of sides. A pair of vertically stacked floating gates is included on at least one of two sides of the pillar. A control gate line also passes through each memory cell. Each memory cell is associated with a control gate line so as to allow selective storage and retrieval of data on the floating gates of the cell. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data, an area of only F.sup.2 is needed per bit of data, where F is the minimum lithographic feature size. If multiple charge states (more than two) are used, an area of less than F.sup.2 is needed per bit of data.

Abstract: A MOS type semiconductor device is provided which includes a series Zener diode array for overvoltage protection, which is provided between source regions and an electrode having substantially the same potential as a drain electrode, and a field insulating film on which the series Zener diode array is provided. The thickness T (.mu.m) of the field insulating film is determined as a function of the clamp voltage V.sub.CE (V) of the series Zener diode array, such that the thickness T is held in the range as represented by: T.gtoreq.2.0.times.10.sup.-3 .times.V.sub.CE. The width W.sub.1 (.mu.m) of a portion of a second-conductivity-type isolation well that is close to the field insulating film on which the series Zener diode array is provided, and the width W.sub.2 (.mu.m) of a portion of the second-conductivity-type isolation well that is close to the field insulating film on which the series Zener diode array is not provided, are determined as a function of the clamp voltage V.sub.

Abstract: The method of the present invention includes patterning a gate structure. Then, a polyoxide layer is formed on side walls of the gate structure. Then, silicon nitride side wall spacers is formed on the side walls of the gate structure. Then, source/drain structure of the device is fabricated. Next, the side wall spacers is removed to expose a portion of the source and drain. Then, an undoped amorphous silicon layer is formed on the surface of the gate structure, the oxide layer and the exposed source and drain. A dry oxidation process is used to convert the amorphous silicon layer into textured tunnel oxide at the interface of the substrate and the oxide. Polysilicon side wall spacers are then formed. A further polysilicon layer is subsequently deposited over the gate. Then, the polysilicon layer is patterned to define the floating gate. A dielectric is formed at the top of the floating gate. A conductive layer is formed on the dielectric layer as control gate.

Abstract: A three dimensional ferroelectric memory device formed on a semiconductor substrate has insulative material formed between rows of conductors to reduce cross talk between the conductors. Access circuitry or other circuitry is formed beneath the three dimensional structure. Continuous conductors, or staggered vias provide for connection to conductors forming the memory cells. An access circuit is provided which eliminates the need for an access transistor for each memory cell by using a memory cell with a reference cell in combination with sensing circuitry. Read cycles are followed by write cycles and an equilibrate cycle to reverse the effects of destructive reads on the memory cells. Side by side memory structures provide the ability to access using either a folded or open bit line circuit.

Abstract: A method for manufacturing an organic EL display including an organic EL elements and an organic field effect transistors being integrated on a same substrate is disclosed. A semitransparent electrode layer of the organic EL element and a gate electrode of the organic transistor are formed on a same transparent plastic substrate. An organic gate insulating layer is deposited on the gate electrode and an organic semiconductor layer is formed on the organic gate insulating layer. A source and drain electrodes is formed on the organic semiconductor layer. An organic EL layer is formed on the semitransparent electrode layer and a part of the drain electrode. The organic semiconductor layer can be made of a charge transfer complex or a thiophene derivative polymer. The resultant EL device is capable of mechanically bent, and then is readily adaptable for use in flexible displays.

Abstract: A structure color sensor of a diode includes following: Firstly, a color sensor layer including a number of color sensor areas is formed on a substrate for absorbing and sensing the different color light. Then, a black matrix film covered by a transparent planarization film is on the color sensor layer by using dispersed pigment method and is placed on the interfaces between color sensor areas to reduce the interference effects between monochromatic lights. Then, a color filter including at least a red filter, a green filter, and a blue filter is on this transparent planarization film. And then, a cover film is formed on the color filter for protection.

Abstract: An antenna effect monitor includes a transistor formed on a semiconductor substrate. The transistor gate is coupled to a doped polysilicon interconnect layer which is also coupled to an antenna effect monitoring unit. Several metal bonding pads float in an orderly fashion above the doped polysilicon interconnect layer without coupling with each other. Several small metal layers are formed in an orderly fashion above the doped polysilicon interconnect layer but are electrically coupled together by several via plugs in between. The top small metal layer is coupled to the top bonding pad. The bottom small metal layer is electrically coupled to the doped polysilicon interconnect layer. Then a passivation layer covers the substrate but leaves a pad opening to expose the top bonding pad.

Abstract: A hermetically sealed semiconductor flip chip and its method of manufacture. The semiconductor flip chip of the present invention is sealed with a silicon nitride layer on an active surface of the flip chip. The silicon nitride layer covers the chip active surface, including bond pads and conductive connectors such as solder balls formed over the bond pads to effect electrical and mechanical connection to terminal pads of a carrier substrate. A portion of the silicon nitride layer is penetrated or removed to expose a portion of each conductive connector. The flip chip is then attached to a substrate by contact of the exposed portions of the conductive connectors with the terminal pads of the substrate. Also included in the invention is the alternative of sealing the flip chip, substrate and intervening connectors with a silicon ride layer after the attachment of the flip chip to the substrate.

Abstract: A field programmable gate array has antifuses disposed over logic modules. Each of these antifuses includes a conductive plug and an overlaying region of programmable material (for example, amorphous silicon). To program one of these antifuses, an electric connection is formed through the programmable material to couple the conductive plug to a metal conductor that overlays the region of programmable material. The metal conductor includes a layer of a barrier metal to separate another metal of the conductor (for example, aluminum from an aluminum layer) from migrating into the programmable material when the antifuse is unprogrammed. In some embodiments, less than three percent of all antifuses of the field programmable gate array has a corner (from the top-down perspective) of the region of programmable material that is disposed (within lateral distance DIS of the conductive plug) underneath the metal conductor of that antifuse.

Abstract: A hermetically sealed sensor device having a glass member defining a mounting surface and base surface, the glass member including one or more pin apertures extending through the glass member from the mounting surface to the base surface. A metallic pin is disposed in each of the pin apertures, each pin having a portion extending above the mounting surface. The sensor device also includes a semiconductor sensor chip including a semiconductor device and a cover hermetically bonded and sealed to a surface of the semiconductor device, the cover protecting the semiconductor device from the external environment. The is chip hermetically bonded and sealed to the mounting surface of glass member. The semiconductor device has one or more contacts disposed on the surface thereof, for making electrical contact thereto, the cover having one or more contact apertures extending therethrough which exposes a portion of the contacts.

Abstract: A zapping diode concerned with a P-N junction diode provided in an integrated circuit, whose P-N junction is subjected to breakdown by an overvoltage to perform fine adjustment in the value of capacitance or resistance involved in the circuit. The diode has a first impurity region of a first conductivity type formed in a first conductivity type semiconductor region, a second impurity region, an interlayer insulation film formed over the semiconductor region, and a third conductor film formed on the semiconductor region between the first and second impurity region. The third conductor film, when applied by a reverse-bias voltage, controls the direction of breakdown in the P-N junction to thereby provide a consistent value of residual resistance.

Abstract: A semiconductor device having: a semiconductor substrate of a first conductivity type; a well formed in a surface of said semiconductor substrate, the well being of a second conductivity type opposite to the first conductivity type; a first MOS transistor formed in a surface of a first conductivity type region of the semiconductor substrate; a second MOS transistor formed in a surface of the well; a wiring connected to the gate electrodes of the first and second MOS transistors; and a protection diode with a p-n junction formed in the first conductivity type region and comprising a second conductivity type region electrically connected to the wiring and the first conductivity region of the semiconductor substrate, wherein the wiring and the well are not directly connected electrically. A CMOS type semiconductor integrated circuit device with a long and wide area wiring is realized which can effectively suppress damage to a gate oxide film of a MOSFET.

Abstract: An integrated circuit includes a plurality of CMOS transistors formed in a monocrystalline substrate. Within the substrate is a plurality of complementary spaced pairs of a p-well region and a n-well region. Between each well region, each of which has a source, gate, and drain, is a self-aligned trench filled with semiconductor material. A method of fabricating a field effect transistor entails a first step of forming a layer of first insulative material over a monocrystalline substrate. Next, a layer of semiconductor material is formed over the first insulative material. A p- or n-well masking layer is formed over the semiconductor layer and patterned to expose a first portion of the underlying semiconductor layer. A first dopant of one polarity is implanted in the region of the substrate aligned with the semiconductor layer first portion, which is then converted into a second insulative material. The masking layer is removed, thereby exposing the remaining portion of the semiconductor layer.