Abstract: The invention concerns a Switched MAGFET (MAGnetic field sensitive Field Effect Transistor). A preferred SMAGFET embodiment consists of a MAGFET structure with two equal sized drain contacts (3, 4), a gate area consisting of two equal sized and electrically isolated gate regions G1 and G2 (5, 6) separated by a third isolated gate region Gc (7) placed along the symmetry line of the device and slightly overlapping G1 and G2. The SMAGFET has a common source (1). By varying the gate voltage on Gc (with reference to the common source contact), the magnetic sensitivity of the SMAGFET may be controlled. By applying a first voltage on Gc, exchange of carriers from the channels beneath G1 and G2 is blocked. In case of an applied magnetic field, this will prevent Lorentz deflected carriers to cross symmetry line and redistribute the drain currents, i.e. the magnetic field sensitivity is virtually zero as the drain currents will remain unaffected by the magnetic induction.

Abstract: A method for making planar silicon-based inductor structure with improved Q is disclosed. This method includes the steps of: (a) providing a lightly-doped P-type substrate as a starting wafer; (b) forming a preliminary oxide layer on the lightly-doped P-type substrate; (c) forming a first oxide layer from the preliminary oxide layer enclosing a predetermined epitaxial area; (d) depositing an epitaxial layer in the epitaxial area using intrinsic doping; (e) forming a second oxide layer which covers both the epitaxial layer and the first oxide layer, and is merged with the first oxide layer to thus form a contiguous inter-connected inductor oxide layer; (f) forming a metal line according to a planar inductor pattern so as to form a silicon-based inductor structure. The epitaxial layer has a resistivity of at least 2 K ohm-cm. The planar silicon-based inductor improves the Q value by reducing or stopping current losses into the substrate.

Abstract: A multi-chip module that incorporates multiple flip chip (16) mounted on a daughter board (12), which in turn is flip-chip mounted onto a product mother board (10). The daughter board (12) is preferably a silicon substrate having solder bump terminals (14) and at least one conductor pattern on a surface thereof. The surface of the daughter board (12) may also have conductive runners and any passive electronic components required by the module. Mounted to the conductor pattern of the daughter board (12) are the flip chips (16) having solder bump terminals (18) that are registered and soldered to the conductor pattern of the daughter board (12). The solder bump terminals (14) of the daughter board (12) are then registered and soldered to a complementary conductor pattern on the mother board (10), such that the flip chips (16) are disposed between the daughter board (12) and the mother board (10).

Abstract: In the present invention, a vertical type MOSFET and a Schottky barrier diode which are used as a switching device of a DC--DC converter are formed on the same semiconductor substrate. Further, a barrier metal which is required for the Schottky barrier diode is also formed on an electrode portion of the vertical type MOSFET. In addition, a Schottky barrier diode forming region is formed to have low impurity concentration than a vertical type MOSFET forming region.

Abstract: The method includes the following steps: delimiting active areas on a substrate, forming gate electrodes insulated from the substrate on the active areas, and subjecting the front surface of the substrate to several implantation steps with doping ion beams to form source and drain regions with the use of the gate electrodes as masks. The direction of the implantation beam is defined by an angle of inclination to the front surface and by an orientation to a reference line on the front surface. To avoid performing numerous implantation steps without foregoing channels of uniform and constant length, the widths of the gate electrode strips are determined at the design stage in relation to the orientation of the strips to the reference line and on the orientation of the directions of the implant beams.

Abstract: A semiconductor processing method of forming an electrically conductive interconnect line having an electrical conductive covering predominately coextensive therewith, includes, a) providing an conductive interconnect line over a first electrically insulating material, the line having a top and sidewalls; b) selectively depositing a second electrically insulating material layer over the interconnect line and the first insulating material in a manner which deposits a greater thickness of the second insulating material atop the interconnect line than a thickness of the second insulating material over the first insulating material; c) anisotropically etching the second insulating material layer inwardly to at least the first insulating material yet leaving second insulating material over the top and the sidewalls of the interconnect line; and d) providing an electrically conductive layer over the anisotropically etched second insulating layer to form a conductive layer which is predominately coextensive with the

Abstract: It is possible for electrical breakdown to occur at a lower voltage in the case of a strong current in a lateral DMOST having a conventional interdigitated source/drain configuration as compared with lower current values. The invention is based on the recognition that this breakdown arises at the end faces of the drain fingers owing to current convergence at the ends of the fingers and the Kirk effect associated therewith. To increase the SOAR (safe operating area) of the transistor, the tips 11 of the drain fingers 7 are rendered inactive in that the source fingers 6 are locally interrupted. In an optimized embodiment, the source fingers are shorter than the drain fingers at the ends of these drain fingers.

Abstract: A memory cell. The memory cell includes an access transistor. The access transistor is formed in a pillar of single crystal semiconductor material. The transistor has first and second source/drain regions and a body region that are vertically aligned. The memory cell also includes a body contact that is coupled to the body region. A gate of the transistor is disposed on a side of the pillar that is opposite from the body contact. A trench capacitor is also included. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor and a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide. An insulator layer that separates the access transistor and the trench capacitor from an underlying layer of semiconductor material.

Abstract: A Germanium junction field effect transistor (Ge-JFET) is fabricated in a manner to produce low noise and which is particularly suitable for a cryogenic detector. The Ge-JFET in accordance with the present invention comprises a germanium base material on which a phosphorous implanted channel region is implanted thereon. A boron cap layer overlies the channel region. On the cap layer are separately spaced drain and source ohmic contact regions, and a gate ohmic contact region therebetween. The drain and source ohmic contact regions are separately spaced arsenic implant regions and a phosphorous implant region. The gate ohmic contact region is a BF.sub.2 implanted region.

Abstract: A semiconductor device includes a semiconductor substrate, and a laminated film insulatively formed over the semiconductor substrate, wherein the laminated film includes a semiconductor film, a metal film of refractory metal formed on the semiconductor film, a conductive oxidation preventing film disposed between the metal film and the semiconductor film, for preventing oxidation of the semiconductor film in an interface between the metal film and the semiconductor film, and an oxide film formed on a side surface of the semiconductor film and formed to extend into upper and lower portions of the semiconductor film in a bird's beak form.

Abstract: The present invention discloses a MOSFET transistor supported on a substrate. The MOSFET transistor includes an epitaxial-layer of a first conductivity type near a top surface of the substrate defining a drain region therein. The MOSFET transistor further includes an oxide block supported on a raised silicon terrace of the epitaxial layer disposed in a central portion of the transistor above a JFET reduction region of a first conductivity type of higher dopant concentration than the epitaxial layer. The MOSFET transistor further includes a lower-outer body region of a second conductivity type surrounding the JFET reduction region disposed near the top surface and defining a boundary of the MOSFET transistor. The MOSFET transistor further includes a source region of the first conductivity type enclosed in the lower-outer body region disposed near the top surface and extended to the transistor boundary.

Abstract: An electronic module includes multiple stacked bare IC chips ("a stack") and a sensor assembly that is mechanically coupled to an end surface of the stack. Electrical connection between the sensor assembly and the stack is provided by a metallization layer disposed on a side-surface of the stack. Specifically, wiring of the sensor assembly extends to an edge surface thereof corresponding to the side-surface of the stack where it electrically connects to the side-surface wiring. The IC chips of the stack are similarly electrically connected to the side-surface wiring. Multiple sensors (e.g., CCD arrays) may be electrically and mechanically coupled to multiple surfaces of the stack for providing a, e.g., multi-view imaging module. Multiple electrical and mechanical options exist for the connection of sensors to stacks within electronic modules.

Abstract: A method for forming shallow trench isolation comprising the steps of providing a substrate having a mask layer formed thereon. Next, the mask layer is patterned to form a first trench in the substrate. Then, dielectric spacers are formed on the sidewalls of the first trench. After that, a second trench is formed in the substrate by an etching operation following the profile of the dielectric spacers. Next, a second dielectric layer is formed filling the second trench, wherein the second dielectric layer and the dielectric spacers are formed from different materials. Thereafter, the dielectric spacers are removed to form recess cavities, and then a filler material is deposited into the recess cavities. Subsequently, a gate oxide layer is formed over the filler material and the substrate. Finally, a polysilicon gate layer is formed over the gate oxide layer.

Abstract: A semiconductor memory device includes a memory cell capacitor for storing information, wherein the memory cell capacitor includes a capacitor insulation film of a double oxide on a lower electrode. The lower electrode has a layered structure of Ir/IrO.sub.2 /Ir or Ru/RuO.sub.2 /Ru acting as a diffusion barrier of oxygen or Pb. Further, the use of a Pt--Ir alloy is disclosed for the lower electrode.

Abstract: In a first region of a semiconductor substrate, there are formed MIS transistors each composed of a gate insulating film, a gate electrode, and source/drain regions. In a second region of the semiconductor substrate, there is formed an impurity diffusion layer serving as a conductive layer. On an interlayer insulating film, there are formed an antenna interconnection connected to the gate electrodes and an interconnection for charge dissipation connected to the conductive layer. During the process of dry etching for forming the interconnections, charges move into the semiconductor substrate via the interconnection for charge dissipation. The deterioration of the gate insulating film caused by the injection of charges into the gate electrode is suppressed and the degradation of characteristics of the MIS transistor including a shift in threshold is also suppressed.

Abstract: In an element region, in which a memory cell is constituted, on a silicon substrate, a gate electrode with which each of a plurality of the memory cells is individually constituted is individually disposed for each memory cell. A first and a second inter-layer insulating films are formed right upon the gate electrode. A jumping wiring is disposed on the insulating films. The jumping wiring is directly and electrically connected, within the memory pattern region in which the memory cell is formed, with each individual gate electrodes through the jumping contact.

Abstract: A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j ?nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff ?nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.

Abstract: The specification describes a thermocompression bonding process using anisotropic conductive film (ACF) bonding material in which the bonding pads are shaped to prevent depletion of conductive particles in the bonding region during compression. The process is useful in bump technology for interconnecting component assemblies on substrates such as glass, printed wiring boards, etc. The shaped structure can be made using photodefinable polymer strips around the bonding pads where the strips are thicker than the bonding pad. Alternative approaches to shaping one or both of the mating conductive surfaces are disclosed.

Abstract: The present invention provides a composite passivation film deposited at low temperatures (<150.degree. C.). A hydrogenated amorphous silicon nitride (a-SiN.sub.x :H) film is formed over a semiconductor device. Then a very thin layer (>6.4 nm) of an amorphous silicon hydrogen (a-Si:H) film is formed over the a-SiN.sub.x :H film. Such a composite passivation film can prevent semiconductor devices from oxidation due to percolation of moisture, and maintain the electric properties and stability of the semiconductor devices.

Abstract: Disclosed is a process for forming a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention comprises, first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. Next, a low ion velocity and low energy ion bombardment plasma doping or PLAD operation is conducted to provide a highly doped inner portion of a shallow junction. In a further step, a higher ion velocity and energy conventional ion bombardment implantation doping operation is conducted using a medium power implanter to extend the shallow junction boundaries with a lightly doped outer portion. An anneal step follows. The result is a shallow junction with a variable concentration profile gradation of dopant. The junction is suitable for forming source and drain regions in MOS transistors, especially where a contact or interconnect is intended to engage the source and drain regions.