Abstract: A re-configurable interface used in modular electronic architectures includes a host (203) and one or more modules (201) for interfacing with the host (203) to provide additional functionality. A configuration controller (209) located in the host (203) is for reading a memory device (215) located in the module (201) for providing configuration information to the host. The pin controller (209) then is able to reconfigure pins of the host connector (207) to communicate with the module (201).

Abstract: The need for a SAF-TE processor embedded on a SCSI backplane of a hot-swap hard disk drive enclosure is eliminated by utilizing the functionality of a RAID on motherboard (ROMB) controller and an Embedded Server Management (ESM) interface already present in an information handling system. Only sensors and input-output (I/O) registers remain on the SCSI backplane as required. The SCSI backplane I/O is split between the ESM and ROMB according to functional requirements.

Abstract: A hybrid switching module includes a hybrid switching module processor data channel; a hybrid switching module main data channel; an input/output link data channel; a switch coupled to the hybrid switching module processor data channel; and a bridge coupled to the hybrid switching module main data channel; wherein the switch selectively coupled to the bridge and selectively coupled to the input/output link data channel, wherein the hybrid switching module processor data channel is thereby selectively coupled to the bridge and selectively coupled to the input/output link data channel.

Abstract: A slave device on a data bus has a register that stores a non-queued split master vector containing bits identifying whether a transaction with corresponding master devices have been split. An input gate is responsive to the status of the slave device and to receipt of a command from a master device when the slave device status is busy to set a bit in the non-queued split master vector identifying that the transaction with the corresponding master device is split. An output gate is responsive to a not busy status of the slave device to output the non-queued split master vector to the arbiter to re-arbitrate use of the data bus among the previously-split non-queued master devices.

Abstract: Methods and apparatus associated with a plurality of serial devices designed to communicate with a bus master in either a daisy chain or a normal configuration are provided. One method includes the step of serially providing a command sequence having a channel identifier to a given device of a plurality of daisy chained devices. The channel identifier is modified as it passes thru each daisy chained device. A specific device is identified or enabled when the channel identifier it receives matches a pre-determined value.

Abstract: A system including at least two processing units embedded on a chip able to communicate with each other and to generally independently control access to data from memory on the chip.

Abstract: Techniques for a pipelined bus which provides a very high performance interface to computing elements, such as processing elements, host interfaces, memory controllers, and other application-specific coprocessors and external interface units. The pipelined bus is a robust interconnected bus employing a scalable, pipelined, multi-client topology, with a fully synchronous, packet-switched, split-transaction data transfer model. Multiple non-interfering transfers may occur concurrently since there is no single point of contention on the bus. An aggressive packet transfer model with local conflict resolution in each client and packet-level retries allows recovery from collisions and buffer backups. Clients are assigned unique IDs, based upon a mapping from the system address space allowing identification needed for quick routing of packets among clients.

Abstract: A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a control interface to drive a control signal at a clock frequency, an address bus interface to drive address elements at twice the clock frequency, and a data bus interface to drive data elements at four times the clock frequency. The address bus interface drives a substantially centered address strobe transition for each address element, and the data bus interface drives a substantially centered data strobe transition for each data element.

Abstract: A data transfer control device using USB (a first bus), the end of a data phase (data transport: transfer of all the data) during an OUT transaction is determined on condition that data transmission (DMA transfer) through EBUS (a second bus) has ended, and the end of a data phase during an IN transaction is determined on condition that data reception through EBUS has ended and also an Empty signal has gone active, indicating that a data storage area has become empty. A counter that counts the data size is provided on the EBUS side. If data reception through EBUS ends and the size of data remaining in the data storage area is less than the maximum packet size, a short packet in the data storage area is transmitted automatically through USB and an interrupt is used to notify the firmware of the presence of the short packet.

Abstract: A method for preventing net update oscillation of a bus bridge by competing net update messages is presented.

Abstract: A target device in a computer bus system allocates resources by selecting a priority requester for allocation of scarce resources. In a non-bus arbiter configuration, the first initiator device to receive a retry response to a transaction request after the resources are exhausted is designated as a priority requester. In a bus arbiter configuration, the priority requester is chosen on a round-robin basis from initiator devices that received a retry response to the initiator's most recent transaction request. If only one resource is available when an initiator sends a transaction request, the initiator receives a retry response unless the initiator is the priority requester.

Abstract: A system and method for dynamically tuning the interrupt coalescing behavior of a communication interface to suit the workload of the interface. An interrupt handler adjusts dynamic Packet and/or Latency values of the interface to control how many packets the interface may accumulate, or how much time the interface may wait after receiving a first packet, before it can signal a corresponding interrupt to a host processor and forward the accumulated packet(s). The interrupt handler maintains a Trend parameter reflecting a comparison between recent sets of packets received from the interface and the interface's Packet parameter. The Packet value is decreased or increased as packet traffic ebbs or flows. When the Packet value is incremented from a minimum value, a Fallback mechanism may be activated to ensure a relatively rapid return to the minimum value if an insufficient amount of traffic is received to warrant a non-minimum Packet value.

Abstract: A modular connecting system for connecting an external device to a fieldbus system includes a fieldbus-specific fieldbus interface circuit and a fieldbus-independent interface device connected to the interface circuit. The interface device has operating modes and is to be selectively connected to an external device including not only simple sensors or actuators with parallel signal transmission, but also complex sensors or actuators with series signal transmission. The interface device connects the external device to said interface circuit during parallel signal transmission and serial signal transmission. The interface device is programmed to autonomously check a type of the external device connected to said interface device and to select an appropriate subset of said operating modes for the type of the external device.

Abstract: When data is transferred from a controller of a liquid crystal display device to each driver through a predetermined number of signal lines, the Transferring Data are divided into a plurality of groups by forming the signal lines into groups beforehand. For each group, the combination of inversion/non-inversion of the data to be transmitted is examined, a well-balanced combination is selected so as to reduce EMI.

Abstract: A method is disclosed for handling interruptions, such as asynchronous interrupts, of a process using a system resource. The method determines whether a process is currently using a system resource. If a resource is being used and the system receives an interruption, then the method logs the interruption and delays accepting the interruption until after the process currently using the resource is completed. The method may be implemented in a system that controls access of processes to resources using semaphores that lock the resources while in use. The method determines whether a resource is currently in use by detecting a load and clear operation, indicating that a semaphore has locked the resource. The method delays acceptance of the interruption until either a branch command is executed, a store command is executed, a specified number of instructions are retired, or a specified number of clock cycles pass.

Abstract: Starting and establishing a dialog between an interruption handler and an operating system for handling of hardware interruptions by the operating system is disclosed. A recommendation for handling such an interruption, and information regarding the interruption, are stored by the interruption handler in a storage accessible by the operating system. The interruption handler calls the operating system at a predetermined interruption handling point thereof, for the operating system to handle the interruption. The handler then determines whether the operating system handled the interruption according to the recommendation.

Abstract: The present invention relates generally to an adapter unit for a personal digital assistant. More specifically, this invention relates to an adapter unit that provides additional functionality, and improved ergonomics and increased ruggedness to the personal digital assistant. The additional functionality includes the ability to automatically change the function of one or more of the application buttons on the personal digital assistant upon the attachment of the adapter unit.

Abstract: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements (PEs) and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debug interrupts and a dynamic debuts monitor mechanism.

Abstract: A backplane bus system and related method for increasing the throughput of cPCI-specified backplane architectures. The system includes an interposer card for transforming reflective-wave switching into incident-wave switching. Establishing incident-wave switching on the bus along with careful slot pitch and impedance layout increases the rate at which the voltage amplitude observed by all receivers connected to the bus is sufficient to produce a change of state on the first signal propagation down the bus. Most existing peripherals are configured with transceivers that produce reflective-wave switching. The present system includes an interposer card to transform that switching into incident-wave switching. A preferred transceiver for doing so and that is implemented on the interposer card is a GTLP transceiver. A state machine is employed to regulate operation of the incident-wave switching transceiver. The system may be used to permit implementation of as many as 21 slots on a conventional cPCI backplane.

Abstract: A hierarchical display of protocol layers for communication data. Fields of the communication data are converted into field cells where each field cell has a text field and a field descriptor. The field cells for each protocol layer are arranged by an interpreter into protocol units according to a protocol standard for that layer and then displayed in a hierarchical manner. Detailed specifications for field cells taken directly from the protocol standard can be displayed by using a cursor over the field cell. Indicators in particular ones of the field cells allow certain field cells within a protocol unit to be collapsed or expanded within the protocol unit or allow lower protocol units to be collapsed or expanded into the higher protocol units.