Abstract: A device includes an array powered between virtual supply and reference voltages, with each row having a wordline and each column having a bitline and complementary bitline. The virtual supply voltage circuit includes a first transistor configured to output the virtual supply voltage, and a second transistor configured to turn off to reduce current supplied to the array. A column driver, while the second transistor is off, drives the bitlines and complementary bitlines to opposite logic states in response to an internal clock. A row decoder asserts wordlines in response to the internal clock. Due to the reduced current supplied to the array, the bitlines remain at a logic high state and the complementary bitlines fall to a logic-low state, resetting the memory cells.

Abstract: A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.

Abstract: A three-dimensional (3D) memory device comprising a 3D memory array, an encoding circuit, a sensing circuit and a processing circuit is provided in present disclosure. The 3D memory array comprises multiple two-dimensional (2D) memory arrays and is configured to receive multiple input voltages and output multiple output currents. Each 2D memory array comprises multiple memory cells and a four-array-side edge. The encoding circuit and the sensing circuit are coupled to the processing circuit and the four-array-side edge, and respectively configured to input the input voltages and receive the output currents. The processing circuit is configured to perform an in-memory-computing according to the input voltages and the output currents. The four-array-side edge has multiple array sides. When one of the array sides is configured to receive the input voltages, another is configured to output the output currents, wherein the one of the array sides is not parallel to the another.

Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage stru

Abstract: A memory module includes a printed circuit board (PCB) including a multi-layer having a wiring structure formed therein. A length of the PCB in a first direction is longer than a length of the PCB in a second direction perpendicular to the first direction. A plurality of memory chips includes a plurality of solder balls. The plurality of memory chips is arranged in a first row and a second row respectively extending in the first direction on the PCB. The plurality of solder balls is continuously arranged in the first direction. The wiring structure alternately zigzag-connects the plurality of memory chips arranged in the first row and the second row.

Abstract: The present disclosure provides a PCM-based memory device for DNN and a method for storing weights thereof, the device comprising: a cell array having a plurality of memory cells implemented with phase change memories (Multi-Level Cell-Phase Change Memory, hereinafter PCM) that each store multi-bit data according to a resistance state level including a resistance value among a plurality of resistance state levels; and a memory controller that stores multi-bit data in the memory cells by mapping each bit pattern and the resistance state level, according to an appearance rate for bit patterns of a plurality of weights included in a plurality of layers constituting a DNN (Deep Neural Network). According to the present disclosure, fault tolerance can be improved by reducing the frequency of data errors due to resistance drift phenomenon.

Abstract: A semiconductor device includes a bit line pre-charger and a buffer circuit. The bit line pre-charger is configured to charge at least one bit line when a first control signal has a first voltage level. The buffer circuit is configured to generate the first control signal. During a first standby period, the buffer circuit adjusts the first control signal to a second voltage level different from the first voltage level.

Abstract: A circuit for carrying out a vector operation. The circuit includes: memory cells, connected to a column line, each having an input terminal and a semiconductor switching element, the gate terminal of which is connected to the input terminal, and the drain or the source terminal being connected to the column line, wherein when a sufficiently high gate voltage is at the gate terminal, the memory cell is activated so that an electrical cell current is conducted out of or into the column line at suitable voltages; an input voltage circuit connected to the input terminals; a detection circuit connected to the column line and having an analog-to-digital converter which determines a digital value corresponding to the intensity of a measurement current flowing into or out of the column line, the detection circuit being configured to detect the digital value determined by the analog-to-digital converter, and reduce the measurement current.

Abstract: A memory circuit includes a memory array comprising a plurality of memory cells arranged over a plurality of word lines and along a bit line, and a controller operatively coupled to the memory array and comprising an RC detector. The RC detector is configured to advance a timing for a first tracking signal to fall, subsequently to a second tracking signal transitioning to rise and prior to a third tracking signal transitioning to rise. The first tracking signal is conducted through a first tracking line, the second tracking signal is provided to conduct through a second tracking line, and the third tracking signal is conducted through the second tracking line.

Abstract: A leakage compensation content addressable memory (CAM) circuit includes at least one CAM cell configured to store a bit value, and at least one compensation CAM cell configured to store the bit value of the CAM cell and to cancel leakage current of the CAM cell. The leakage compensation CAM circuit further includes at least one main bit line driver coupled to bit lines of the CAM cell to supply output to the bit lines of the CAM cell, at least one compensation bit line driver coupled to bit lines of the compensation CAM cell to supply output to the bit lines of the compensation CAM cell, and at least one word line driver coupled to word lines to supply output to the word lines of the CAM cell and the compensation CAM cell.

Abstract: A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.

Abstract: A dynamic random access memory (DRAM) array has a first portion configured as a data array and a second portion configured as a reference array. The DRAM array includes read bit lines which include a first plurality of read bit lines in the data array and a second plurality of read bit lines in the reference array. Read circuitry includes a plurality of sensing circuits, each sensing circuit coupled to a corresponding read bit line of the first plurality of read bit lines and configured to receive a first reference voltage generated by a first read bit line of the second plurality of read bit lines and a second reference voltage generated by a second read bit line of the second plurality of bit lines. The plurality of sensing circuits is configured to provide a corresponding bit of an output read value.

Abstract: Examples of the present disclosure disclose a memory and an operation method thereof, and a memory system. The memory includes: a memory cell array including a plurality of memory cells; bit lines coupled to the plurality of memory cells; a plurality of word lines coupled to the plurality of memory cells; and a peripheral circuit coupled to the bit lines and the word lines. The peripheral circuit is configured to apply, at a first time period, a first voltage to a selected word line in the plurality of word lines to turn on a cell transistor of a memory cell coupled to the selected word line, and apply, at the first time period, a second voltage to at least one dummy word line in the plurality of word lines to turn on a cell transistor of a memory cell coupled to the at least one dummy word line.

Abstract: A memory device includes: a memory cell array; an input/output circuit controlling inputting and outputting data stored in the memory cell array; an impedance calibration circuit generating an impedance calibration code based on an external resistor connected to an impedance pad for application to the input/output circuit as an applied impedance calibration code; and a calibration control circuit comparing a new impedance calibration code received from the impedance calibration circuit with a calibration code range for generating a calibration code update flag when the new impedance calibration code is included in the calibration code range. The impedance calibration circuit updates the applied impedance calibration code with the new impedance calibration code when receiving the calibration code update flag.

Abstract: A device to detect attacks on a memory system in an advanced driver-assistance system (ADAS) of a vehicle. The device has an interface operable on a memory channel, a random access memory, a non-volatile memory cell array, and a controller configured to detect a trigger event, and in response: identify a sequence of commands received in the interface from the memory channel to access memory services provided via at least the random access memory during ADAS operations; perform operations of multiplication and accumulation using the non-volatile memory cell array to implement computations of an artificial neural network responsive to the sequence of commands as an input to generate a classification of the sequence as an output; and provide the classification via the interface.

Abstract: The present disclosure provides memory devices, operating methods, memory systems. An example memory device includes a memory array and a peripheral circuit. The memory array includes a first and a second finger memory region, each region including multiple memory cell strings. Each memory cell string includes a first bottom select transistor (BSG). First BSGs in the first and second finger memory regions have a first and a second threshold voltage, respectively. The peripheral circuit is configured to: apply a first bias voltage to the BSGs in the first pre-charge phase of a programming verification operation on the first finger memory region; apply a second bias voltage to the first BSGs after the first pre-charge phase; the first bias voltage is smaller than the second bias voltage; and the second bias voltage is smaller than the second threshold voltage and greater than the first threshold voltage.

Abstract: A circuit includes a memory circuit, and a power management circuit having a first circuit. The first circuit is configured to, in response to a first state of the first power management control signal and a first state of the second power management control signal, control supply of a first supply voltage to the memory circuit in accordance with a first power mode control signal. The first circuit is further configured to, in response to a second state of the first power management control signal, store a state of the first power mode control signal, and control supply of the first supply voltage to the memory circuit in accordance with the stored state of the first power mode control signal. The power management circuit is configured to, in response to a second state of the second power management control signal, disable a part of the first circuit.

Abstract: A pipeline system includes a first inverter latch configured to receive plural data entries, and plural second inverter latches coupled to each other in parallel for storing the plural data entries input from the first inverter latch in a distributive manner. Plural first switches are arranged between the first inverter latch and the plural second inverter latches, each first switch configured for controlling transmission of each of the plural data entries from the first inverter latch to one of the plural second inverter latches. Plural second switches are configured to output the plural data entries stored in the plural second inverter latches.

Abstract: An exemplary magnetoresistive random-access memory (MRAM) cell is configured to store more than one bit. The MRAM cell includes a first magnetic tunneling junction (MTJ) and a second MTJ connected in parallel. The first MTJ has a first diameter, the second MTJ has a second diameter, and the second diameter is less than the first diameter. The MRAM cell further includes a transistor connected to the first MTJ and the second MTJ, a bit line connected to the first MTJ and the second MTJ, a word line connected to the transistor, and a source line connected to the transistor. A method of writing to the MRAM cell can include supplying one or more write voltages to the MRAM cell (e.g., having different levels) depending on an initial memory state and a desired memory state of the MRAM cell.

Abstract: A memory is provided that includes a negative bit line hybrid boost circuit for boosting a discharged bit line to a negative voltage during a negative bit line boost period for a write operation to a selected column in the memory. The hybrid boost circuit uses a charged gate capacitance of a boost transistor and a charged capacitance of a metal line capacitor to provide the negative bit line boost. Similarly, the memory may include a word line hybrid boost circuit that uses another boost transistor and another metal line capacitor for boosting a word line above a word line power supply voltage during the write operation.