Abstract: A neuromorphic architecture is formed from a laminate of non-woven carbon fiber reinforced polymer layers arranged in a plurality of different directions. A plurality of distributed nodes are formed through the laminate via transverse voids, and an encapsulant encapsulates an electrochemical fluid or gel such that the electrochemical fluid or gel may flow within the nodes and around the laminate. Electrical current flowing through the architecture creates reversible metal deposits at various nodes, depending on the path developed through the architecture, with a complexity sufficient for neuromorphic processing, and providing a writable and erasable memory. A neuromorphic actuator may be formed by combining shape memory materials with such a neuromorphic architecture, which may provide desired surface contours and/or actuations based on current in the neuromorphic architecture.

Abstract: A method comprises applying a first reference drive voltage to a wordline of memory cells to generate a respective first resulting voltage level from each respective cell in the wordline, and storing in memory a first respective logic value indicated by the respective first resulting voltage level for each memory cell. The method further comprises applying a second reference drive voltage to the wordline of memory cells to generate a respective second resulting voltage level from each respective cell in the wordline while detecting a pattern of logic values stored in the memory in parallel. The memory is modified based on a second respective logic value indicated by the respective second resulting voltage level, and at least one of the first reference drive voltage and the second reference drive voltage is modified based on the detected pattern data.

Abstract: To reduce power consumption and circuitry requirements, the following presents an “unmatched” data output architecture, in which the clock path does not mimic the data path. To provide proper data transfers in the data output path, the clock signal is tuned at points of the clock path, such as for data transfers from internal data buses to FIFOs and from the FIFO though the multiplexers to the input/output pads. An amount of timing offset is introduced in the generation of internal transfer clocks, which can be determined as part of a valid data window training process that can be performed by the controller, such as part of the power up process.

Abstract: A semiconductor device includes: a memory array; a modulation circuit including a first resistive element, a second resistive element and a third resistive element; a regulator including a transistor; and a controller configured to: determine an operation mode of the memory array; generate a first regulated voltage at a drain terminal of the transistor, wherein the first regulated voltage corresponds to a positive temperature coefficient, a negative temperature coefficient or a zero temperature coefficient according to a first resistance ratio between the first resistive element and the second resistive element and a second resistance ratio between the second resistive element and the third resistive element; provide a first access voltage to the memory array in response to the first regulated voltage corresponding to the positive temperature coefficient; and provide a second access voltage to the memory array in response to the first regulated voltage corresponding to the negative temperature coefficient.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory device are configured to add variable delays to a command. The variable delays may be provided by a host device (e.g., a test equipment) using a test mode of the memory devices. Alternatively, the variable delays may be stored in nonvolatile memory (NVM) components of the memory devices. Further, mode registers of the memory devices may be set to indicate that the command is associated with the variable delays stored in the NVM components. Further, the memory devices may include delay components configured to add the variable delays to the command. Such variable delays facilitate staggered execution of the command across multiple memory devices so as to avoid (or mitigate) issues related to an instantaneous, large amount of current drawn from a power supply connected to the memory devices.

Abstract: A memory device includes a memory cell array including memory cells, a single-ended bitline sense amplifier connected to the memory cells through a bitline and a complementary bitline, and electrically connected through one of the bitline or the complementary bitline in response to the memory cells being activated. A DSI circuit is configured to conditionally transmit complementary input data generated by inverting input data to the single-ended bitline sense amplifier in response to a first number of bits included in the input data having a first level greater than a second number of bits included in the input data having a second level, and a data inversion flag indicating that the input data is inverted, to the sense amplifier. The sense amplifier stores the complementary input data in the memory cell array and the data inversion flag in a specified partial area of the memory cell array.

Abstract: A parallel e-fuse device including: a first e-fuse to receive an input voltage and transfer a first fuse current to an output terminal; and a second e-fuse to receive the input voltage and transfer a second fuse current to the output terminal, the first e-fuse includes: a power transistor to control the first fuse current according to a gate voltage; a clamp amplifier to provide a charging current to charge a gate of the power transistor, the charging current being obtained by monitoring a feedback voltage; a balance amplifier to provide a first sinking current to discharge the gate of the power transistor, the first sinking current being obtained by comparing a current sensing signal with a current monitoring signal, wherein the clamp amplifier generates the charging current according to a differential voltage between the feedback voltage and a reference voltage.

Abstract: A method for operating a data processing system for processing data. The data processing system is set up for the repeated execution of a plurality of data processing tasks. The following steps are carried out for the operation of the data processing system: a) executing the individual data processing tasks at their respective repetition rate in the time grid; b) outputting of output data by the individual data processing tasks into the buffer memory assigned to the clock pulse of the grid; c) reading in of input data by the individual data processing tasks from the buffer memories which are assigned to the preceding clock pulses of the grid.

Abstract: A memory circuit may comprise a memory array comprising a plurality of memory cells, an input/output (I/O) circuit, and a power management circuit. The I/O circuit can be operatively coupled to the memory array and configured to read or write each of the memory cells. The power management circuit can be operatively coupled to the memory array and the I/O circuit. The power management circuit can be configured to provide a first gate control signal and a second gate control signal based on a received first supply voltage and a received second supply voltage. The first supply voltage can be substantially higher than two times the second supply voltage.

Abstract: A current detector includes: a plurality of memory cells configured to store a plurality of first data, each having a plurality of bits; a plurality of first wiring lines configured to transmit a result of a bit operation of each of the plurality of first data and second data having bits, the number of bits of the second data being the same as the number of bits of first data; and a detector configured to detect a first wiring line through which a lowest current flows among the plurality of first wiring lines.

Abstract: The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.

Abstract: A magnetic memory element includes an antiferromagnetic layer made of a canted antiferromagnet having a magnetic order with a canted magnetic moment, and a contact layer in contact with the antiferromagnetic layer and made of a different material from the canted antiferromagnet. A roughness of an interface between the antiferromagnetic layer and the contact layer is 1.0 nm or less. A spin current flowing through the contact layer is configured to induce a torque to act on the magnetic order of the antiferromagnetic layer, thereby allowing reversal of the magnetic order.

Abstract: Technology for programming selector-only memory cells in a cross-point memory structure. The threshold switching memory element may include, but is not limited to, an Ovonic Threshold Switch (OTS). The memory system removes Vth drift in the threshold switching memory elements prior to programming. The Vth drift is removed by applying a first voltage and a second voltage having opposite polarities to all of the SOM cells to be programmed. Then, two programming voltages having the two polarities are applied to program the cells to two states.

Abstract: A data buffer circuit structure, a layout structure of multiple data buffer circuits, and a memory. The data buffer circuit structure includes a first amplification circuit, a second amplification circuit, a decision equalizer, and a power module. An output terminal of the first amplification circuit, an input terminal of the second amplification circuit, and adjustment output terminals of the decision equalizer are connected through a signal line. The power module includes a first power supply unit and a second power supply unit. A minimum distance between the first power supply unit and the first amplification circuit is less than a minimum distance between the first power supply unit and the second amplification circuit, and a minimum distance between the second power supply unit and the second amplification circuit is less than a minimum distance between the second power supply unit and the first amplification circuit.

Abstract: Numerous examples are disclosed of systems and methods to implement redundancy. In one example, a system comprises an array of non-volatile memory cells; a redundant array of non-volatile memory cells; and an input block coupled to respective rows in the array and respective rows in the redundant array and comprising row tag registers and redundant row tag registers.

Abstract: When performing a read process, a non-volatile memory first performs a pre-read sensing of the condition of memory cells connected to neighbor word lines. While applying a first word line voltage associated with a first programmed data state to the selected word line, the memory system performs two sensing operations for the first programmed data state on selected memory cells that have neighbor memory cells on the neighbor word lines in a first condition and perform two sensing operations for the first programmed data state on selected memory cells that have neighbor memory cells on the neighbor word lines in a second condition. Based on that sensing, the data being stored in the set of selected memory cells is determined. In some embodiments, at least one of the two sensing operations for each condition includes sensing soft bit information that improves the data decoding process.

Abstract: A magnetoresistive memory cell includes a first terminal electrode, a second terminal electrode, and a magnetoresistive layer stack located between the first terminal electrode and the second terminal electrode and including, from one side to another, a reference layer, a dielectric tunnel barrier layer, a free layer, and a material layer having two different states of lattice deformation which have different average in-plane lattice constants and which are configured to apply different in-plane stress. The material layer may be a metal-insulator transition (MIT) material layer that exhibits a phase transition between an insulator state and a metal state.

Abstract: A non-volatile memory attempts to read a data set from a plurality of non-volatile memory cells in multiple threshold voltages distributions and determines that the data set was not read successfully due to there being too many errors in the data read. In response to determining that the data set was not read successfully, the system identifies memory cells storing error bits that are in upper tails and lower tails of the threshold voltages distributions. To reduce the number of errors, memory cells storing error bits that are in upper tails have their threshold voltages reduced by bit level erase and memory cells storing error bits that are in lower tails their threshold voltages increased to move the memory cells closer to the center of their respective threshold voltages distributions by bit level program.

Abstract: A first select transistor is connected to a first wiring. A first memory cell transistor and a second memory cell transistor are connected in series between the first select transistor and a second select transistor. A first word line is connected to the first memory cell transistor. A second word line is connected to the second memory cell transistor. During a first period in which the first voltage is applied to the first wiring, a second voltage lower than a first voltage is applied in parallel to the first word line and the second word line. During a second period in which a third voltage higher than the first voltage is applied to the first wiring, the second voltage is applied to the first word line, and a fourth voltage higher than the second voltage and lower than the third voltage is applied to the second word line.

Abstract: Numerous embodiments of input circuitry for an analog neural memory in a deep learning artificial neural network are disclosed.