Abstract: A non-volatile synapse circuit of a non-volatile neural network. The synapse includes: a first input signal line for providing a first input signal; a reference signal line for providing a reference signal; first and second output lines for carrying first and second output signals therethrough, and first and second cells for generating the first and second output signals, respectively. Each of the first and second cells includes: a first upper select transistor having a gate that is electrically coupled to the first input signal line; and a first resistive changing element having one end connected to the first select transistor in series and another end electrically coupled to the reference signal line. The value of the first resistive changing element may be programmable to change the magnitude of an output signal.

Abstract: A method of operating a neuromorphic system is provided. The method includes applying voltage signals across input lines of a crossbar array structure, the crossbar array structure including rows and columns interconnected at junctions via programmable electronic devices, the rows including the input lines for applying voltage signals across the electronic devices and the columns including output lines for outputting currents. The method also includes correcting, via a correction unit connected to the output lines, each of the output currents obtained at the output lines according to an affine transformation to compensate for temporal conductance variations in the electronic devices.

Abstract: Error correction values for a memory device include row error correction values and column error correction values for the same memory array. The memory device includes a memory array that is addressable in two spatial dimensions: a row dimension and a column dimension. The memory array is written as rows of data, and can be read as rows in the row dimension or read as columns in the column dimension. A data write triggers updates to row error correction values and to column error correction values.

Abstract: A computing device including a logic track including two logic-track magnetic domains separated by a logic-track domain wall, an input track arranged crossing the logic track at a first position of the logic track, and an output track arranged crossing the logic track at a second position of the logic track near the logic-track domain wall. The input track includes at least one input-track magnetic domain, and each of the at least one input-track magnetic domain includes at least one input-track storage unit configured to store binary 0 or 1. The output track includes at least one output-track magnetic domain, and each of the at least one output-track magnetic domain includes at least one output-track storage unit configured to store binary 0 or 1.

Abstract: An operating method of a nonvolatile memory device includes receiving, at the nonvolatile memory device, a suspend command, suspending, at the nonvolatile memory device, a program operation being performed, in response to the suspend command, receiving, at the nonvolatile memory device, a resume command, and resuming, at the nonvolatile memory device, the suspended program operation in response to the resume command. The program operation includes program loops, each of which includes a bit line setup interval, a program interval, and a verify interval. In the program interval of each of the program loops, a level of a program voltage to be applied to selected memory cells of the nonvolatile memory device increases as much as a first voltage. A difference between a level of the program voltage finally applied s suspend and a level of the program voltage applied first after resume is different from the first voltage.

Abstract: A semiconductor memory training method includes: selecting two adjacent reference voltages from a plurality of reference voltages as a first reference voltage and a second reference voltage; obtaining a first minimum margin value for the plurality of target signal lines under the first reference voltage; obtaining a second minimum margin value for the plurality of target signal lines under the second reference voltage, according to a minimum margin value for each target signal line under the second reference voltage; determining a target interval for an expected margin value according to the first minimum margin value and the second minimum margin value, the expected margin value being the maximum one among the minimum margin values for the plurality of target signal lines under the plurality of reference voltages; and searching for the expected margin value in the target interval.

Abstract: A serial NOR memory device receives serial input data using a single data rate (SDR) mode and transmits serial output data using a double data rate (DDR) mode. In some embodiments, a serial NOR memory device includes an input-output circuit including a transceiver coupled to receive a clock signal and serial input data and to provide serial output data. The transceiver is configured to receive serial input data using the single data rate mode and is configured to transmit serial output data using the double data rate mode.

Abstract: A computer-implemented method of designing a dental restoration at a display includes providing a virtual three dimensional representation of at least a portion of the patient's dental situation. The method includes displaying a library arch form in an alignment with the virtual three dimensional representation of the portion of the patient's dentition. The library arch form includes a pair of two virtual library teeth packing to each other. The method also includes in response to a parametric change of one of the two virtual library teeth, moving the other virtual library tooth to keep packing to the changed virtual library tooth.

Abstract: An apparatus for reading a bit of a memory array includes a bit cell column, voltage enhancement circuitry, and control circuitry. The voltage enhancement circuitry is configured to couple a bitline to a reference node. The control circuitry is configured to, in response to a read request for a bitcell element of a plurality of bitcell elements, couple a current source to the bitcell column such that a read current from the current source flows from the source line, through the bitcell column and the voltage enhancement circuitry, to the reference node and determine a state for the bitcell element based on a voltage between the source line and the reference node. The voltage enhancement circuitry is configured to generate, when the read current flows through the voltage enhancement circuitry, a voltage at the bitline that is greater than a voltage at the reference node.

Abstract: According to an embodiment, a neural network apparatus includes a plurality of neuron circuits, each including an integration circuit, a firing circuit, and a secondary battery. The integration circuit is configured to output an integral signal obtained by integrating input signals. The firing circuit is configured to generate, in accordance with the integral signal, a pulse signal to be transmitted to the neuron circuit provided at a subsequent layer. The secondary battery is configured to supply the firing circuit with drive electric power used for generating the pulse signal.

Abstract: An apparatus for performing in-memory processing includes a memory cell array of memory cells configured to output a current sum of a column current flowing in respective column lines of the memory cell array based on an input signal applied to row lines of the memory cells, a sampling circuit, comprising a capacitor connected to each of the column lines, configured to be charged by a sampling voltage of a corresponding current sum of the column lines, and a processing circuit configured to compare a reference voltage and a currently charged voltage in the capacitor in response to a trigger pulse generated at a timing corresponding to a quantization level, among quantization levels, time-sectioned based on a charge time of the capacitor, and determine the quantization level corresponding to the sampling voltage by performing time-digital conversion when the currently charged voltage reaches the reference voltage.

Abstract: A memory device includes a memory cell array including a plurality of memory cells on which a programming loop is executed a plurality of times; a voltage generator configured to apply a verifying voltage to the memory cells, for verifying at least one programming state of the memory cells; and a voltage controller configured to control the voltage generator to change a level of the verifying voltage as a program loop count increases, based on temperature information about a temperature inside or outside the memory device.

Abstract: In a particular implementation, a circuit comprises: a memory array including a plurality of bit cells, where each of the bit cells are coupled to a respective bit path; a first multiplexer comprising a plurality of column address locations, where each of the plurality of column address locations is coupled to the memory array and corresponds to a respective bit path capacitance; and a variable capacitance circuit coupled to a reference path and configured to substantially match reference path capacitance to each of the respective bit path capacitances.

Abstract: A memory device includes: one or more planes each including a plurality of memory blocks; and a control circuit for selectively performing a dummy read operation before a valid read operation on the first memory block, according to whether a read command on the first memory block is firstly received from a host after a program operation is performed on a plane including the first memory block.

Abstract: Embodiments provide a scheme for determining the order of read threshold voltages used in a read error recovery operation for a memory system. A controller performs one or more read operations on a memory device using one or more read voltages among a plurality of read voltages in a set order. The controller detects a successful read operation among the one or more read operations. The controller determines one or more credits for the one or more read voltages, respectively, in response to the detected successful read operation. The controller updates the set order based on the determined credits.

Abstract: Methods, systems, and apparatuses for self-referencing sensing schemes are described. A cell having two transistors, or other switching components, and one capacitor, such as a ferroelectric capacitor, may be sensed using a reference value that is specific to the cell. The cell may be read and sampled via one access line, and the cell may be used to generate a reference voltage and sampled via another access line. For instance, a first access line of a cell may be connected to one read voltage while a second access line of the cell is isolated from a voltage source; then the second access line may be connected to another read voltage while the first access line is isolate from a voltage source. The resulting voltages on the respective access lines may be compared to each other and a logic value of the cell determined from the comparison.

Abstract: Technologies for scrambling functions in a column-addressable memory architecture includes a device having a memory and a circuitry. The memory includes a matrix storing individually addressable bit data, and the matrix is formed by rows and columns. The circuitry is to receive a request to perform a write operation of one or more bit values to one of the columns. The circuitry is further to determine a scrambler state at each location of the column, the location corresponding to a respective row and column index. The scrambler state is indicative of a function used to determine a value at the respective column location. Each of the bit values is scrambled as a function of the scrambler state for the respective column location and written thereto.

Abstract: A control circuit for a neural network system includes a first multiply accumulate circuit, a first neuron value storage circuit and a first processor. The first multiply accumulate circuit includes n memristive cells. The first terminals of the n memristive cells receive a supply voltage. The second terminals of the n memristive cells are connected with a first bit line. The control terminals of the n memristive cells are respectively connected with n word lines. Moreover, n neuron values of a first layer are stored in the first neuron value storage circuit. In an application phase, the first neuron value storage circuit controls the n word lines according to binary codes of the n neuron values. The first processor generates a first neuron value of a second layer.

Abstract: There are provided a semiconductor memory device and a method for operating the same. The semiconductor memory device includes: a memory cell array with a plurality of memory cells programmed to a plurality of program states; a peripheral circuit configured for performing a program operation on selected memory cells among the plurality of memory cells through a plurality of program loops; a current sensing circuit for determining a verify result of each of the plurality of program states by performing an individual state current sensing operation on the selected memory cells among the memory cells; and a control logic for controlling the current sensing circuit to perform the individual state current sensing operation, based on a number of program loops, among a plurality of program loops, that are performed.

Abstract: Aspects of a storage device including a memory and a controller are provided. The memory can include memory dies that draw a current from a current source during a program operation. The controller may monitor for an alarm signal from the memory dies on a first common channel between the controller and the memory dies. The alarm signal indicates that a corresponding memory die is entering an operational state that draws a peak current from the current source for the program operation. The controller can receive, from the memory dies, one or more alarm signals on the first common channel within a predetermined threshold time. The controller can transmit a postpone signal on a second common channel to the memory dies based on the one or more alarm signals received within the predetermined threshold time.