Patents Examined by Douglas M Menz
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Patent number: 10510606Abstract: A method for forming an integrated circuit (IC) package is provided. In some embodiments, a semiconductor workpiece comprising a scribe line, a first IC die, a second IC die, and a passivation layer is formed. The scribe line separates the first and second IC dies, and the passivation layer covers the first and second IC dies. The first IC die comprises a circuit and a pad structure electrically coupled to the circuit. The pad structure comprises a first pad, a second pad, and a bridge. The bridge is within the scribe line and connects the first pad to the second pad. The passivation layer is patterned to expose the first pad, but not the second pad, and testing is performed on the circuit through the first pad. The semiconductor workpiece is cut along the scribe line to individualize the first and second IC dies, and to remove the bridge.Type: GrantFiled: April 26, 2019Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yueh-Chuan Lee, Chia-Chan Chen, Ching-Heng Liu
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Patent number: 10510838Abstract: Embodiments disclosed herein relate generally to forming a source/drain region with a high surface dopant concentration at an upper surface of the source/drain region, to which a conductive feature may be formed. In an embodiment, a structure includes an active area on a substrate, a dielectric layer over the active area, and a conductive feature through the dielectric layer to the active area. The active area includes a source/drain region. The source/drain region includes a surface dopant region at an upper surface of the source/drain region, and includes a remainder portion of the source/drain region having a source/drain dopant concentration. The surface dopant region includes a peak dopant concentration proximate the upper surface of the source/drain region. The peak dopant concentration is at least an order of magnitude greater than the source/drain dopant concentration. The conductive feature contacts the source/drain region at the upper surface of the source/drain region.Type: GrantFiled: November 29, 2017Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng Chen, Liang-Yin Chen
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Patent number: 10504935Abstract: An organic light emitting display device is disclosed. The organic light emitting display device includes a light emitting element disposed in each sub-pixel area on a substrate; a pixel circuit disposed in a circuit area of each sub-pixel area to drive the light emitting element; a first signal line disposed on the substrate to contact the substrate, arranged in a first direction, and connected to the pixel circuit; a second signal line arranged in a second direction and connected to the pixel circuit; and at least two insulation films disposed between the first and second signal lines.Type: GrantFiled: November 29, 2017Date of Patent: December 10, 2019Assignee: LG Display Co., Ltd.Inventors: Woo-Chan Cho, Ho-Young Jeong, Yong-Min Kim
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Patent number: 10504724Abstract: A method includes etching a portion of a semiconductor material between isolation regions to form a trench, forming a semiconductor seed layer extending on a bottom surface and sidewalls of the trench, etching-back the first semiconductor seed layer until a top surface of the semiconductor seed layer is lower than top surfaces of the isolation regions, performing a selective epitaxy to grow a semiconductor region from the semiconductor seed layer, and forming an additional semiconductor region over the semiconductor region to fill the trench.Type: GrantFiled: November 28, 2018Date of Patent: December 10, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Lien Huang, De-Wei Yu
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Patent number: 10505000Abstract: An electronic device can include a transistor structure. In an embodiment, the transistor structure can include a channel region and a drift structure including different semiconductor base materials. In another embodiment, the transistor structure can include a source region and a drain structure including a first region, wherein the source region and the first region include different semiconductor base materials and have the same conductivity type. In another aspect, a process of forming an electronic device can include forming a semiconductor layer; forming a body region; patterning the body region and the semiconductor layer to define a trench having a sidewall; forming a first region of a drain structure along the sidewall of the trench, wherein the first region and body region include different semiconductor base materials and different conductivity types.Type: GrantFiled: December 28, 2017Date of Patent: December 10, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Peter Moens, Piet Vanmeerbeek, Gary H. Loechelt, John Michael Parsey, Jr.
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Patent number: 10497825Abstract: Disclosed are a light emitting element, which may reduce power consumption, and a light emitting device including the same. The light emitting element includes an active layer emitting light by recombination of electrons and holes respectively supplied from first and second electrodes, and a control electrode controlling light emission of the active layer. Therefore, a transistor conventionally connected to the light emitting element may be omitted and thus power loss generated due to the transistor may be prevented.Type: GrantFiled: December 28, 2017Date of Patent: December 3, 2019Assignee: LG Display Co., Ltd.Inventors: Sang-Uk Lee, Won-Yong Jang
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Patent number: 10488722Abstract: A liquid crystal display device includes a TFT substrate and a counter substrate with liquid crystal sandwiched therebetween. The TFT substrate has scanning lines 10 extending in a first direction and arrayed in a second direction and video signal lines 20 extending in the second direction and arrayed in the first direction. The TFT substrate has a display area 500 in which TFT pixels are arrayed in a matrix pattern, and a frame area 600 surrounding the display area. In the frame area 600, common bus wires 521 are formed in the same layer and with the same material as the video signal lines 20 and are impressed with a common voltage. Dummy TFTs are formed in a layer under the common bus wires 521. The scanning lines 10, extending over the frame area 600, are divided outside the display area and are interconnected by bridging wires 170.Type: GrantFiled: January 18, 2019Date of Patent: November 26, 2019Assignee: JAPAN DISPLAY INC.Inventors: Motoharu Miyamoto, Atsuhiro Katayama
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Patent number: 10490633Abstract: An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.Type: GrantFiled: October 25, 2018Date of Patent: November 26, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventor: Keiji Okumura
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Patent number: 10490764Abstract: The present disclosure provides an organic electroluminescent device and a display device. The material of the blue light emitting layer in the organic electroluminescent device comprises an electron transport material and a hole transport material that can form a blue light exciplex. The proportions respectively occupied by the electron transport material and the hole transport material of the blue light emitting layer in all materials of the blue light emitting layer match with the abilities of the red light emitting layer and the green light emitting layer to transport electrons, so that electrons and holes would not recombine within and at an edge of the portion of the blue light emitting layer that covers the red light emitting layer and the green light emitting layer when the red light emitting layer and/or the green light emitting layer is required to emit light.Type: GrantFiled: June 23, 2017Date of Patent: November 26, 2019Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Juanjuan You, Chinlung Liao
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Patent number: 10483156Abstract: A method includes electrically joining two or more semiconductor chips to a silicon bridge chip, and electrically joining the two or more semiconductor chips to a substrate structure, the silicon bridge chip extends into a recess in the substrate structure such that a top surface of the silicon bridge chip is substantially flush with a top surface of the substrate structure.Type: GrantFiled: November 29, 2017Date of Patent: November 19, 2019Assignee: International Business Machines CorporationInventor: Effendi Leobandung
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Patent number: 10472735Abstract: There is herein described a method of making a single crystal wavelength conversion element from a polycrystalline wavelength conversion element, a single crystal wavelength conversion element, and a light source containing same. By making the single crystal wavelength conversion element from a polycrystalline wavelength conversion element, the method provides greater flexibility in creating single crystal wavelength conversion elements as compared to melt grown methods for forming single crystals. Advantages may include higher activator contents, forming more complex shapes without machining, providing a wider range of possible activator gradients and higher growth rates at lower temperatures.Type: GrantFiled: April 28, 2016Date of Patent: November 12, 2019Assignee: OSRAM Opto Semiconductors GmbHInventors: John Kelso, Alan Piquette, David Johnston
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Patent number: 10461049Abstract: An aluminum electrode (2) is provided on a semiconductor device (1). A metallic film (3) for a solder joint is provided on the aluminum electrode (2). The organic protective film (4) is apart from the metallic film (3). An interval between the organic protective film (4) and the metallic film (3) is equal to or greater than half of a thickness of the organic protective film (4). Thus, even when the organic protective film (4) is deformed during sinter joining, the stress is not transmitted to the metallic film (3). Therefore, it is possible to prevent the solder connection metallic film (3) from cracking.Type: GrantFiled: December 14, 2015Date of Patent: October 29, 2019Assignee: Mitsubishi Electric CorporationInventors: Takuya Hamaguchi, Yosuke Nakata, Seiya Nakano, Masayoshi Tarutani
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Patent number: 10461025Abstract: A method for metallization during fabrication of an Integrated Circuit (IC). The IC includes a semiconductor wafer having a back surface and a front surface. The method includes etching a via hole through the semiconductor wafer. After this, a seed metal layer is deposited on the back surface of the semiconductor wafer. Thereafter, a photoresist layer is deposited on the back surface of the semiconductor wafer such that the via hole remains uncovered. After depositing the photoresist layer, a metal layer is formed along the walls of the via hole to electrically connect the back surface and the front surface of the semiconductor wafer. Finally, the photoresist layer is removed subsequent to forming the metal layer.Type: GrantFiled: January 2, 2019Date of Patent: October 29, 2019Assignee: Skyworks Solutions, Inc.Inventors: Mohsen Shokrani, Boris Gedzberg, Ronald Michels
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Patent number: 10453901Abstract: A display device and a method of manufacturing the display device are provided. A display device includes: a plurality of first emission areas and a plurality of second emission areas alternately arranged at centers of virtual quadrangles aligned adjacent to each other in a row direction and a column direction; and a plurality of third areas respectively arranged at vertexes of the virtual quadrangles, and a difference between planar areas of the first to third emission areas is less than 25% of a largest planar area among the planar areas of the first to third emission areas.Type: GrantFiled: April 3, 2018Date of Patent: October 22, 2019Assignee: Samsung Display Co., Ltd.Inventors: Hyunwoong Kim, Seungkyu Lee, Wonkyu Kwak, Jongwon Park
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Patent number: 10454058Abstract: An organic light emitting diode display device includes a substrate. A first protective layer is disposed on the substrate. A conductive line is disposed on the first protective layer. A second protective layer is disposed on the conductive line. A first electrode is disposed on the second protective layer. An organic light emitting layer is disposed on the first electrode. A second electrode is disposed on the light emitting layer. The first electrode is symmetric with respect to a center of the conductive line.Type: GrantFiled: November 29, 2017Date of Patent: October 22, 2019Assignee: SAMSUNG DISPLAY CO., LTD.Inventor: Moojong Kim
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Patent number: 10444586Abstract: A liquid crystal display (LCD) device capable of perventing impurities from permeating into a channel area of a switching element, the LCD device including: a gate electrode above a substrate; a semiconductor layer which overlaps the gate electrode; a drain electrode and a source electrode which overlap the semiconductor layer; an ohmic contact layer between the semiconductor layer and the drain electrode and between the semiconductor layer and the source electrode; a pixel electrode which is connected to one of the drain electrode and the source electrode; and a gate insulating layer between the gate electrode and the semiconductor layer, the gate insulating layer comprising fluorine. A concentration of the fluorine is decreasing, as the fluorine of the gate insulating layer being more adjacent to the substrate.Type: GrantFiled: September 12, 2018Date of Patent: October 15, 2019Assignee: Samsung Display Co., Ltd.Inventors: Taeyoung Ahn, Bogeon Jeon, Wooseok Jeon, Yungbin Chung, Eunjeong Cho
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Patent number: 10446789Abstract: A display device and a method of manufacturing a display device are provided. A display device includes a substrate; a display area on the substrate and configured to display an image; a pad portion on at least one edge of the substrate, the pad portion including at least one sink portion; an anisotropic conductive film on the pad portion and filling the at least one sink portion, the anisotropic conductive film spaced apart from an end of the substrate; and a flexible printed circuit board on the anisotropic conductive film and electrically connected to the pad portion.Type: GrantFiled: February 16, 2019Date of Patent: October 15, 2019Assignee: LG Display Co., Ltd.Inventors: Eunah Kim, Miae Kim
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Patent number: 10438160Abstract: Repurpose Intelligence System for repurposing expired food stuffs and ensuring that locked-up nutrients in these expired food stuffs find their way into the supply chain so that their values is realized.Type: GrantFiled: February 14, 2018Date of Patent: October 8, 2019Inventors: John New, Michael Dershem
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Patent number: 10431676Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a first III-V group compound semiconductor layer disposed on the substrate. The first III-V group compound semiconductor layer includes a fin structure having a top surface, a first sidewall, and a second sidewall opposite to the first sidewall. The semiconductor device also includes a second III-V group compound semiconductor layer disposed on the first III-V group compound semiconductor layer. The first III-V group compound semiconductor layer and the second III-V group compound semiconductor layer are made of different materials. The semiconductor device also includes a gate electrode disposed on the second III-V group compound semiconductor layer.Type: GrantFiled: December 28, 2017Date of Patent: October 1, 2019Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Hsin-Chih Lin, Yu-Chieh Chou
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Patent number: 10424579Abstract: A semiconductor device for electric discharge protection is disclosed. In one aspect, the semiconductor device includes a substrate having a p-type doping. The semiconductor device includes a first well and a second well having an n-type doping and arranged spaced apart within a surface layer of the substrate, and a third well having a p-type doping and arranged in the surface layer of the substrate between the first well and the second well. The semiconductor device further includes an emitter region and a base contact region having a p-type doping and arranged within a surface layer of the first well, and a collector region having a p-type doping. The collector region is arranged at least partly within a surface layer of the third well and such that it overlaps both of the first well and the second well. An integrated circuit including a semiconductor device is also provided.Type: GrantFiled: December 28, 2017Date of Patent: September 24, 2019Assignee: IMEC vzwInventors: Mirko Scholz, Shih-Hung Chen