Abstract: Aspects of the disclosure relate generally to semiconductor packaging, and specifically to semiconductor device having a lead frame having a semiconductor supporting die pad that is capable of engaging with a wire bonding clamp.

Abstract: A liquid crystal apparatus as an electro-optical device includes a TFT including a semiconductor layer and a gate electrode, a scan line electrically connected to the gate electrode and provided in a layer different from a layer where the gate electrode is provided, a capacitance line, and a conductive light shielding film electrically connected to the capacitance line. The light shielding film is provided in a layer between the gate electrode and the scan line, and in a plan view, overlaps with at least a part of a low-concentration drain region of the semiconductor layer.

Abstract: An OLED display device includes a substrate, an active element array, at least one OLED, a light absorption layer or an optical scattering layer, and an encapsulation plate. The active element array and the OLED are disposed over an upper surface of the substrate. The OLED includes a first electrode, a second electrode, and an organic light-emitting layer. The first electrode is disposed on a side adjacent to the active element array, and the second electrode is opposite to the first electrode. Both the first and second electrodes have a high transmittance and a low reflection in a wavelength range of visible light. The organic light-emitting layer is interposed between the first and second electrodes. The light absorption layer or optical scattering layer is disposed between the OLED and the substrate. The encapsulation plate is disposed over the second electrode.

Abstract: Methods and apparatus for proving a sensor assembly. Embodiments can include employing a circuit assembly having a first layer bonded to a second layer with an oxide layer, depositing bonding oxide on the second layer of the circuit assembly, and thinning the first layer of the circuit assembly after depositing the bonding oxide. A coating can be applied over at least a portion of the first layer of the circuit assembly after annealing the circuit assembly. After polishing the bonding oxide on the second surface of the second layer of the circuit assembly, a shim can be secured to the bonding oxide on the second surface of the second layer of the circuit assembly to reduce bow of the assembly. Embodiments can provide a sensor useful in focal plane arrays.

Abstract: A semiconductor structure includes a free-floating silicon-bridge chip electrically joined on a top portion to two or more semiconductor chips and electrically joined on a bottom portion to a substrate structure that includes a plurality of metal interconnect structures and a plurality of metal layers disposed on an interlevel dielectric. The silicon bridge chip is aligned with and extends into a recess located in a region of the substrate structure away from the plurality of metal interconnect structures and the plurality of metal layers such that a top surface of the silicon bridge chip is substantially flush with a top surface of the substrate structure.

Abstract: An interposer is capable of efficiently reinforcing the connecting portion between an electronic component and a substrate. The interposer is used for mounting a first electronic component on a substrate and includes a sheet-shaped spacer having at least one through-hole and including a material that does not flow during reflow soldering and a resin portion that covers at least a part of the spacer and is flowable during reflow soldering, and the through-hole is configured to store a bump of the first electronic component.

Abstract: A layout of semiconductor structure includes plural patterns arranged along a first direction to form plural columns, with each pattern spaced from each other. A region is defined by the patterns, and which includes a first edge and a second edge, with the first edge extended along the first direction, and the second edge extended along a second direction different from the first direction and being serrated. The second edge includes plural fragments, with each fragment being defined by at least two patterns. The present invention also provided a semiconductor device and a method of forming the same.

Abstract: A wafer structure and a trimming method thereof are provided. The trimming method includes the following steps. A first wafer having a first surface and a second surface opposite to the first surface is provided. A first pre-trimming mark is formed on the first surface of the first wafer, wherein forming the first pre-trimming mark includes forming a plurality of recesses arranged as a path along a periphery of the first wafer. The first wafer is trimmed on the first pre-trimming mark and along the path of the first pre-trimming mark to remove a portion of the first wafer and form a trimmed edge having first regions thereon.

Abstract: A hermetically sealed electronic package may include a thermal panel having a panel interior surface and a panel exterior surface with electronic device(s) in thermal communication with the panel interior surface. An enclosure, isolating environmental communication from internal electronic devices and modules, may be coupled to the thermal panel, and the enclosure may have an enclosure interior surface and an enclosure exterior surface. A plurality of electrical feedthroughs may be coupled to the package enclosure for signal and data transmission, and the conducting pin(s) in every electrical feedthrough may be bonded by a hydrophobic sealing material for harsh environmental electrical signal, data and power transmission. The ratio of sealing length over sealing bead diameter in the electrical feedthrough subassembly may have a preferred value from 2 to 3; and the ratio of the sealing bead diameter over pin diameter in the electrical feedthrough subassembly may have a preferred value from 1.5 to 2.

Abstract: An assembly that includes a first substrate, a second substrate, and a stress mitigation layer disposed between the first and the second substrates. The stress mitigation layer is directly bonded onto the second substrate, and the second substrate is separated from the intermetallic compound layer by the stress mitigation layer. The stress mitigation layer has a high purity of at least 99% aluminum such that the stress mitigation layer reduces thermomechanical stresses on the first and second substrates. The assembly further includes an intermetallic compound layer disposed between the first substrate and the stress mitigation layer such that the stress mitigation layer is separated from the first substrate by the intermetallic compound layer.

Abstract: There is provided a measurement device including: a first electrode and a second electrode that are configured to form an energization path via a measurement object at a front side and measure an electrical conductivity of the measurement object; and a reference electrode and an ISFET that are configured to measure a pH value of the measurement object, wherein a standard electrode of the reference electrode is disposed at a rear side of the first electrode and the second electrode.

Abstract: A method includes etching a portion of a semiconductor material between isolation regions to form a trench, forming a semiconductor seed layer extending on a bottom surface and sidewalls of the trench, etching-back the first semiconductor seed layer until a top surface of the semiconductor seed layer is lower than top surfaces of the isolation regions, performing a selective epitaxy to grow a semiconductor region from the semiconductor seed layer, and forming an additional semiconductor region over the semiconductor region to fill the trench.

Abstract: A liquid crystal display device includes a TFT substrate and a counter substrate with liquid crystal sandwiched therebetween. The TFT substrate has scanning lines 10 extending in a first direction and arrayed in a second direction and video signal lines 20 extending in the second direction and arrayed in the first direction. The TFT substrate has a display area 500 in which TFT pixels are arrayed in a matrix pattern, and a frame area 600 surrounding the display area. In the frame area 600, common bus wires 521 are formed in the same layer and with the same material as the video signal lines 20 and are impressed with a common voltage. Dummy TFTs are formed in a layer under the common bus wires 521. The scanning lines 10, extending over the frame area 600, are divided outside the display area and are interconnected by bridging wires 170.

Abstract: A semiconductor integrated circuit includes: a p?-type semiconductor substrate defining a high-potential side circuit area and a low-potential side circuit area separated from each other; a high-side n well provided in an upper part of the semiconductor substrate in the high-potential side circuit area; a high-side p well provided in the high-side n well; and a p-type semiconductor region provided in an upper part of the semiconductor substrate in the low-potential side circuit area; and n+-type semiconductor region provided to be brought contact with the p-type semiconductor region, wherein a whole n-type semiconductor region including the n+-type semiconductor region, has an impurity concentration higher than an impurity concentration of the high-side n well.

Abstract: An organic light-emitting display apparatus includes a substrate having a display area displaying an image and a periphery area. The periphery area is located next to the display area. A first organic insulating layer is disposed on the substrate. The first organic insulating layer includes a valley portion separating the first organic insulating layer from the periphery area. A plurality of organic light-emitting devices is disposed on the substrate. Each of the organic light-emitting devices includes a first electrode, an emission layer, and a second electrode, sequentially disposed over the first organic insulating layer. The second electrode covers the emission layer and the valley portion. A second organic insulating layer is disposed over the first organic insulating layer and includes a first opening exposing a center portion of the first electrode and a second opening overlapping the valley portion. A capping layer covers the second electrode.

Abstract: A display device and a method of manufacturing a display device are provided. A manufacturing method of a display apparatus includes forming a display module including a first area and including a display panel including lower and upper surfaces opposite each other, a first film under the lower surface of the display panel, a second film on the upper surface of the display panel, and an adhesive layer between the lower surface of the display panel and the first film; weakening an adhesive force of a first adhesive portion of the adhesive layer in the first area to be weaker than an adhesive force of a second adhesive portion of the adhesive layer outside the first area; cutting the first film and the adhesive layer; and removing a portion of the first film and the first adhesive portion from the first area.

Abstract: A method for forming a silicon structure. A non-limiting example of the method includes forming at least two semiconductor fins on a substrate. A polymer brush material is formed over the fins and the substrate. A block copolymer (BCP) composed of a first polymer and a second polymer which are covalently bound together is applied over the polymer brush material, such that the first polymer and second polymer self-assemble into a plurality of interleaved first microdomains and second microdomains perpendicular to and within a trench between the fins. The first microdomains are composed of the first polymer and the second microdomains are composed of the second polymer. The second microdomains can be selectively removed.

Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.

Abstract: The embodiments of the disclosure disclose a flexible substrate, a fabrication method thereof, and a flexible display apparatus. The flexible substrate includes a first organic layer and an inorganic buffer layer stacked together. The first organic layer and the inorganic buffer layer form an organic-inorganic composite structure. The expansion coefficient of the flexible substrate provided by the embodiment of the present disclosure is more matched with that of the rigid auxiliary substrate, so as to reduce the risk of warping of the rigid auxiliary substrate and then improve the process accuracy when fabricating the display device.

Abstract: A method of manufacturing a semiconductor memory apparatus, in which a plurality of memory dies are stacked, includes forming first memory dies on a wafer. An under-fill material is deposited on a wafer, on which the first memory dies are formed, to form a first part of an under-fill layer. A first portion of the under-fill layer remaining on top surfaces of the first memory dies is removed by performing a half sawing process, and parts of edge portions of the first memory dies are removed during the removal of the first portion of the under-fill layer to form first cavities. Second memory dies are formed on the first memory dies. The under-fill material is deposited on the wafer including the second memory dies formed thereon to form a second part of the under-fill layer on a remaining part of the under-fill layer.