Abstract: A semiconductor memory device and a method for manufacturing the same are provided.

Abstract: A structure (microduct) for temperature management (e.g., cooling) of the surface temperature of an electronic device (e.g., a microprocessor). In an embodiment of the present invention, the system includes an upper plate , wherein the upper plate has a bottom surface forming the top portion and sides of the microduct structure, and wherein the top surface of a lower wall forms the bottom surface of the microduct structure. The lower wall can be adapted to be coupled to a top surface of device. The microduct structure further includes a coolant that flows through the microduct to provide cooling for a device.

Abstract: There is described a back thinned sensor in which a material is added on the front surface to extend the wavelength of the sensor into wavelengths it normally does not reach. In the preferred embodiment, the back-thinned layer comprises silicon and is the base for a CMOS device or a CCD. The photocathode in a night vision device comprises in the preferred unit GaAs.

Abstract: A compact multiband Inverted-F antenna (110) that has a compact form factor and is particularly suited for manufacturability and inclusion into small form-factor devices. The Inverted-F Antenna (110) includes a first arm (150) and a substantially parallel second arm (152) connected by a conductive bridge (206). An RF feed that has an RF contact (126) and a ground contact (124) is attached to a middle portion of the second arm (150). The Inverted-F antenna (110) is suitable for mounting on an external face of a non-conductive support (112). The RF feed (150, 152) extends through the non-conductive support to facilitate electrical connection to RF circuits (108). The Inverted-F Antenna (110) has a three band RF characteristic (300), with the upper two bands chosen to form a single, continuous RF band (304).

Abstract: Various embodiments of an apparatus for holding and processing semiconductor workpieces are provided. In one aspect, an apparatus is provided that includes a first base, a second base and three elongated members coupled to and between the first base and the second base. The three elongated members are spatially arranged so that a semiconductor workpiece may be positioned therebetween. Each of the elongated members has a first lateral edge, a second lateral edge and at least one radially inwardly projecting member. The at least one radially inwardly projecting member has a third lateral edge, a fourth lateral edge and an upper surface for receiving a portion of the semiconductor workpiece and a lower surface. The third lateral edge is displaced laterally inward from the first lateral edge and the fourth lateral edge is displaced laterally inward from the second lateral edge.

Abstract: A semiconductor device is capable of adjusting an input resistance without changing an input terminal capacitance. The capacitance formed by a capacitive wiring and a comb-shaped wiring can be adjusted by changing the length of the capacitive wiring. The resistance between the capacitive wiring and the ground potential can be adjusted by changing the positions of contacts which interconnect the capacitive wiring and a resistive wiring. Since the resistance can be adjusted simply by changing the connections of the contacts, only the input resistance can be adjusted without changing the input terminal capacitance.

Abstract: A heterojunction type compound semiconductor field effect transistor includes a channel layer, a first electron supply layer, an electric field strength reducing layer, a first contact layer, a recess stopper layer, and a second contact layer sequentially stacked on a compound semiconductor substrate. This transistor has a double recess structure. The first contact layer is composed of GaAs or InGaAs doped with n type impurities with a high electron mobility. The electric field strength reducing layer is composed of intrinsic InGaP.

Abstract: An underfill material for attaching and underfilling a semiconductor component on a substrate includes a polymer base material, and electrically conductive particles in the polymer base material. The particles are configured to melt and rigidify bonded electrical connections between solder terminal contacts on the component and substrate contacts on the substrate. A size and concentration of the particles is selected to prevent electrical conductivity in X and Y directions. A method for attaching and underfilling the component on the substrate includes the steps of depositing the underfill material on the substrate or the component, placing the terminal contacts in contact with the substrate contacts while the underfill material is in a viscous or B-stage condition, bonding the terminal contacts to the substrate contacts to form the connections, and then curing the underfill material to form an underfill layer.

Abstract: An OLED display including: a transparent electrode; a reflective electrode having a transparent window; a light emissive layer disposed between the transparent electrode and the reflective electrode; and a photosensor located under the transparent window of the reflective electrode to sense light produced by the light emissive layer.

Abstract: The present invention relates to a technique for fabricating a mechanical or visual alignment fiducial on a laser die particularly adapted for application with a laser die that is a buried structure edge emitting laser. In fabricating the device, the fiducial and the active mesa are formed in the same photolithography patterning step, using conventional techniques. The active is then buried with regrowth layers. The regrowth layers are subsequently selectively etched to expose the fiducial, leaving the active region protected and buried.

Abstract: New methods for fabrication of silicon microstructures have been developed. In these methods, an etching delay layer is deposited and patterned so as to provide differential control on the depth of features being etched into a substrate material. Structures having features with different depth can be formed thereby in a single etching step.

Abstract: A method of fabricating integrated circuit wafers, in accordance with this invention comprises the following steps. Provide an integrated circuit wafer having devices formed therein covered with a metal layer and a photoresist layer over the metal layer which is selectively exposed and developed forming a photoresist mask. Introduce the wafer into a multi-chamber system, patterning the metal layer by etching and then exposing the mask to light in a cooled chamber wherein the light is derived from a source selected from a mercury lamp and a laser filtered to remove red and infrared light therefrom before exposure of the wafer thereto. The chamber is cooled by a refrigerant selected from water and liquefied gas Then remove the wafer, and load it into a photoresist stripping tank to remove the photoresist mask with a wet photoresist stripper. Place the wafer in a batch type plasma chamber after removing the photoresist mask.

Abstract: Disclosed is a method and an apparatus for manufacturing a barrier layer of semiconductor device. The disclosed comprises the steps of: forming an interlayer insulating layer having a contact hole on a semiconductor substrate; forming a Ti layer on the contact hole and on the interlayer insulating layer; and reacting the Ti layer with nitrogen radical to transform a part of the Ti layer into a TiN layer.

Abstract: An imaging composition comprising a mixture of a solvent and a functional material; wherein the solvent is a compressed fluid and the functional material is a electron transporting material which is dissolved, dispersed and/or solubilized in the compressed fluid; wherein the mixture is thermodynamically stable or thermodynamically metastable or both; wherein the functional material is solvent-free upon deposition on a substrate; and wherein the functional material forms a solid film upon deposition on the substrate.

Abstract: A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is optionally powered by a supply voltage that is greater than a permitted supply voltage for a processes technology that is used to fabricate the CMOS gain stage. In order to protect CMOS devices within the CMOS gain stage, optional drain-to-bulk junction punch-through protection circuitry is disclosed. A variety of optional features can be implemented alone and/or in various combinations of one another. Optional features include process-voltage-temperature (“PVT”) variation protection circuitry, which renders a gain relatively independent of process, voltage, and/or temperature variations. Optional features further include bandwidth enhancement circuitry.

Abstract: An InGaN layer is formed on an undercoat layer of the same composition as the InGaN layer. The composition of the undercoat layer may be changed continuously or stepwise.

Abstract: An LCD fabricated by forming gate lines, gate electrodes, gate pads, vertical patterns, and a first gate shorting bar on a substrate, forming channels over the gate electrodes, forming data lines, source electrodes, drain electrodes, and a second shorting bar, forming a passivation layer, patterning the passivation layer to form drain contact holes to the drain electrodes, data pad contact holes to the data pads, first connecting contact holes to the first gate shorting bar, second connecting contact holes to the second gate shorting bar, and etching holes to the vertical patterns, forming a transparent conductive layer, and patterning the transparent conductive layer to form pixel electrodes, first pad connectors that connect odd numbered gate pads to the first gate shorting bar, and second pad connectors that connect the even numbered gate pads to the second gate shorting bar, wherein the vertical patterns are etched via the etching holes.

Abstract: An embodiment of the invention is a method to reduce light induced corrosion and re-deposition of a metal, 8, (such as copper) that is used to make the interconnect wiring during the semiconductor manufacturing process. The light induced corrosion and re-deposition is caused by the exposure of a P-N junction to light, causing a photovoltaic effect. A photon-blocking layer, 13, is used in the invention to reduce the amount of exposure of the P-N junction to light. The photon blocking layer, 13, of the invention may be a direct band-gap material with a band-gap energy that is less than the lower edge of the energy spectrum of a typical light source used in the semiconductor manufacturing facility (typically less than 1.7 eV).

Abstract: The invention relates to a method for producing an optical transmitting and receiving device (1, 1a) comprising a light emitting transmission element (3, 3a) and a receiving element (4, 4a) which converts this light into an electrical magnitude. The transmission and receiving elements are inserted into a silicon substrate. The optical transmitting and receiving device (1) is preferably inserted in a monolithic manner into a common substrate, comprising a sequence of superimposed layers for the light emitting transmission element (3) and the light receiving element (4). An electrically insulating intermediate layer (9, 9a) is incorporated between the transmission and receiving element.

Abstract: A semiconductor device and a fabricating method for the same are disclosed, in which when forming a capacitor sacrificial film pattern, even if a misalignment occurs, the degradation of the dielectric property due to a direct contact between the contact plug and the dielectric medium can be prevented. The semiconductor device includes a connecting part connected through an insulating layer of a substrate to a conductive layer, a seed separating layer formed around the connecting part and the insulating layer to provide an open region exposing at least part of the connecting part, a seed layer filled into the open region of the seed separating layer and a capacitor. The capacitor includes of a lower electrode formed upon the seed layer, a dielectric medium formed upon the lower electrode, and an upper electrode formed upon the dielectric medium.