Abstract: There is provided a spin valve transistor that comprises a collector region made of semiconductor, a base region provided on the collector region and including a first ferromagnetic layer whose magnetization direction changes in accordance with a direction of an external magnetic field, a barrier layer provided on the base layer and made of insulator or semiconductor, and an emitter region provided on the barrier layer and including a second ferromagnetic layer whose magnetization direction is fixed.

Abstract: Failure light emission of an EL element due to failure film formation of an organic EL material in an electrode hole 46 is improved. By forming the organic EL material after embedding an insulator in an electrode hole 46 on a pixel electrode and forming a protective portion 41b, failure film formation in the electrode hole 46 can be prevented. This can prevent concentration of electric current due to a short circuit between a cathode and an anode of the EL element, and can prevent failure light emission of an EL layer.

Abstract: A III-nitride light emitting device including a substrate, a first conductivity type layer overlying the substrate, a spacer layer overlying the first conductivity type layer, an active region overlying the spacer layer, a cap layer overlying the active region, and a second conductivity type layer overlying the cap layer is disclosed. The active region includes a quantum well layer and a barrier layer containing indium. The barrier layer may be doped with a dopant of first conductivity type and may have an indium composition between 1% and 15%. In some embodiments, the light emitting device includes an InGaN lower confinement layer formed between the first conductivity type layer and the active region. In some embodiments, the light emitting device includes an InGaN upper confinement layer formed between the second conductivity type layer and the active region. In some embodiments, the light emitting device includes an InGaN cap layer formed between the upper confinement layer and the active region.

Abstract: A semiconductor device for electro-optic applications includes a rare-earth ions doped P/N junction integrated on a semiconductor substrate. The semiconductor device may be used to obtain laser action in silicon. The rare-earth ions are in a depletion layer of the doped P/N junction, and are for providing a coherent light source cooperating with a waveguide defined by the doped P/N junction. The doped P/N junction may be the base-collector region of a bipolar transistor, and is reverse biased so that the rare-earth ions provide the coherent light.

Abstract: When a plurality of semiconductor layers including a nitride compound layer containing indium are stacked on a substrate, materials of layers above the indium containing nitride compound layer are limited to specific compounds, or their growth temperatures are limited within a predetermined range, to suppress thermal deterioration of the nitride compound layer containing indium or deterioration of the interface and to thereby grow a high-quality semiconductor light emitting element using nitride compound semiconductors.

Abstract: Disclosed are a display system and a method of producing the same. In the present invention, a hexagonal pyramid shaped GaN semiconductor light-emitting device selectively crystal-grown is fixed on an upper surface of a substrate by embedding it in an insulation layer formed of an epoxy resin. Then the insulation layer is selectively dry etched in an oxygen plasma atmosphere to expose an upper end portion of the GaN semiconductor light-emitting device. A conductor film is formed on the entire surface, and a required portion of the conductor film is left as a lead-out electrode while the unrequired portion is removed by lithography.

Abstract: A method of manufacturing a semiconductor component includes providing a substrate (110) with a surface (119), providing a layer (120) of undoped gallium arsenide over the surface of the substrate, forming a gate contact (210) over a first portion of the layer, and removing a second portion of the layer.

Abstract: A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band gap of the conventional practical SiGe (the Ge content is about 10%), and good crystalline can be maintained after a heat treatment. As a result, a narrow band gap base with no practical inconvenience can be realized.

Abstract: The invention relates to a method for production of an integrated limiter. The integrated limiter with PIN diodes has the following structure: at least one PIN diode is disposed on a highly conductive n+substrate in a first level, at least one resistor is disposed in a second level, at least one capacitor is disposed in a third level, connecting metallization is applied on the third level and the levels are interconnected as an integrated limiter.

Abstract: Microswitch, comprising a base element (G) with a contact surface (KG) and an electrode (EG), and a switching element (S) with a contact surface (KS) and an electrode (ES) disposed opposite the electrode (EG) of the base element (G) at a distance (g). The switching element (S) is provided with a spring constant and is connected at least with a part of its edge portion with the base element (G) in a fixed manner. The contact surfaces (KG, KS) form a switching contact which is closable against a reaction force caused by the spring constant by means of a voltage applied to the electrodes (EG, ES). The base element (G) and the switching element (S) each comprise an auxiliary electrode (HG, HS) at a distance (a) from the electrode (EG, ES), to which a voltage can be applied. For opening the switching contact the electrodes (EG, ES) have a first voltage potential (U1) and the auxiliary electrodes have a second voltage potential (U2) of the voltage.

Abstract: An integrated circuit device includes a thin semiconductor layer disposed on a surface of a wafer, a plurality of wafer-scale integrated (WSI) circuits formed on the semiconductor layer, and a node formed on the semiconductor layer that provides an optoelectronic interface to an axial optical data bus for high-speed optical interconnectivity between the WSI circuits and other external devices interconnected to the optical data bus.

Abstract: A method for integrating a compound semiconductor with a substrate of high thermal conductivity is provided. The present invention employs a metal of low melting point, which is in the liquid state at low temperature (about 200° C.), to form a bonding layer. The method includes the step of providing a compound semiconductor structure, which includes a compound semiconductor substrate and an epitaxial layer thereon. Then, a first bonding layer is formed on the epitaxial layer. A substrate of thermal conductivity greater than that of the compound semiconductor substrate is selected. Then, a second bonding layer is formed on the substrate. The first bonding layer and the second bonding layer are pressed to form an alloy layer at low temperature.

Abstract: The semiconductor substrate of the integrated circuit includes at least one dielectrically isolating, vertical buried trench (2) having a height at least five times greater than its width, the trench laterally separating two regions (4, 5), and an epitaxial semiconductor layer (6) coveting the trench. An application is advantageously suited to MOS, CMOS and BiCMOS technologies.

Abstract: A zirconium silicate layer 103 is formed on a silicon substrate 100, a zirconium oxide layer 102 is also formed on the zirconium silicate layer 103, and the zirconium oxide layer 102 is then removed, thereby forming a gate insulating film 104 made of the zirconium silicate layer 103.

Abstract: A method of using critical dimension measurements to control stepper process parameters is disclosed. In one illustrative embodiment, the method comprises forming a masking layer above a process layer, the masking layer having a plurality of features formed therein, measuring at least one critical dimension of a plurality of features positioned within at least one exposure field of a stepper exposure process used in forming the features, and determining a tilt of the masking layer within at least one exposure field based upon the measured critical dimensions of the plurality of features. In one illustrative embodiment, the system comprises a metrology tool adapted to measure at least one critical dimension of a plurality of features in a masking layer and a controller for determining a tilt of the masking layer based upon the measured critical dimensions of said plurality of features.

Abstract: In order to prevent silicides from getting under side walls when the silicides are formed over MOSFET formed over an SOI substrate, trenches are defined in the SOI substrate and side walls are formed over the trenches, whereby the silicides are blocked so as not to get under a gate insulator with a lower portion of each side wall as a structure convex in a downward direction of the substrate. Thus, an increase in gate withstand voltage, a decrease in gate leakage current and control on a short channel effect are achieved.

Abstract: Disclosed is a method of horizontally growing carbon nanotubes, in which the carbon nanotubes can be selectively grown in a horizontal direction at specific locations of a substrate having catalyst formed thereat, so that the method can be usefully utilized in fabricating nano-devices. The method includes the steps of: (a) forming a predetermined catalyst pattern on a first substrate; (b) forming a vertical growth preventing layer on the first substrate, which prevents carbon nanotubes from growing in a vertical direction; (c) forming apertures through the vertical growth preventing layer and the first substrate to expose the catalyst pattern through the apertures; and (d) synthesizing carbon nanotubes at exposed surfaces of the catalyst pattern in order to grow the carbon nanotubes in the horizontal direction.

Abstract: An n-type layer of the opposite conduction type composed of n-GaN is formed between a light emitting layer and a p-type cladding layer composed of p-AlGaN. The bandgap of the n-type layer of the opposite conduction type is larger than the bandgap of the light emitting layer and is smaller than the bandgap of the p-type cladding layer.

Abstract: In one embodiment, a process for fabricating a high-K layer comprising the steps of: placing a semiconductor substrate into a first chamber of a deposition apparatus; supplying high-K precursors to the deposition apparatus; generating ions or molecules of high-K material from the high-K precursors in a second chamber of the deposition apparatus, the second chamber being remote from the first chamber; passing the ions or molecules of high-K material from the second chamber to the first chamber; and depositing a high-K layer upon the semiconductor substrate.

Abstract: The bottom and the sides of a lower part of recess formed in the substrate has an insulating structure. A first part of the conductive structure of a first electric conductivity type is located in the lower part of the recess. A second part of the conductive structure of a second electric conductivity type, lower than the first type, is located in an upper part and borders the region of the substrate at the sides of the recess. The conductive structure has a diffusion barrier between its first and second parts. The conductive structure is configured as a bit line of a DRAM cell configuration with a vertical transistor, whereby S/Du represents the lower source/drain area and S/Do represents the upper source/drain area connected to a memory capacitor. Or, the conductive structure is configured as a memory capacitor and the upper source drain/area is connected to a bit line.