Abstract: A semiconductor arrangement with a vertical power semiconductor switch and an integrated CMOS or bipolar circuit is provided, whereby the integrated CMOS or bipolar circuit is arranged on a semiconductor islet insulated from a first semiconductor material region by a buried insulating layer. The first semiconductor material region is included as a part of the structure of the power semiconductor switch. The buried insulating layer is surrounded by a second semiconductor material region arranged between it and the first semiconductor material region, the doping of which is the opposite of that of the first semiconductor material region. The second semiconductor region is coupled to the first semiconductor region by a circuit. This circuit does not directly connect the potential of the second semiconductor material region with the potential of the first semiconductor material region.

Abstract: A MOSFET includes a first SiC semiconductor contact layer, a SiC semiconductor channel layer supported by the first SiC contact layer, and a second SiC semiconductor contact layer supported by the channel layer. The second contact and channel layers are patterned to form a plurality of gate region grooves therethrough. Each of the gate region grooves includes a base surface and side surfaces which are covered with groove oxide material. A plurality of metal gate layers are provided, each being supported in a respective one of the plurality of grooves. A plurality of deposited oxide layers are provided, each in a respective one of the grooves so as to be supported by a respective one of the plurality of metal gate layers. A first metal contact layer is applied to the surface of the first SiC contact layer, and a second metal contact layer is applied to a portion of the surface of the second SiC contact layer.

Abstract: An electronic device which includes, a couple of first conduction regions which are capable of confining carriers, a second conduction region having a higher energy level than those of the first conduction regions, and a first electrode for impressing a voltage on the first conduction regions, wherein when a voltage is impressed via the first electrode between the couple of first conduction regions, carriers are caused to move due to a tunneling effect from one of the first conduction regions via the second conduction region to the other of the first conduction regions, and when the voltage impressed between the couple of first conduction regions is removed, carriers are confined mainly in the one of the first conduction regions.

Abstract: A bipolar transistor in which the emitter possesses a double "mesa" structure so as to achieve the maximum avoidance of the phenomena of electron/hole recombinations that have a deleterious effect on the current gain. The double mesa emitter can be made out of an alternation of materials M.sub.I /M.sub.II having different types of behavior with respect to a pair of etching methods. These materials may be GaInP and GaAs.

Abstract: A Coulomb-blockade element includes a silicon layer formed on a substrate through an insulating film. The silicon layer includes a narrow wire portion and first and second electrode portions. The narrow wire portion serves as a conductive island for confining a charge. The first and second electrode portions are formed to be connected to the two ends of the narrow wire portion and are wider than the narrow wire portion. Each of the first and second electrode portions has constrictions on at least one of the upper and lower surfaces thereof, which make a portion near the narrow wire portion thinner than the narrow wire portion.

Abstract: An impurity diffusion surface layer is formed in a surface of a silicon substrate, and an aluminum electrode is arranged in direct contact with the impurity diffusion layer. The surface layer contains Ge as an impurity serving to change the lattice constant in a concentration of at least 1.times.10.sup.21 cm.sup.-1 under a thermal non-equilibrium state. The lattice constant of the surface layer is set higher than that of silicon containing the same concentration of germanium under a thermal equilibrium state. As a result, it is possible to decrease the Schittky barrier height at the contact between the surface layer and the electrode. The surface layer also contains an electrically active boron as an impurity serving to impart carriers in a concentration higher than the critical concentration of solid solution in silicon under a thermal equilibrium state. The presence of Ge permits the carrier mobility within the surface layer higher than that within silicon.

Abstract: The present invention provides a MOS field effect transistor comprising: a semiconductor substrate having a first conductivity type; source/drain regions of a second conductivity type; lightly doped regions covering the bottom of the source/drain regions and surrounding the source/drain regions, the lightly doped regions having the second conductivity type and a lower impurity concentration than an impurity concentration of the source/drain regions; an off-set region surrounding the lightly doped regions, the off-set region having the first conductivity type, the off-set region having a lower impurity concentration than the impurity concentration of the lightly doped regions; and a channel stopper region having the first conductivity type, the channel stopper region having a higher impurity concentration than the impurity concentration of the off-set region, the channel stopper region surrounding the off-set region, the channel stopper region having projected portions under a gate electrode, the projected por

Abstract: Provided is a press contact type semiconductor device which improves the shape of an insulator formed along an outer peripheral edge and a major surface of a semiconductor substrate, simplifies alignment of an anode heat compensator and a cathode heat compensator, causes no biting, causes no separation in molding, and has excellent heat dissipation. In the press contact type semiconductor device, the inner periphery of a ring-shaped insulator (22) which is formed along an edge of the overall periphery and a major surface of a semiconductor substrate (6) provided with a P-N junction in its interior comprises a tapered portion (22a) along the inner peripheral direction and a vertical portion (22b) forming a perpendicular inner peripheral diameter which is continuous to this tapered portion (22a).

Abstract: In a semiconductor device comprising a semiconductor chip, a heat radiation plate mounting the semiconductor chip thereon and having a plurality of rounded corner portions of a first radius, a ceramic substrate for mounting the heat radiation plate, and a metallize pattern formed onto the ceramic substrate for soldering the heat radiation plate onto the ceramic substrate, the metallize pattern has a plurality of rounded corner portions of a second radius. The metallize pattern is larger than the heat radiation plate in area. The first radius is greater than the second radius.

Abstract: A semiconductor device having: an underlie having a semiconductor surface capable of growing thereon single crystal; and a first semiconductor layer, the first semiconductor layer including: a first region of group III-V compound semiconductor epitaxially grown on generally the whole area of the semiconductor surface; and second regions of group III-V compound semiconductor disposed and scattered in the first region, the second region having a different composition ratio of constituent elements from the first region, wherein lattice constants of the first and second regions in no strain state differ from a lattice constant of the semiconductor surface, and a difference between the lattice constant of the second region in no strain state and the lattice constant of the semiconductor surface is greater than a difference between the lattice constant of the first region in no strain state and the lattice constant of the semiconductor surface.