Abstract: The present disclosure provides a system and method for forming device on an insulator material. First, a semiconductor depletion material is formed with a predetermined height and width overlying a predetermined portion of the substrate to from an active region. An isolation material formed on top of the substrate surrounding the active region so as to bury a bottom portion of the active region therein, thereby exposing a top portion of the active region. A gate dielectric layer is deposited for covering the exposed the top and two sidewalls of the top portion of the active region, and at least one gate electrode is then formed on top of the gate dielectric layer and extending through two sidewalls thereof to reach the isolation material.

Abstract: A photoelectric conversion device taking the form of a thin film and having a substrate exhibiting poor thermal resistance. The device prevents thermal deformation which would normally be caused by local application of excessive heat to the substrate. The device has output terminals permitting the output from the device to be taken out. The output terminals are formed on the surface of the substrate opposite to the photoelectric conversion device. The device further includes electrical connector portions for electrically connecting the electrodes of the device with the output terminals. The present invention also provides a method of treating a substrate having poor thermal resistance with a plasma with a high throughput. The substrate is continuously supplied into a reaction chamber and treated with a plasma. This supply operation is carried out in such a way that the total length of the substrate existing in a plasma processing region formed by electrodes is longer than the length of the electrodes.

Abstract: A method and apparatus for repair of a multi-chip module, such as a memory module, is provided, where at least one redundant or auxiliary chip attach location is provided on the substrate of the multi-chip module. The auxiliary chip attach location preferably provides contacts for attachment of more than one type of replacement semiconductor chip. Accordingly, when one or more chips on the multi-chip module are found to be completely or partially defective, at least one replacement chip can be selected and attached to the auxiliary location to provide additional memory to bring the module back to its design capacity.

Abstract: Semiconductor devices are provided which can be configured as optically activated memories or single photon detectors. The devices comprise an active layer with a plurality of quantum dots and an active layer. The devices are configured so that charge stored in the quantum dots affects the transport and/or optical characteristics etc of the active layer.

Abstract: A real index guided semiconductor laser device includes an optical waveguide layer at least on one side of an active layer that has a band gap energy not less than that of the active layer; a cladding layer on an outer side of the optical waveguide layer that has a band gap energy not less than that of the optical waveguide layer; a refractive index control layer having a striped window, buried in the optical waveguide layer by selective growth; and a semiconductor layer formed in the optical waveguide layer by selective growth prior to the selective growth of the refractive index control layer. In a laminated portion including the semiconductor layer and the refractive index control layer, a change in effective refractive index due to a change in thickness of the semiconductor layer is smaller than that of the refractive index control layer.

Abstract: A lead frame assembly including at least two layers. A first of the lead frame layers includes a first wide, electrically conductive bus and a plurality of leads that extend substantially unidirectionally from a single edge of the lead frame assembly. The second lead frame layer includes a second wide, electrically conductive bus that is superimposed over the first bus and a plurality of lead fingers extending substantially unidirectionally from a single edge of the lead frame assembly. Preferably, the lead fingers of both the first and second layers extend in substantially the same direction. An insulator element is disposed between the first and second buses. One of the buses is connectable to a power supply source (Vcc), while the other is connectable to a power supply ground (Vss). Thus, the co-extensive portions of the first and second buses form a decoupling capacitor.

Abstract: A method and structure for blowing a fuse including removing an insulator above a fuse link and etching the fuse link.

Abstract: In a semiconductor light-emitting device including a substrate, a first compound semiconductor layer including an active layer formed on the substrate, a second compound semiconductor layer of a ridge type formed on the first compound semiconductor layer, and a protective film formed above the first compound semiconductor layer on both sides of the second compound semiconductor layer, the disclosed semiconductor light-emitting device has a current blocking layer formed above the first compound semiconductor layer outside the protective film. This semiconductor light-emitting device is with a high production yield since readily cleaved and assembled, with adequately squeezed currents, and with, when assembled in the junction-down type, a high output and a longer life span.

Abstract: A heterostructure comprising: a buffer layer; a bottom barrier layer formed on the buffer layer; a quantum well layer formed on the bottom barrier layer; a top barrier layer formed on the quantum well layer; and a p-doped cap layer formed on the top barrier layer; wherein a portion of the cap layer is etched to form conducting electrons in the quantum well layer below the etched portion of the cap layer. A method of etching comprising the steps of: providing a heterostructure; providing an etchant solution comprising acetic acid, hydrogen peroxide, and water; and contacting the etchant solution to the heterostructure to etch the heterostructure.

Abstract: A particle filter for a partially enclosed microelectromechanical systems that include a substrate material having at least one micro-device formed thereon. The particle filter includes a first structural layer forming a filter bottom and a second structural layer forming a filter wall. The filter bottom and filter wall are interconnected by at least one support feature to define a particle trap between the filter wall and filter bottom. The particle trap is a gap formed by mating, but non-interconnected portions of the filter wall and filter bottom that operates to trap and prevent particles from passing beyond the filter bottom into the microelectromechanical system.

Abstract: A method of inhibiting pattern collapse using relacs (resist enhancement lithography assisted by chemical shrink) is disclosed herein. More particularly, the present invention relates to a method of forming photoresist patterns by coating relacs material on an underlying layer before coating photoresist material thereon and then heating the layer to inhibit pattern collapse.

Abstract: In a method for producing a semiconductor configuration that includes at least two semiconductor elements, at least two differently doped surface regions are embodied on the top side of a semiconductor substrate. After that, an active layer structure including a plurality of layers is constructed on each of the surface regions, and each layer structure is associated with one of the semiconductor elements. Whichever are the lowermost electrically conductive layers toward the substrate in the active layer structures are electrically separated from one another.

Abstract: A PIN photodiode and method for forming the PIN photodiode are shown where an intrinsic layer of the photodiode can be made arbitrarily thin and a second active region of the photodiode substantially shields a first active region of the photodiode. A fabrication substrate is lightly doped in order to form the intrinsic layer of the photodiode. A void is formed in a first surface of the fabrication substrate and a first active region of the photodiode having a first conductivity type is formed in the void. An oxide layer is also formed upon the first surface of the fabrication substrate. A handling substrate is bonded to the first surface of the fabrication substrate. A second surface of the fabrication substrate is then lapped to a obtain a preselected thickness of the intrinsic layer. A depth of the void is selected such that a portion of the first active region is exposed at the second surface of the fabrication substrate after lapping.

Abstract: A method for forming on a Ge or Si monocrystalline substrate successive Si/Ge, Si/SiGe, or Si/SiGe/Ge layers for a Ge substrate and inversely for a Si substrate is described. Electrochemical treatment of the stack of layers to make the layers porous and form therein residual crystallites is also described. The invention may be used to provide devices having layers of planes of quantum drops.

Abstract: The present invention relates to an SOI semiconductor device and a method for fabricating an SOI semiconductor device, in which the portions formed with silicide layers are laterally restricted by spacers to a predetermined range in the diffusion regions to be used for diodes or well resistors. In this manner, it is possible to fix the length of distance between the sides of a silicide layer and a diffusion region, greater than that available in the prior art techniques, thereby minimizing power leakage at the sides of the diffusion regions.

Abstract: A semiconductor device comprises a base substrate, an insulating film formed on the substrate, an undoped first and lattice-relaxed semiconductor layer formed on the insulating film, a second semiconductor layer having a tensile strain and formed on the first semiconductor layer, and a MISFET formed on the second semiconductor layer. Since the MISFET is formed in a strained Si layer, electrons are prevented from scattering in a channel region, improving the electron mobility. Furthermore, since the MISFET is formed in a thin SOI layer having a thickness of 100 nm or less, it is possible to reduce a parasitic capacitance in addition to the improvement of the electron mobility. As a result, the MISFET excellent in drivability can be obtained.

Abstract: An electronic component such as a surface acoustic wave component has a chip a piezoelectric substrate with electrically conductive structures thereon and a base plate having external electrical terminal elements that are contacted to the electrically conductive structures of the chip. A protective film is applied onto the chip surface carrying the electrically conductive structures. The surface of the protective film facing away from the piezoelectric substrate carries electrical contact elements that are connected, to the electrically conductive structures of the chip via through-contacts in the protective film and/or directly via bumps, as well as to the electrical terminal elements of the base plate.

Abstract: Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.

Abstract: A field oxide surrounding an active region, an N-type doped layer formed in the active region, and an electrode formed on the field oxide in the vicinity of the active region are provided on a P-type semiconductor substrate. During the operation as a constant voltage device, a desired voltage is applied to the electrode. Then, trapping of carriers in the interface between the field oxide and the semiconductor region can be suppressed, although such trapping is ordinarily caused by a reverse breakdown phenomenon at the pn junction between the doped layer and the P-type semiconductor substrate. Accordingly, the variation in strength of the electric field between the doped layer and the semiconductor substrate can be suppressed. As a result, it is possible to suppress a variation in reverse withstand voltage, which is usually caused by a reverse breakdown voltage at a pn junction, for a semiconductor device functioning as a constant voltage device.

Abstract: A high frequency semiconductor integrated circuit device having a semiconductor chip, a package for housing the semiconductor chip and a ground conductor, comprises a first package terminal for transferring a high frequency signal; a second package terminal which is either a package terminal for transferring a high frequency signal or a package terminal for supplying current to a node at which a high frequency signal is transferred or to a drain of a transistor; a third package terminal disposed between the first and second package terminals, for applying a bias voltage to a circuit element of the integrated circuit through a first resistor; and a first capacitor disposed in the package, and having one electrode connected between the third package terminal and the first resistor and the other electrode connected to the ground conductor. The integrated circuit device provides sufficient high frequency isolation between package terminals.