Patents Examined by Dustin Bone
  • Patent number: 9996269
    Abstract: Method including receiving first and second identification data relative to data blocks to be transmitted via data bus between processor and system memory. Listening data transmitted via data bus to detect block data corresponding to the first or second identification data; storing in a first location of temporary storage a first data block transmitted via bus and corresponding to first identification data; storing in a second location of temporary storage a second data block transmitted via bus and corresponding to the second identification data. The storing of the first and second data blocks being performed without disturbing transfer of the first and second data blocks via data bus. When the first and/or second data blocks are stored in the temporary storage activating their respective signature calculator connected to the location of the temporary storage to compute a signature of the data block, and storing the signature in a result memory.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: June 12, 2018
    Inventor: Dmitriy Gusev
  • Patent number: 9977608
    Abstract: A digital memory imaging system for imaging the digital memory of a target computer (1) comprising: a plurality of removable data storage devices (3, 5, 7, 9, 11, 13) each receivable by the target computer (1); an imaging means configured to image the digital memory of the target computer; an output means to output the imaged digital memory as a series of data blocks to two or more of the removable data storage devices (3, 5, 7, 9, 11, 13).
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: May 22, 2018
    Assignee: MOBILE CONTENT MANAGEMENT SOLUTIONS LIMITED
    Inventor: Paul Farrell
  • Patent number: 9971696
    Abstract: A file-system filter driver is attached to each cache volume containing a cache and a source volume containing a source file. The file-system filter driver intercepts requests and may redirect the requests to the cache. The redirection may be based on metadata information corresponding to the file or folder associated with a given request. Redirection to the cache prevents an application or user from directly accessing or modifying the source volume, which may be shared among multiple client devices. Redirecting requests to the cache also permits user-specific modifications to be stored in the cache. A merged view of the source volume and the cache may then be presented to the user or an application, reflecting the user-specific modifications without affecting the source volume.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: May 15, 2018
    Assignee: Dell Products L.P.
    Inventors: Sergii Liashenko, Puneet Kaushik, Rushikesh P. Patil, Satya Mylvara
  • Patent number: 9940229
    Abstract: Technologies for persistent memory programming include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may assign a virtual memory address of a target location in persistent memory to a persistent memory pointer using persistent pointer strategy, and may dereference the pointer using the same strategy. Persistent pointer strategies include off-holder, ID-in-value, optimistic rectification, and pessimistic rectification. The computing device may log changes to persistent memory during the execution of a data consistency section, and commit changes to the persistent memory when the last data consistency section ends. Data consistency sections may be grouped by log group identifier. Using type metadata stored in the nonvolatile region, the computing device may identify the type of a root object within the nonvolatile region and then recursively identify the type of all objects referenced by the root object. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: Xipeng Shen, Youfeng Wu, Cheng Wang, Hyunchul Park, Hongbo Rong
  • Patent number: 9933944
    Abstract: An information processing system comprises a processor. The processor executes a process that causes the information processing system to perform first writing, when requested to write data, data from which to subtract remainder data obtained by dividing a data size of write target data by a first data size of first processing unit data, the first data size being a size of processing unit data of a reading/writing process in a first storage device, in the write target data requested to be written to the first storage device and second writing the remainder data not being written by the first writing to a second storage device in which to set a second data size of second processing unit data, the second data size being smaller than the first data size of the first processing unit data.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: April 3, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Atsushi Nukariya, Tsuyoshi Hashimoto
  • Patent number: 9928181
    Abstract: A computing device within a reflective memory system includes a memory block and a special purpose processor. The memory block includes a plurality of memory areas, which are configured to store data of a corresponding one of a plurality of external devices. The special purpose processor is configured to intercept a write request. The write request is associated with a first external device of the plurality of external devices, and the first external device is associated with a first memory area of the plurality of memory areas. The special purpose processor is configured to determine whether the write request is valid or invalid, write the data of the first external device to the first memory area if the write request is valid, and prevent the data of the first external device from being written to the memory block if the write request is invalid.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: March 27, 2018
    Assignee: GE-HITACHI NUCLEAR ENERGY AMERICAS, LLC
    Inventors: Oscar L. Meek, Gregory S. Droba
  • Patent number: 9875056
    Abstract: An information processing system includes a plurality of physical machines, in each of which a virtual machine is constructed, and a migration processing unit that executes a migration process for moving a migration source virtual machine, constructed on a migration source physical machine, onto a migration destination physical machine during operation of the migration source virtual machine. The migration processing unit includes a memory data transfer processing unit that transfers first data stored in a first memory of the migration source virtual machine from the first memory to a second memory of the migration destination physical machine, transfers second data written in the first memory during the transfer to the second memory, and, when a transfer completion scheduled time for the first and second data exceeds an allowed time, restricts writing executed on the first memory.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: January 23, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Atsushi Sakai
  • Patent number: 9875064
    Abstract: According to one embodiment, a storage system includes a first storage and a controller which controls the first storage. The first storage includes a first group which includes a plurality of pages which are data write units and include first nonvolatile memories, and a first counter which counts the number of data writes to the first group. The controller determines whether all the pages in the first group has been written to or not.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: January 23, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Shinichi Kanno
  • Patent number: 9852075
    Abstract: Provided are a computer program product, system, and method to allocate a segment of a buffer to each of a plurality of threads to use for writing data. Each of a plurality of threads are assigned to one of a plurality of segments in a buffer, wherein the threads write to the segment to which they are assigned. A free segment list indicates segments which are not assigned to one of the threads. In response to one of the segments assigned to one of the threads becoming a full segment having less than a threshold amount of free space, indicating the full segment assigned to the thread in the free segment list and assigning one of the segments in the free segment list to the thread different from the full segment.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: December 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Herve G. P. Andre, Juan J. Ruiz, Trung N. Nguyen
  • Patent number: 9818485
    Abstract: An erase method of a nonvolatile memory device includes setting an erase mode, and performing one of a normal erase operation and a quick erase operation according to the set erase mode. The normal erase operation is performed to set a threshold voltage of a memory cell to an erase state which is lower than a first erase verification level. The quick erase operation is performed to set a threshold voltage of a memory cell to a pseudo erase state which is lower than a second erase verification level. The second erase verification level is higher than the first erase verification level.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: November 14, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun Chu Oh, Jongha Kim, Junjin Kong
  • Patent number: 9792062
    Abstract: Technologies are generally described for systems, devices and methods effective to accelerate memory access. A memory unit, including a memory and a programmable circuit, may be in communication with a processor executing a virtual machine. The memory unit may receive from the processor, a request to configure the programmable circuit in accordance with a program. The program may be associated with the virtual machine. The programmable circuit may be configured in accordance with the program. The programmable circuit may then be operated to perform one or more operations on data in the memory.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: October 17, 2017
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Ezekiel Kruglick
  • Patent number: 9747036
    Abstract: Data is placed in tiered storage with a suitable granularity according to application characteristics. The storage apparatus comprises a controller for managing storage areas, provided by storage media of a plurality of types of varying performance, as pools, and for assigning the storage areas in page units to a virtual volume from any tiered storage among a plurality of types of tiered storage which the pool comprises in response to a data write request from the host computer, wherein, for specific data which is managed by the host computer, the controller specifies an area with a high referencing frequency among the specific data on the basis of organization information of the specific data, and moves this area to another of the tiered storage with a higher performance than an already assigned tiered storage.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: August 29, 2017
    Assignee: HITACHI, LTD.
    Inventors: Nobuhiro Maki, Yuri Hiraiwa, Kenichi Oyamada
  • Patent number: 9734048
    Abstract: A receiving unit receives an input of information of a performance level with respect to a volume that is allocated by using different types of disks. A target value calculating unit calculates, on the basis of a distribution ratio that is previously determined for each type of the disks, a target value of the performance of sending and receiving data to and from the volume. On the basis of the target value calculated by the target value calculating unit, a performance management unit determines a distribution ratio for each type of the disks allocated to the volume, determines a band distribution with respect to the volume, and instructs the storage device to re-allocate the volume by using the determined distribution ratio and adjust the bandwidth in accordance with the determined band distribution.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: August 15, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Toshiharu Makida
  • Patent number: 9720607
    Abstract: The disclosed embodiments relate to the design of an append-only data storage system that stores sets of data blocks in extents that are located in storage devices in the system. During operation of the system, when an extent is in an open state, the system allows data blocks to be appended to the extent, and disallows operations to be performed on the extent that are incompatible with data being concurrently appended to the extent. When the extent becomes full, the system changes the extent from the open state to a closed state. Then, while the extent is in the closed state, the system disallows data blocks to be appended to the extent, and allows operations to be performed on the extent that are incompatible with data being concurrently appended to the extent.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: August 1, 2017
    Assignee: Dropbox, Inc.
    Inventors: James Cowling, James Turner
  • Patent number: 9690823
    Abstract: A append-only data storage system that stores sets of data blocks in extents that are located in storage devices. When an extent becomes full, the system changes the extent from an open state, wherein data can be appended to the extent, to a closed state, wherein data cannot be appended to the extent. This change involves performing a synchronization operation by: obtaining a list of data blocks in the extent from each storage device that has a copy of the extent; forming a union of the lists; looking up data blocks from the union in a database that maps data blocks to storage devices and extents to determine which data blocks belong in the extent; and if a copy of the extent is missing data blocks that belong in the extent, performing a remedial action before changing the extent from the open state to the closed state.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: June 27, 2017
    Assignee: Dropbox, Inc.
    Inventors: James Cowling, James Turner
  • Patent number: 9582213
    Abstract: Embodiments described herein provide an object store that efficiently manages and services objects for use by clients of a distributed data processing system. Illustratively, the object store may be embodied as a quasi-shared storage system that interacts with nodes of the distributed data processing system to service the objects as blocks of data stored on a plurality of storage devices, such as disks, of the storage system. To that end, an architecture of the object store may include an on-disk layout, e.g., of the storage system, and an incore layout, e.g., of the nodes, that cooperate to illustratively convert the blocks to objects for access by the clients.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: February 28, 2017
    Assignee: NetApp, Inc.
    Inventors: Gaurav Makkar, Srinivasan Narayanamurthy, Kartheek Muthyala, Stephen Daniel
  • Patent number: 9582419
    Abstract: A data processing device 100 comprises a plurality of storage circuits 130, 160, which store a plurality of data elements of the bits in an interleaved manner. Data processing device also comprises a consumer 110 with a number of lanes 120. The consumer is able to individually access each of the plurality of storage circuits 130, 160 in order to receive into the lanes 120 either a subset of the plurality of data elements or y bits of each of the plurality of data elements. The consumer 110 is also able to execute a common instruction of each of the plurality of lanes 120. The relationship of the bits is such that b is greater than y and is an integer multiple of y. Each of the plurality of storage circuits 130, 160 stores at most y bits of each of the data elements. Furthermore, each of the storage circuits 130, 160 stores at most y/b of the plurality of data elements. By carrying out the interleaving in this manner, the plurality of storage circuits 130, 160 comprise no more than b/y storage circuits.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: February 28, 2017
    Assignee: ARM Limited
    Inventors: Ganesh Suryanarayan Dasika, Rune Holm, Stephen John Hill
  • Patent number: 9575886
    Abstract: Systems and methods for storing data to a non-volatile storage device are provided. A request to store data to the storage device at a given address corresponding to one of a plurality of regions of the storage device is received. A region classification map associated with the storage device associates a classification with each of the plurality of regions. A determination is made based on the region classification map as to which classification is associated with the one of the plurality of regions corresponding to the given address. The data is stored at the given address in response to determining that the one of the plurality of regions is associated with a first classification. The data is stored to an alternate location in response to determining that the one of the plurality of regions is associated with a second classification.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: February 21, 2017
    Assignee: Marvell World Trade Ltd.
    Inventor: Abhijeet P. Gole
  • Patent number: 9569365
    Abstract: A data processing system includes a plurality of transaction masters, each with an associated local cache memory and coupled to coherent interconnect circuitry. Monitoring circuitry within the coherent interconnect circuitry maintains a state variable (flag) in respect of each of the transaction masters to monitor whether an exclusive store access state is pending for that transaction master. When a transaction master is to execute a store-exclusive instruction, then a current value of the subject state variable for that transaction master is compared with a previous value of that variable stored when the exclusive store access was setup. If there is a match, then store-exclusive instruction is allowed to proceed and the state variables of all other transaction masters for which there is a pending exclusive store access state are changed. If there is not a match, then the execution of the store-exclusive instruction is marked as failing.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: February 14, 2017
    Assignee: ARM Limited
    Inventors: Stuart David Biles, Richard Roy Grisenthwaite, Bruce James Mathewson
  • Patent number: 9569370
    Abstract: Embodiments relate to a method, system and computer program product for storing a system-absolute address (SAA) in a first level look-aside buffer (TLB). In one embodiment, the system includes a central processor including the TLB and general purpose registers (GPRS). The TLB is configured for storing the SAA. The central processor is configured for issuing a load system-absolute address (LSAA) instruction. The system includes a translation unit that is in communication with the TLB of the central processor. The system is configured to perform a method including determining, based on the LSAA instruction being issued, whether the SAA is stored in the TLB. The method includes sending a translation request to the translation unit from the central processor based on the SAA not being stored in the TLB. The method includes determining the SAA by the translation unit based on receiving the translation request.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Khary J. Alexander, Jonathan T. Hsieh, Christian Jacobi, Timothy J. Slegel