Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; a first oxide layer disposed over the second metal layer; a second oxide layer disposed over the first oxide layer; and a second level including at least one array of memory cells and second transistors, where each of the memory cells includes at least one of the second transistors, where the second level overlays the first level, where at least one of the second transistors includes at least two independent gates, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

Abstract: A display substrate, a manufacturing method thereof, a display panel and a display device are provided. The display substrate includes: an array layer on a base substrate and a light shielding layer on a side of the array layer away from the base substrate, wherein the array layer includes a driving transistor and a switching transistor, the switching transistor is a transistor connected to a gate electrode of the driving transistor, a plurality of imaging pinholes are formed in the light shielding layer, and a first orthographic projection of the imaging pinholes onto the base substrate and a second orthographic projection of an active layer pattern of the switching transistor in the array layer onto the base substrate do not overlap at least in part.

Abstract: A semiconductor capacitor array layout generates parasitic capacitance toward an edge of the layout to reduce a capacitance difference between an outer capacitor unit and an inner capacitor unit. The semiconductor capacitor array layout includes a primary capacitor structure and an outer capacitor structure. Each of the primary capacitor structure and the outer capacitor structure includes a first crisscross structure and a second crisscross structure that are staggered. Each of the first crisscross structure and the second crisscross structure includes longitudinal conductive strips and lateral conductive strips, wherein the longitudinal conductive strips are disposed in a first integrated circuit (IC) layer and the lateral conductive strips are disposed in a second IC layer. The second crisscross structure of the primary capacitor structure and the first crisscross structure of the outer capacitor structure jointly generate the parasitic capacitance.

Abstract: A semiconductor structure can include: a semiconductor substrate having a first region, a second region, and an isolation region disposed between the first region and the second region; an isolation component located in the isolation region; and where the isolation component is configured to recombine first carriers flowing from the first region toward the second region, and to extract second carriers flowing from the second region toward the first region.

Abstract: A capacitor structure includes an insulation layer and a capacitor unit disposed on the insulation layer. The capacitor unit includes a first electrode, a second electrode, a first dielectric layer, and a patterned conductive layer. The second electrode is disposed above the first electrode in a vertical direction. The first dielectric layer is disposed between the first electrode and the second electrode in the vertical direction. The patterned conductive layer is disposed between first electrode and the second electrode, the patterned conductive layer is electrically connected with the first electrode, and the first dielectric layer surrounds the patterned conductive layer in a horizontal direction.

Abstract: An integrated fluxgate device includes a substrate that includes a dielectric layer. A fluxgate core is located over the dielectric layer. Lower windings are disposed in a lower metal level between the fluxgate core and the dielectric layer, and upper windings are disposed in an upper metal level above the fluxgate core. A metal structure in the upper metal level or the lower metal level overlaps an end of the fluxgate core and is conductively isolated from the upper and lower windings.

Abstract: A semiconductor storage device includes a substrate, a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate, a first semiconductor layer that extends in the first direction and faces the plurality of first conductive layers, a first gate insulating film that extends in the first direction and covers an outer peripheral surface of the first semiconductor layer, a first insulating layer that extends in the first direction and has an outer peripheral surface covered with the first semiconductor layer, and a second conductive layer that is farther from the substrate than the plurality of first conductive layers and is connected to one end in the first direction of the first semiconductor layer. The first semiconductor layer includes a first region facing the plurality of first conductive layers and a second region farther from the substrate than the first region.

Abstract: A radio frequency (RF) transistor amplifier includes a package submount. a package frame comprising an electrically insulating member and one or more conductive layers on the package submount and exposing a surface thereof, a transistor die on the surface of the package submount and comprising respective terminals that are electrically connected to the package frame, a protective member covering the transistor die, and one or more electrical components that are attached to the package frame outside the protective member. Related RF power device packages and fabrication methods are also discussed.

Abstract: A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level on top of or above the second metal layer; performing a lithography step on the second level; forming at least one third level on top of or above the second level; performing processing steps to form first memory cells within the second level and second memory cells within the third level, where the first memory cells include at least one second transistor, the second memory cells include at least one third transistor, second transistors comprise gate electrodes comprising metal, and then forming at least four independent memory arrays which include some first memory cells and/or second memory cells.

Abstract: A semiconductor device includes a doped substrate, a barrier layer, a channel layer, and a doped semiconductor structure. The barrier layer is disposed on the doped substrate. The channel layer is disposed between the doped substrate and the barrier layer, in which a bandgap of the barrier layer is greater than a bandgap of the channel layer. The doped semiconductor structure is embedded in the doped substrate and at a position lower than the channel layer, in which the doped substrate and the doped semiconductor structure have different polarities, so as to form a diode therebetween.

Abstract: A semiconductor device includes a doped substrate, a barrier layer, a channel layer, a doped semiconductor structure, and the conductive structure. The barrier layer is disposed on the doped substrate. The channel layer is disposed between the doped substrate and the barrier layer, in which a bandgap of the barrier layer is greater than a bandgap of the channel layer. The doped semiconductor structure is embedded in the doped substrate, in which the doped substrate and the doped semiconductor structure have different polarities, so as to form a diode therebetween. The conductive structure is disposed over the doped substrate and makes contact with the doped semiconductor structure, in which the conductive structure extends from the doped semiconductor structure to a position higher than the channel layer and the barrier layer.

Abstract: A semiconductor device includes: an insulated circuit substrate; a power semiconductor element mounted on the insulated circuit substrate; a first terminal having a plate-like shape having a first main surface and electrically connected to the power semiconductor element; a second terminal having a second main surface opposed to the first main surface of the first terminal and electrically connected to the power semiconductor element; an insulating sheet interposed between the first main surface and the second main surface; and a conductive film provided on at least one of the first main surface side and the second main surface side of the insulating sheet.

Abstract: A semiconductor device package includes a first and a second input lead and a plurality of uniform transistor-based components, the plurality of uniform transistor-based components comprising a first subset of the uniform transistor-based components coupled to the first input lead and a second subset of the uniform transistor-based components coupled to the second input lead. The first subset and the second subset are arranged in an asymmetric configuration with respect to one another.

Abstract: A semiconductor device includes several first cell row an several second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. A first row of the first cell rows is configured for a first cell to be arranged. The second cell rows extend in the first direction. Each of the second cell rows has a second row height that is different from the first row height. At least one row of the second cell rows includes a portion for at least one second cell to be arranged. The portion has a third row height that is different from the first row height and the second row height.

Abstract: An electronic device includes a carrier substrate having a front face. An electronic chip is mounted on the front face of the carrier substrate and includes an optical component. An encapsulation cover is mounted on top of the front face of the carrier substrate and bounds a chamber within which the chip is situated. A front opening extends through the cover and is situated in front of the optical component. An optical element, designed to allow light to pass, is mounted within the chamber at a position which covers the front opening of the encapsulation cover. The optical element includes a central region designed to deviate the light and having an optical axis aligned with the front opening and the optical component. A positioning pattern is provided on the optical element to assist with mounting the optical element to the cover and mounting the cover to the carrier substrate.

Abstract: An apparatus includes a substrate and a memory cell array disposed on the substrate. The apparatus also includes a logic cell disposed on the substrate in a peripheral region adjacent the memory cell array. The apparatus further includes a trench isolation region disposed in the substrate in the peripheral region. The trench isolation region either separates a first active area of the logic cell from a second active area of the logic cell or separates the logic cell from an adjacent logic cell. The logic cell includes a connection line that is buried within the trench isolation region. The connection line can be formed as an extension of a buried word line in the memory cell array region during a same fabrication process that forms the corresponding buried word line. By extending the buried word line into the peripheral region, the buried connection line can be formed without additional processing.

Abstract: A semiconductor device may include first channels on a first region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, second channels on a second region of the substrate and spaced apart from each other in the vertical direction, a first gate structure on the first region of the substrate and covering at least a portion of a surface of each of the first channels, and a second gate structure on the second region of the substrate and covering at least a portion of a surface of each of the second channels. The second channels may be disposed at heights substantially the same as those of corresponding ones of the first channels, and a height of a lowermost one of the second channels may be greater than a height of a lowermost one of the first channels.

Abstract: A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Access points for providing an etchant for removing the sacrificial material layers may be provided by memory openings, contact via cavities or backside trenches.

Abstract: A semiconductor storage device according to an embodiment includes: a stacked body in which a plurality of conductive layers are stacked via an insulating layer and which has a memory region in which a plurality of memory cells are disposed and a staircase region in which end portions of the plurality of conductive layers form a staircase shape. A first region of the staircase region includes a first sub-staircase portion ascending in a first direction toward the memory portion, and a second sub-staircase portion disposed side by side with the first sub-staircase portion in a second direction opposite to the first direction from the first sub-staircase portion and ascending in the second direction.