Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.

Abstract: An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N? drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.

Abstract: Circuit boards, LED lighting systems and methods of manufacture are described. A circuit board includes a ceramic carrier and a body on the ceramic carrier. The body includes dielectric layers and slots formed completely through a thickness of the dielectric layers. The slots are filled with a dielectric material. A conductive pad is provided on a surface of each of the slots opposite the ceramic carrier.

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The channel region is crystalline and comprises a plurality of vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. Other embodiments, including methods, are disclosed.

Abstract: A ceramic article. In some embodiments, the ceramic article includes a ceramic body composed of a ceramic material; and a first conductive trace, the first conductive trace having a first portion entirely within the ceramic material, the first portion having a length of 0.5 mm and transverse dimensions less than 500 microns, the ceramic material including a plurality of ceramic particles in a ceramic matrix.

Abstract: In one example, an electronic device includes: an electronic component comprising a sensor and an electrical interconnect; a substrate comprising an electrically conductive material and a translucent mold compound, wherein the electrically conductive material is coupled to the translucent mold compound and wherein the electrical interconnect of the electronic component is coupled to the electrically conductive material of the substrate; and a translucent underfill contacting the electrical interconnect and between the translucent mold compound and the sensor. Other examples and related methods are also disclosed herein.

Abstract: A method includes: abutting a first logic cell having a first cell height to a first memory cell having the first cell height; forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively; forming a plurality of first conductive rails between the first conductive rail and the second conductive rail; forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively; and forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail. An amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails.

Abstract: The invention relates to a vertical compound semiconductor structure having a substrate with a first main surface and an opposite second main surface, a vertical channel opening extending completely through the substrate between the first main surface and the second main surface and a layer stack arranged within the vertical channel opening. The layer stack includes an electrically conductive layer arranged within the vertical channel opening and a compound semiconductor layer arranged within the vertical channel opening. The compound semiconductor layer includes a compound semiconductor layer arranged on the electrically conductive layer and connected galvanically to the electrically conductive layer. Further, the invention relates to a method for producing such a vertical compound semiconductor structure.

Abstract: A transistor amplifier includes a semiconductor layer structure comprising first and second major surfaces and a plurality of unit cell transistors on the first major surface that are electrically connected in parallel, each unit cell transistor comprising a gate finger coupled to a gate manifold, a drain finger coupled to a drain manifold, and a source finger. The semiconductor layer structure is free of a via to the source fingers on the second major surface.

Abstract: A semiconductor device includes an active region over a substrate extending along a first lateral direction. The semiconductor device includes a number of first conductive structures operatively coupled to the active region. The first conductive structures extend along a second lateral direction. The semiconductor device includes a number of second conductive structures disposed above the plurality of first conductive structures. The second conductive structures extend along the first lateral direction. The semiconductor device includes a first capacitor having a first electrode and a second electrode. The first electrode includes one of the first conductive structures and the active region, and the second electrode includes a first one of the second conductive structures. Each of the active region and the first conductive structures is electrically coupled to a power rail structure configured to carry a supply voltage.

Abstract: A stacked staggered electrode capacitor in semiconductor devices and methods for fabrication. There are capacitor elements each with a cathode vertically disposed relative to an anode, an anode conductive plating on the anode and a cathode conductive plating on the anode. The anode conductive plating is in a laterally offset relationship to the cathode conductive plating. The plurality of capacitor elements are stacked onto another. One or more build-up layers are interposed between the capacitor elements. One or more anode connecting electrode segments are on a first side of the plurality of capacitor elements, and a cathode connecting electrode on an opposed second side of the plurality of capacitor elements is connected to the cathode conductive plating of each of the plurality of capacitor elements.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; a first oxide layer disposed over the second metal layer; a second oxide layer disposed over the first oxide layer; and a second level including at least one array of memory cells and second transistors, where each of the memory cells includes at least one of the second transistors, where the second level overlays the first level, where at least one of the second transistors includes at least two independent gates, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

Abstract: A semiconductor capacitor array layout generates parasitic capacitance toward an edge of the layout to reduce a capacitance difference between an outer capacitor unit and an inner capacitor unit. The semiconductor capacitor array layout includes a primary capacitor structure and an outer capacitor structure. Each of the primary capacitor structure and the outer capacitor structure includes a first crisscross structure and a second crisscross structure that are staggered. Each of the first crisscross structure and the second crisscross structure includes longitudinal conductive strips and lateral conductive strips, wherein the longitudinal conductive strips are disposed in a first integrated circuit (IC) layer and the lateral conductive strips are disposed in a second IC layer. The second crisscross structure of the primary capacitor structure and the first crisscross structure of the outer capacitor structure jointly generate the parasitic capacitance.

Abstract: A display substrate, a manufacturing method thereof, a display panel and a display device are provided. The display substrate includes: an array layer on a base substrate and a light shielding layer on a side of the array layer away from the base substrate, wherein the array layer includes a driving transistor and a switching transistor, the switching transistor is a transistor connected to a gate electrode of the driving transistor, a plurality of imaging pinholes are formed in the light shielding layer, and a first orthographic projection of the imaging pinholes onto the base substrate and a second orthographic projection of an active layer pattern of the switching transistor in the array layer onto the base substrate do not overlap at least in part.

Abstract: A semiconductor structure can include: a semiconductor substrate having a first region, a second region, and an isolation region disposed between the first region and the second region; an isolation component located in the isolation region; and where the isolation component is configured to recombine first carriers flowing from the first region toward the second region, and to extract second carriers flowing from the second region toward the first region.

Abstract: A capacitor structure includes an insulation layer and a capacitor unit disposed on the insulation layer. The capacitor unit includes a first electrode, a second electrode, a first dielectric layer, and a patterned conductive layer. The second electrode is disposed above the first electrode in a vertical direction. The first dielectric layer is disposed between the first electrode and the second electrode in the vertical direction. The patterned conductive layer is disposed between first electrode and the second electrode, the patterned conductive layer is electrically connected with the first electrode, and the first dielectric layer surrounds the patterned conductive layer in a horizontal direction.

Abstract: An integrated fluxgate device includes a substrate that includes a dielectric layer. A fluxgate core is located over the dielectric layer. Lower windings are disposed in a lower metal level between the fluxgate core and the dielectric layer, and upper windings are disposed in an upper metal level above the fluxgate core. A metal structure in the upper metal level or the lower metal level overlaps an end of the fluxgate core and is conductively isolated from the upper and lower windings.

Abstract: A semiconductor storage device includes a substrate, a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate, a first semiconductor layer that extends in the first direction and faces the plurality of first conductive layers, a first gate insulating film that extends in the first direction and covers an outer peripheral surface of the first semiconductor layer, a first insulating layer that extends in the first direction and has an outer peripheral surface covered with the first semiconductor layer, and a second conductive layer that is farther from the substrate than the plurality of first conductive layers and is connected to one end in the first direction of the first semiconductor layer. The first semiconductor layer includes a first region facing the plurality of first conductive layers and a second region farther from the substrate than the first region.

Abstract: A radio frequency (RF) transistor amplifier includes a package submount. a package frame comprising an electrically insulating member and one or more conductive layers on the package submount and exposing a surface thereof, a transistor die on the surface of the package submount and comprising respective terminals that are electrically connected to the package frame, a protective member covering the transistor die, and one or more electrical components that are attached to the package frame outside the protective member. Related RF power device packages and fabrication methods are also discussed.