Abstract: A display panel and a display apparatus. The display panel includes first and second display areas. The first display area includes a transparent display area and a transition display area. The display panel includes a device layer and a light-emitting element layer. The light-emitting element layer includes a first pixel structure arranged in the first display area. The first pixel structure includes a plurality of first sub-pixels, and the first sub-pixels include first electrodes. The device layer includes first driving transistors, and the first driving transistors include first gate electrodes. In a stacking direction the light-emitting element layer stacked with the device layer, an orthographic projection of a first gate electrode of one first driving transistor does not overlap with an orthographic projection of a first electrode of a first sub-pixel emitting a color different from another first sub-pixel driven by that first driving transistor.

Abstract: Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.

Abstract: A chips bonding auxiliary structure includes a first chip, an auxiliary pattern and a second chip. The first chip has a first surface. The auxiliary pattern is form on the first surface. The second chip has a second surface bonding to the first surface to form at least one gap space surrounding the auxiliary pattern.

Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate, and first and second epitaxial layers wrapping around the first and second semiconductor fins, respectively. The semiconductor device further includes a contact plug over the first epitaxial layer and the second epitaxial layer. The contact plug includes a first interfacial layer over the first epitaxial layer and a second interfacial layer over the second epitaxial layer. The first and second interfacial layers include a noble metal element and a Group IV element.

Abstract: An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N? drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.

Abstract: A semiconductor structure is provided. The semiconductor structure includes an interconnection structure, a first transistor, and a second transistor. The interconnection structure includes a first metal line layer, a second metal line layer and a third metal line layer arranged over one another. The first transistor includes a gate structure. The second transistor is disposed adjacent to the first transistor, and includes a source/drain structure. The gate structure of the first transistor is disposed over and electrically connected to the first metal line layer, and the source/drain structure of the second transistor is arranged below and electrically connected to the second metal line layer through the third metal line layer. A manufacturing method of a semiconductor structure is also provided.

Abstract: A memory cell including a set of active regions that overlay a set of gate regions to form a pair of cross-coupled inverters. A first active region extends along a first axis. A first gate region extends transversely to the first active region and overlays the first active region to form a first transistor of the pair of cross-coupled inverters. A second gate region extends transversely to the first active region and overlays the first active region to form a second transistor of the pair of cross-coupled inverters. A second active region extends along a second axis and overlays the first gate region to form a third transistor of the pair of cross-coupled inverters. A fourth active region extending along a third axis and overlays a gate region to form a transistor of a read port.

Abstract: Provided is a substrate structure including a substrate, a buffer layer disposed on the substrate, a porous semiconductor layer disposed on the buffer layer, the porous semiconductor layer having a plurality of voids, a plurality of semiconductor light emitting structures disposed on the porous semiconductor layer, the plurality of semiconductor light emitting structures having a nanorod shape extending vertically, and a passivation film disposed on a side wall of each of the plurality of semiconductor light emitting structures, the passivation film having an insulation property.

Abstract: A semiconductor device with an active transistor cell comprising a p-type first and second base layers, surrounding an n-type source region, the device further comprising a plurality of first gate electrodes embedded in trench recesses, has additional gate runners formed adjacent to the first base layer, outside the active cell, and contacting the first gate electrodes at the cross points thereof. The additional gate runners do not affect the active cell design in terms of cell pitch i.e., the design rules for cell spacing, hole drainage between the cells, or gate-collector capacitance, hence resulting in optimum low conduction and switching losses. The transistor cell and layout designs offer a range of advantages both in terms of performance and manufacturability, with the potential of applying additional layers or structures.

Abstract: A ferroelectric device structure includes an array of ferroelectric capacitors overlying a substrate, first metal interconnect structures electrically connecting each of first electrodes of the array of ferroelectric capacitors to a first metal pad embedded in a dielectric material layer, and second metal interconnect structures electrically connecting each of the second electrodes of the array of ferroelectric capacitors to a second metal pad embedded in the dielectric material layer. The second metal pad may be vertically spaced from the substrate by a same vertical separation distance as the first metal pad is from the substrate. First metal lines laterally extending along a first horizontal direction may electrically connect the first electrodes to the first metal pad, and second metal lines laterally extending along the first horizontal direction may electrically connect each of the second electrodes to the second metal pad.

Abstract: A method includes forming a first semiconductor device, wherein the first semiconductor device includes a top surface and a bottom surface, and wherein the first semiconductor device includes a metal layer having an exposed first surface. The method also includes forming a Electromagnetic Interference (EMI) layer over the top surface and sidewalls of the first semiconductor device, wherein the EMI layer electrically contacts the exposed first surface of the metal layer. The method also includes forming a molding compound over the EMI layer.

Abstract: Disclosed are a display panel and a display device. The display panel includes: a base substrate; a detection circuit, located on the side of the base substrate, and including a transistor and a photosensitive detection component electrically connected to the transistor, and an orthographic projection of the transistor on the base substrate and an orthographic projection of the photosensitive detection component on the base substrate do not overlap with each other; a planarization layer, located on the side of the detection circuit facing away from the base substrate, and including a first surface facing away from the base substrate at the position in which the transistor is located, and a second surface facing away from the base substrate at the position in which the photosensitive detection component is located; and a light-emitting device, located on the side of the planarization layer away from the detection circuit.

Abstract: Devices and methods to manufacture a stack of FET switches in presence of a neighboring stack of FET switches are described. The stack of FET switches is designed or manufactured so that at least its top FET has a width that is smaller than the width of its bottom FET. Other voltage handling configurations and distributions of widths are described.

Abstract: Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.

Abstract: A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.

Abstract: A fan-out package includes a redistribution structure having redistribution-side bonding structures, a plurality of semiconductor dies including a respective set of die-side bonding structures that is attached to a respective subset of the redistribution-side bonding structures through a respective set of solder material portions, and an underfill material portion laterally surrounding the redistribution-side bonding structures and the die-side bonding structures of the plurality of semiconductor dies. A subset of the redistribution-side bonding structures is not bonded to any of the die-side bonding structures of the plurality of semiconductor dies and is laterally surrounded by the underfill material portion, and is used to provide uniform distribution of the underfill material during formation of the underfill material portion.

Abstract: An electrical distribution grid energy management and router device, or GER device, may be installed in a distribution grid, and route power from power supply to one or more power consumers. The GER devices described herein may provide platforms to add one or more features to a distribution transformer, provide additional features and benefits to both the utility company and end consumer, and may serve as a platform for providing other features, such as multi-layer protection systems for detecting, among other things, one or more fault conditions, and responding to such conditions when detected. A GER device may include sensors to measure electrical properties of incoming and outgoing power, and may include an electrical circuit layer having a central DC power stage.

Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: A method for manufacturing micro-LED displays includes depositing a first material over a substrate having a plurality of micro-LEDs such that the plurality of micro-LEDs are covered by the first material and the first material fills gaps laterally separating the micro-LEDs, removing a portion of the first material from the gaps that laterally separate the plurality of micro-LEDs to form trenches that extend to or below light-emitting layers of the micro-LEDs, depositing a second material over the substrate such that the second material covers the first material and extends into the trenches, and removing a portion of the first and second material over the plurality of micro-LEDs to expose top surfaces of the plurality of micro-LEDs and such that isolation walls positioned in the gaps between the plurality of micro-LEDs extend vertically higher than the top surface of the first material.

Abstract: A semiconductor device includes a substrate having a first active region disposed in a first region of a substrate and a second active region disposed in a second region of the substrate. A first gate stack is disposed over the first active region and a second gate stack is disposed over the second active region, the first and second gate stacks having elongated shapes oriented in a first direction. A first metal layer is disposed over the first gate stack and the second gate stack. The first metal layer includes first metal layer structures oriented in a second direction orthogonal to the first direction. A second metal layer disposed over the first metal layer. The second metal layer includes second metal layer structures oriented in the first direction. A third metal layer is disposed over the second metal layer. The third metal layer includes a third metal layer structures oriented in the second direction.