Patents Examined by Duy T Nguyen
  • Patent number: 11990399
    Abstract: An electronic device includes a substrate having a surface, functional metallic traces on a first portion of the surface that are electrically connected to carry current in the electronic device and have a first density, and dummy metallic traces on a second portion of the surface that are electrically isolated from the functional metallic traces and have a second density that is within at least 50% of the first density.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: May 21, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Frank Armstrong
  • Patent number: 11990519
    Abstract: An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N? drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: May 21, 2024
    Assignee: GENESIC SEMICONDUCTOR INC.
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Patent number: 11984516
    Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: May 14, 2024
    Assignee: TONG HSING ELECTRONIC INDUSTRIES, LTD.
    Inventors: Fu-Chou Liu, Jui-Hung Hsu, Yu-Chiang Peng, Chien-Chen Lee, Ya-Han Chang, Li-Chun Hung
  • Patent number: 11984321
    Abstract: A method for the etching of deep, high-aspect ratio features into silicon carbide (SiC), gallium nitride (GaN) and similar materials using an Inductively-Coupled Plasma (ICP) etch process technology is described. This technology can also be used to etch features in silicon carbide and gallium nitride having near vertical sidewalls. The disclosed method has application in the fabrication of electronics, microelectronics, power electronics, Monolithic Microwave Integrated Circuits (MMICs), high-voltage electronics, high-temperature electronics, high-power electronics, Light-Emitting Diodes (LEDs), Micro-Electro-Mechanical Systems (MEMS), micro-mechanical devices, microelectronic devices and systems, nanotechnology devices and systems, Nano-Electro-Mechanical Systems (NEMS), photonic devices, and any devices and/or structures made from silicon carbide and/or gallium nitride.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: May 14, 2024
    Assignee: Corporation for National Research Initiatives
    Inventors: Mehmet Ozgur, Michael Pedersen, Michael A. Huff
  • Patent number: 11984446
    Abstract: A semiconductor device may include a first capacitor and a second capacitor. The first capacitor may include a first lower electrode, a first upper electrode and a first dielectric layer disposed between the first lower electrode and the first upper electrode at a first height. The second capacitor may be positioned spaced apart from the first capacitor. The second capacitor may include a second lower electrode, a second upper electrode and a second dielectric layer disposed between the second lower electrode and the second upper electrode at a second height different from the first height.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: May 14, 2024
    Assignee: SK hynix Inc.
    Inventors: Kyu Jin Choi, Seong Min Ma, Kyu Chan Shim
  • Patent number: 11978822
    Abstract: A method of manufacturing a light-emitting device 1 includes a step of providing first phosphor sheets 11, a step of providing second phosphor sheets 12, a step of providing a light-emitting element 13, a selection step of selecting a combination of one of the first phosphor sheets 11 and one of the second phosphor sheets 12 on the basis of a wavelength conversion characteristic of each of the first phosphor sheets 11 and a wavelength conversion characteristic of each of the second phosphor sheets 12, a step of obtaining a plurality of first phosphor pieces 11c and a plurality of second phosphor pieces 12c from the selected first phosphor sheet 11 and the selected second phosphor sheet 12, and a step of disposing one of the first phosphor pieces 11c and one of the second phosphor pieces 12c on or above the light-emitting element 13.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: May 7, 2024
    Assignee: NICHIA CORPORATION
    Inventor: Suguru Beppu
  • Patent number: 11973117
    Abstract: Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsien Huang, Chang-Ting Chung, Wei-Cheng Lin, Wei-Jung Lin, Chih-Wei Chang
  • Patent number: 11967652
    Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: April 23, 2024
    Assignee: TONG HSING ELECTRONIC INDUSTRIES, LTD.
    Inventors: Fu-Chou Liu, Jui-Hung Hsu, Yu-Chiang Peng, Chien-Chen Lee, Ya-Han Chang, Li-Chun Hung
  • Patent number: 11967544
    Abstract: In providing electrical wire-like connections between at least one semiconductor die arranged on a semiconductor die mounting area of a substrate and an array of electrically-conductive leads in the substrate, pressure force is applied to the electrically-conductive leads in the substrate during bonding the wire-like connections to the electrically-conductive leads. Such a pressure force is applied to the electrically-conductive leads in the substrate via a pair of mutually co-operating force transmitting surfaces. These surfaces include a first convex surface engaging a second concave surface.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: April 23, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mauro Mazzola, Matteo De Santa
  • Patent number: 11957013
    Abstract: A display panel includes: a silicon-based substrate, a driving layer, a first electrode layer, an organic light emitting layer, a second electrode layer and a plurality of pads. The display signal access pad is configured to access the display signal during a display phase, the test signal access pad at least includes a first group of test phase access pads, and the first group of test phase access pads includes a first pad and a second pad, the first pad is electrically connected with the electrode ring, and the second pad is electrically connected with the silicon-based substrate.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: April 9, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhijian Zhu, Pengcheng Lu, Yu Ao, Yunlong Li, Yuanlan Tian
  • Patent number: 11942389
    Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: March 26, 2024
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 11942484
    Abstract: A semiconductor device includes an insulating substrate, a first semiconductor layer formed of silicon and positioned above the insulating substrate, a second semiconductor layer formed of a metal oxide and positioned above the first semiconductor layer, a first insulating film formed of a silicon nitride and positioned between the first semiconductor layer and the second semiconductor layer, and a block layer positioned between the first semiconductor film and the second semiconductor layer, the block layer hydrogen diffusion of which is lower than that of the first insulating film.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 26, 2024
    Assignee: Japan Display Inc.
    Inventors: Akihiro Hanada, Hajime Watakabe, Kazufumi Watabe
  • Patent number: 11943987
    Abstract: A color conversion substrate and a display device are provided. The color conversion substrate includes a base substrate, a first color filter and a second color filter disposed on a surface of the base substrate, a first partition layer disposed between the first color filter and the second color filter, a second partition layer disposed on the first partition layer, a first wavelength conversion pattern disposed on the first color filter and a second wavelength conversion pattern disposed on the second color filter, wherein the first partition layer includes a first lower surface disposed on the first color filter and a second lower surface disposed on the second color filter.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: March 26, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Gak Seok Lee, Byung Chul Kim, In Ok Kim, Jae Min Seong, In Seok Song, Keun Chan Oh, Ji Eun Jang, Chang Soon Jang, Sun Kyu Joo, Ha Lim Ji
  • Patent number: 11942466
    Abstract: According to one embodiment, a memory device includes: a first chip including a first insulating layer and a first pad; a plurality of memory units provided in a first area of the first insulating layer and arranged at first intervals in a first direction parallel to a surface of the first chip; a plurality of mark portions provided in a second area of the first insulating layer and arranged at second intervals in the first direction; a second chip including a second pad connected to the first pad and overlapping the first chip in a second direction perpendicular to the surface of the first chip; and a circuit provided in the second chip.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: March 26, 2024
    Assignee: Kioxia Corporation
    Inventor: Mutsumi Okajima
  • Patent number: 11935929
    Abstract: A stacked device is provided. The stacked device includes a reduced height active device layer, and a plurality of lower source/drain regions in the reduced height active device layer. The stacked device further includes a lower interlayer dielectric (ILD) layer on the plurality of lower source/drain regions, and a conductive trench spacer in the lower interlayer dielectric (ILD) layer, wherein the conductive trench spacer is adjacent to one of the plurality of lower source/drain regions. The stacked device further includes a top active device layer adjacent to the lower interlayer dielectric (ILD) layer, and an upper source/drain section in the top active device layer. The stacked device further includes a shared contact in electrical connection with the upper source/drain section, the conductive trench spacer, and the one of the plurality of lower source/drain regions.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: March 19, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Julien Frougier, Su Chen Fan, Ravikumar Ramachandran, Nicolas Loubet
  • Patent number: 11923287
    Abstract: A semiconductor device includes an insulating layer, a conductive member provided inside the insulating layer, a chip disposed on a first surface of the insulating layer and connected to the conductive member, and an electrode connected to the conductive member via a barrier layer. A resistivity of the barrier layer is higher than a resistivity of the conductive member. At least a portion of the electrode protrudes from a second surface of the insulating layer.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: March 5, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, Kioxia Corporation
    Inventors: Takayuki Tajima, Kazuo Shimokawa
  • Patent number: 11923380
    Abstract: A display panel and a manufacturing method thereof are provided. The display panel includes a base substrate, a first active layer, a first gate insulating layer, a first gate layer, and a second gate insulating layer stacked in sequence on the base substrate, and a metal layer, a first interlayer dielectric layer, a first source, and a first drain. A first metal portion and a second metal portion of the metal layer are respectively filled in a first through hole and a second through hole of the second gate insulating layer and are electrically connected to the first active layer.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: March 5, 2024
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Jiaqing He, Jixiang Gong, Hao Peng
  • Patent number: 11916067
    Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee
  • Patent number: 11915986
    Abstract: A described example includes: a ceramic package having a board side surface and an opposite top side surface; a heat slug mounted to the board side surface of the ceramic package, forming a bottom surface in a die cavity; leads mounted to conductive lands on the ceramic package; sidewall metallization extending from the conductive lands and covering a portion of one of the sides of the ceramic package; copper tungsten alloy conductor layers formed in the ceramic package and spaced by dielectric layers; bond fingers formed of a conductor layer and extending to the die cavity; a semiconductor device mounted over the heat slug, and having bond pads on a device side surface facing away from a surface of the heat slug; electrical connections between bond pads on the semiconductor device and the bond fingers; and a lid mounted to the top side surface of the ceramic package.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ramlah Binte Abdul Razak, Hector Torres
  • Patent number: 11916006
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Kaladhar Radhakrishnan, Krishna Bharath, Shawna M. Liff, Johanna M. Swan