Abstract: An image sensing device may include a photoelectric conversion region structured to convert incident light into photocharge, a first transmission gate structured to transfer the photocharge generated by the photoelectric conversion region to a first floating diffusion region structured to store the photocharge, and a second transmission gate structured to transfer the photocharge transferred to the first floating diffusion region to a second floating diffusion region structured to store the photocharge for readout, wherein a first side surface of the second transmission gate abuts on a side surface of the first transmission gate, the first floating diffusion region abuts on a bottom surface of the second transmission gate and the side surface of the first transmission gate, and the second floating diffusion region abuts on a second side surface of the second transmission gate facing away from the first side surface of the second transmission gate.

Abstract: An integrated circuit is provided and includes first transistors of a first circuit arranged in a first cell row having a first number of fin structures and a second transistor of a second circuit. The second transistor is coupled in parallel with a first element in the first transistors between first and second terminals of the first circuit, and arranged in a second cell row having a second number, different from the first number, of fin structures. The first element and the second transistor share a first gate extending in a first direction to pass through the first and second cell rows in a layout view. The second transistor is a duplication of the first element.

Abstract: A system and method for mitigating flux trapping in a superconducting integrated circuit. A first metal layer is formed having a first critical temperature and a first device, and a flux directing layer is formed having a second critical temperature. The flux directing layer is positioned in communication with an aperture location, and the aperture location is spaced from the first device to isolate the first device from flux trapped in the aperture. The superconducting integrated circuit is cooled from a first temperature that is above both the first and second critical temperatures to a second temperature that is less than both the first and second critical temperatures by a cryogenic refrigerator. A relative temperature difference between the first and second critical temperatures causes the flux directing layer to direct flux away from the first device and trap flux at the aperture location.

Abstract: An OLED display panel, a preparation method therefor, and a display apparatus. The display panel includes a display area including a first sub-pixel, a second sub-pixel and a third sub-pixel displaying different colors; the display area includes a first electrode layer, a pixel defining layer, an organic functional layer and a second electrode layer sequentially arranged on a substrate; the organic functional layer includes a first light-emitting layer in the first sub-pixel, a second light-emitting layer in the second sub-pixel, and a third light-emitting layer covering the display area and having an integrated structure; the orthographic projection, on the substrate, of each of the first light-emitting layer and the second light-emitting layer includes the orthographic projection of an opening on the substrate, which defines a corresponding sub-pixel, of the pixel defining layer and does not overlap with orthographic projections of remaining openings of the pixel defining layer on the substrate.

Abstract: A lithium niobate semiconductor structure includes: a first lithium niobate material layer, a second lithium niobate material layer and a third lithium niobate material layer. A polarization direction of a ferroelectric domain of the first lithium niobate material layer is a first direction. The second lithium niobate material layer is spaced apart from the first lithium niobate material layer, and a polarization direction of a ferroelectric domain of the second lithium niobate material layer is the first direction. The third lithium niobate material layer is sandwiched between the first lithium niobate material layer and the second lithium niobate material layer, and a polarization direction of a ferroelectric domain of the third lithium niobate material layer is a second direction; the first direction is opposite to the second direction.

Abstract: An exemplary method includes forming a multilayer interlevel dielectric (ILD) layer having a metal-containing dielectric layer (e.g., an aluminum oxide layer) between a first dielectric layer and a second dielectric layer and forming a bottom electrode via in the multilayer ILD layer. The method further includes forming a bottom electrode layer over the bottom electrode via, magnetic tunnel junction (MTJ) layers over the bottom electrode layer, and a top electrode layer over the MTJ layers. The bottom electrode layer, the MTJ layers, and the top electrode layer are etched to form a bottom electrode, an MTJ element, and a top electrode, respectively, of a magnetoresistive random-access memory (MRAM). The etching, such as an ion beam etch, forms a recess in the multilayer ILD layer that extends to the metal-containing dielectric layer of the multilayer ILD layer. In some embodiments, the etching extends the recess into and/or through the metal-containing dielectric layer.

Abstract: A semiconductor memory device including an array region and a peripheral region surrounding the array region. The array region includes a plurality of active regions and a first insulating layer disposed between the active regions. The peripheral region includes a peripheral structure, a second insulating layer surrounding the peripheral structure, and a third insulating layer surrounding the second insulating layer. At least a buried word line extends through the array region and the peripheral region, wherein a portion of the buried word line through the second insulating layer comprises a neck profile from a plan view.

Abstract: Methods, systems, and apparatus, including an integrated circuit (IC) with a ring-shaped hot spot area. In one aspect, an IC includes a first area along an outside perimeter of a surface of the IC. The first area defines a first inner perimeter. The IC includes a second area that includes a center of the IC and that includes a first set of components. The second area defines a first outer. The IC includes a ring-shaped hot spot area between the first area and the second area. The ring-shaped hot spot area defines a ring outer perimeter that is juxtaposed with the first inner perimeter. The ring-shaped hot spot area defines a ring inner perimeter that is juxtaposed with the first outer perimeter. The ring-shaped hot spot area includes a second set of components that produce more heat than the first set of components.

Abstract: A process for protecting an upper stage of an electronic components against antenna effects includes providing a first structure having a first substrate with a first surface, a first stage of electronic components formed in a second surface of the first substrate, and a first stack having a last metallization level electrically connected to the second surface; and providing a second structure having a second substrate with a through-substrate via and having a second stage of electronic components having protective components that are arranged to drain electric charges to the second substrate. The process also includes joining the first and second structures so that the through-substrate via is electrically connected to the last metallization level of the first stack and forming a second stack on the second stage having a first metallization level electrically connected to the through-substrate via and to the first surface of the second substrate.

Abstract: In a semiconductor device, a semiconductor element has a front electrode and a back electrode. The back electrode is connected to a wiring member through a bonding member. Wire pieces are disposed in the bonding member, and bonded to a bonding surface of the wiring member to protrude toward the semiconductor element. The bonding member has, in a plan view, a central region that overlaps with a central portion of the semiconductor element including an element center, and an outer peripheral region that includes a portion overlapping with an outer peripheral portion of the semiconductor element surrounding the central portion and surrounds the central region. At least four wire pieces are disposed in the outer peripheral region at positions corresponding to at least four respective corners of the semiconductor element. At least one wire piece is disposed to extend toward the element center in the plan view.

Abstract: A method of making flexible and stretchable semiconductor devices with reduced footprints can include coating a gate electrode layer having a first composition over an elastomer layer, solidifying a portion of the gate electrode layer by irradiation to form a gate electrode, coating a dielectric layer having a second composition over the gate electrode layer, solidifying a portion of the dielectric layer by the irradiation to form a gate dielectric, coating a semiconductor layer having a third composition over the dielectric layer, solidifying a portion of the semiconductor layer by the irradiation to form a device core, coating a terminal layer having the first composition over the dielectric layer, and solidifying a portion of the terminal layer by the irradiation to form a source electrode and a drain electrode contacting the semiconductor layer.

Abstract: A display device includes a substrate, a first light-emitting diode (LED) element and a second LED element provided to the substrate and configured to output light, a first signal line provided between the first LED element and the second LED element and electrically coupled to the first LED element, a second signal line provided between the first LED element and the second LED element and electrically coupled to the second LED element, gate wiring intersecting the first signal line and the second signal line, and anode wiring overlapping the gate wiring and electrically coupled to the first LED element and the second LED element. The anode wiring extends parallel to the gate wiring.

Abstract: A display panel and a display apparatus. The display panel includes first and second display areas. The first display area includes a transparent display area and a transition display area. The display panel includes a device layer and a light-emitting element layer. The light-emitting element layer includes a first pixel structure arranged in the first display area. The first pixel structure includes a plurality of first sub-pixels, and the first sub-pixels include first electrodes. The device layer includes first driving transistors, and the first driving transistors include first gate electrodes. In a stacking direction the light-emitting element layer stacked with the device layer, an orthographic projection of a first gate electrode of one first driving transistor does not overlap with an orthographic projection of a first electrode of a first sub-pixel emitting a color different from another first sub-pixel driven by that first driving transistor.

Abstract: Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.

Abstract: An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N? drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.

Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate, and first and second epitaxial layers wrapping around the first and second semiconductor fins, respectively. The semiconductor device further includes a contact plug over the first epitaxial layer and the second epitaxial layer. The contact plug includes a first interfacial layer over the first epitaxial layer and a second interfacial layer over the second epitaxial layer. The first and second interfacial layers include a noble metal element and a Group IV element.

Abstract: A chips bonding auxiliary structure includes a first chip, an auxiliary pattern and a second chip. The first chip has a first surface. The auxiliary pattern is form on the first surface. The second chip has a second surface bonding to the first surface to form at least one gap space surrounding the auxiliary pattern.

Abstract: Provided is a substrate structure including a substrate, a buffer layer disposed on the substrate, a porous semiconductor layer disposed on the buffer layer, the porous semiconductor layer having a plurality of voids, a plurality of semiconductor light emitting structures disposed on the porous semiconductor layer, the plurality of semiconductor light emitting structures having a nanorod shape extending vertically, and a passivation film disposed on a side wall of each of the plurality of semiconductor light emitting structures, the passivation film having an insulation property.

Abstract: A semiconductor structure is provided. The semiconductor structure includes an interconnection structure, a first transistor, and a second transistor. The interconnection structure includes a first metal line layer, a second metal line layer and a third metal line layer arranged over one another. The first transistor includes a gate structure. The second transistor is disposed adjacent to the first transistor, and includes a source/drain structure. The gate structure of the first transistor is disposed over and electrically connected to the first metal line layer, and the source/drain structure of the second transistor is arranged below and electrically connected to the second metal line layer through the third metal line layer. A manufacturing method of a semiconductor structure is also provided.

Abstract: A memory cell including a set of active regions that overlay a set of gate regions to form a pair of cross-coupled inverters. A first active region extends along a first axis. A first gate region extends transversely to the first active region and overlays the first active region to form a first transistor of the pair of cross-coupled inverters. A second gate region extends transversely to the first active region and overlays the first active region to form a second transistor of the pair of cross-coupled inverters. A second active region extends along a second axis and overlays the first gate region to form a third transistor of the pair of cross-coupled inverters. A fourth active region extending along a third axis and overlays a gate region to form a transistor of a read port.