Patents Examined by Duy T Nguyen
  • Patent number: 11658133
    Abstract: An integrated circuit device is disclosed, the device comprising a protective layer and a protected circuit on a substrate, the protective layer being configured to protect the protected circuit by absorbing laser radiation targeted at the protected circuit through the substrate. The device may be configured such that removal of the protective layer causes physical damage that disables the protected circuit. The device may comprise intermediate circuitry protruding into the substrate between the protective layer and the protected circuit, wherein the physical damage that disables the protected circuit is physical damage to the intermediate circuitry. The device may comprise detection circuitry configured to detect a change in an electrical property of the device indicative of removal of the protective layer, and, in response to detecting the change in the electrical property, cause the protected circuit to be disabled.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: May 23, 2023
    Assignee: Nagravision SA
    Inventors: Stephane Jullian, Pascal Aubry
  • Patent number: 11658206
    Abstract: A deep trench structure may be formed between electrodes of a capacitive device. The deep trench structure may be formed to a depth, a width, and/or an aspect ratio that increases the volume of the deep trench structure relative to a trench structure formed using a metal etch-stop layer. Thus, the deep trench structure is capable of being filled with a greater amount of dielectric material, which increases the capacitance value of the capacitive device. Moreover, the parasitic capacitance of the capacitive device may be decreased by omitting the metal etch-stop layer. Accordingly, the deep trench structure (and the omission of the metal etch-stop layer) may increase the sensitivity of the capacitive device, may increase the humidity-sensing performance of the capacitive device, and/or may increase the performance of devices and/or integrated circuits in which the capacitive device is included.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: May 23, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: En-Shuo Lin, Sheng Ko, Chi-Fu Lin, Che-Yi Lin, Clark Lee
  • Patent number: 11658250
    Abstract: High-density metal-oxide semiconductor (MOS) capacitor (MOSCAP) cell circuits and MOS device array circuits are disclosed. A gate comprising a selected aspect ratio disposed in a MOSCAP cell circuit comprising a cell region is configured to increase a capacitive density by increasing an extent to which metal routing layers contribute to a total MOSCAP cell circuit capacitance. An area of a MOSCAP array circuit is also reduced. Also, bulk tie cells are disposed within a MOS device array circuit in array diffusion regions to increased MOS device array circuit density. The array diffusion regions include a first device region including MOS devices and a bulk tie region including the bulk tie cells. The bulk tie region is isolated from the first device region by a diffusion cut. A diffusion cut is between a first gate on the device region and a second gate on the bulk tie region.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: May 23, 2023
    Assignee: QUALCOMM Incorporated
    Inventor: Bed Raj Kandel
  • Patent number: 11652365
    Abstract: An electrical distribution grid energy management and router device, or GER device, may be installed in a distribution grid, and route power from power supply to one or more power consumers. The GER devices described herein may provide platforms to add one or more features to a distribution transformer, provide additional features and benefits to both the utility company and end consumer, and may serve as a platform for providing other features, such as communications services, local and remote management, and intelligence to components of the distribution grid. A GER device may include sensors to measure electrical properties of incoming and outgoing power, and may include an electrical circuit layer having a central DC power stage. A GER device may also include a communications platform for one or more communication devices to communicate with a utility, power consumers, other electrical devices/parties, and/or other GER devices to form a micro-grid.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: May 16, 2023
    Assignee: Gridbridge, Inc.
    Inventors: Chad Eckhardt, Stephen Timothy Watts
  • Patent number: 11647623
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes providing a substrate having a first top surface; forming an isolation region in the substrate to surround an active region; forming a recess in the active region; disposing a first conductive material within the recess to form a buried power line and a buried signal line; forming a first circuit layer and a second circuit layer on the first top surface of the substrate, wherein the first circuit layer covers the buried power line and the buried signal line, and the second circuit layer is separated from the first circuit layer; and forming a cell capacitor over the first circuit layer.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: May 9, 2023
    Inventors: Chiang-Lin Shih, Tseng-Fu Lu, Jeng-Ping Lin
  • Patent number: 11640921
    Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: May 2, 2023
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Franck Julien, Abderrezak Marzaki
  • Patent number: 11640970
    Abstract: A capacitor structure includes an insulation layer and a capacitor unit disposed on the insulation layer. The capacitor unit includes a first electrode, a second electrode, a first dielectric layer, and a patterned conductive layer. The second electrode is disposed above the first electrode in a vertical direction. The first dielectric layer is disposed between the first electrode and the second electrode in the vertical direction. The patterned conductive layer is disposed between first electrode and the second electrode, the patterned conductive layer is electrically connected with the first electrode, and the first dielectric layer surrounds the patterned conductive layer in a horizontal direction.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: May 2, 2023
    Inventors: Chih-Tung Yeh, Kuang-Pi Lee, Wen-Jung Liao
  • Patent number: 11637104
    Abstract: Semiconductor memory devices and methods of forming the same are provided. The semiconductor devices may include a vertical insulating structure extending in a first direction on a substrate, a semiconductor pattern extending along a sidewall of the vertical insulating structure, a bitline on a first side of the semiconductor pattern, an information storage element on a second side of the semiconductor pattern and including first and second electrodes, and a gate electrode on the semiconductor pattern and extending in a second direction that is different from the first direction. The bitline may extend in the first direction and may be electrically connected to the semiconductor pattern. The first electrode may have a cylindrical shape that extends in the first direction, and the second electrode may extend along a sidewall of the first electrode.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: April 25, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yong-Hoon Son
  • Patent number: 11631668
    Abstract: An electronic circuit having a first terminal and a second terminal. The electronic circuit includes a plurality of diodes connected in parallel, the plurality of diodes including a first diode and a second diode that respectively have applied thereto a first forward voltage and a second forward voltage, the second forward voltage being higher than the first forward voltage. A first path and a second path are formed from the first terminal, respectively via the first diode and the second diode, to the second terminal. An inductance of the first path is larger than an inductance of the second path.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 18, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 11616009
    Abstract: A semiconductor device includes a semiconductor element, an internal electrode connected to the semiconductor element, a sealing resin covering the semiconductor element and a portion of the internal electrode, and an external electrode exposed from the sealing resin and connected to the internal electrode. The internal electrode includes a wiring layer and a columnar portion, where the wiring layer has a wiring layer front surface facing the back surface of the semiconductor element and a wiring layer back surface facing opposite from the wiring layer front surface in the thickness direction. The columnar portion protrudes in the thickness direction from the wiring layer front surface. The columnar portion has an exposed side surface facing in a direction perpendicular to the thickness direction. The external electrode includes a first cover portion covering the exposed side surface.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: March 28, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Yusuke Harada, Mamoru Yamagami
  • Patent number: 11610967
    Abstract: The invention relates to a vertical compound semiconductor structure having a substrate with a first main surface and an opposite second main surface, a vertical channel opening extending completely through the substrate between the first main surface and the second main surface and a layer stack arranged within the vertical channel opening. The layer stack includes an electrically conductive layer arranged within the vertical channel opening and a compound semiconductor layer arranged within the vertical channel opening. The compound semiconductor layer includes a compound semiconductor layer arranged on the electrically conductive layer and connected galvanically to the electrically conductive layer. Further, the invention relates to a method for producing such a vertical compound semiconductor structure.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: March 21, 2023
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Peter Ramm, Armin Klumpp
  • Patent number: 11610802
    Abstract: A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: March 21, 2023
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 11609402
    Abstract: An electronic device includes a carrier substrate having a front face. An electronic chip is mounted on the front face of the carrier substrate and includes an optical component. An encapsulation cover is mounted on top of the front face of the carrier substrate and bounds a chamber within which the chip is situated. A front opening extends through the cover and is situated in front of the optical component. An optical element, designed to allow light to pass, is mounted within the chamber at a position which covers the front opening of the encapsulation cover. The optical element includes a central region designed to deviate the light and having an optical axis aligned with the front opening and the optical component. A positioning pattern is provided on the optical element to assist with mounting the optical element to the cover and mounting the cover to the carrier substrate.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 21, 2023
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Nicolas Mastromauro, Roy Duffy, Karine Saxod
  • Patent number: 11600498
    Abstract: A semiconductor package includes a leadframe forming a plurality of leads with a die attach site, a semiconductor die including a set of die contacts mounted to the die attach site in a flip chip configuration with each die contact of the set of die contacts electrically connected to leadframe via one of a set of solder joints, a set of solder joint capsules covering each of the set of solder joints against the leadframe, a clip mounted to the leadframe over the semiconductor die with a clip solder joint. The solder joint capsules restrict flow of the solder joints of the semiconductor die contacts in the flip chip configuration such that the solder remains in place if remelted during later clip solder reflow.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: March 7, 2023
    Inventors: James Raymond Maliclic Baello, Steffany Ann Lacierda Moreno
  • Patent number: 11594529
    Abstract: A memory device includes a cell block including memory cells; a control logic; and a correction block in a dummy region in a core region. The correction block may include first metal lines extending in a first direction; vias extending in a second direction; and second metal lines extending in a third direction. Each of the second metal lines may have a metal center line defining a center of each of the second metal lines in the first direction. Each of the vias may have a via center line defining a center of each of the vias in the first direction. At least one metal center line and at least one via center line may be spaced apart from each other by a first gap in the first direction.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: February 28, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Min Chul Han
  • Patent number: 11594457
    Abstract: The present invention includes a method for creating a system in a package with integrated lumped element devices and active devices on a single chip/substrate for heterogeneous integration system-on-chip (HiSoC) in photo-definable glass, comprising: masking a design layout comprising one or more electrical passive and active components on or in a photosensitive glass substrate; activating the photosensitive glass substrate, heating and cooling to make the crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate; and depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate on the surface of the photodefinable glass.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: February 28, 2023
    Assignee: 3D Glass Solutions, Inc.
    Inventors: Jeb H. Flemming, Kyle McWethy
  • Patent number: 11588073
    Abstract: This application describes a light emitting device or an assembly of light emitting devices. In the completed light emitting device, a distributed Bragg reflector minimizes the possibility of disturbing adjacent light emitting devices. Methods to fabricate such devices and assemblies of devices are also described.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: February 21, 2023
    Assignee: Black Peak LLC
    Inventor: Scott Brad Herner
  • Patent number: 11581222
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack and a source/drain contact structure formed over a substrate. A first gate spacer is separated the gate stack from the source/drain contact structure and extends above top surfaces of the gate stack and the source/drain contact structure. An insulating capping layer covers the top surface of the gate stack and extends on the top surface of the first gate spacer. A conductive via structure partially covers the top surface of the insulating capping layer and the top surface of the source/drain contact structure. A first insulating layer surrounds the conductive via structure and partially covers the top surface of the source/drain contact structure.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: February 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Jui Huang, Li-Te Lin, Pinyen Lin
  • Patent number: 11581312
    Abstract: A semiconductor device may include first channels on a first region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, second channels on a second region of the substrate and spaced apart from each other in the vertical direction, a first gate structure on the first region of the substrate and covering at least a portion of a surface of each of the first channels, and a second gate structure on the second region of the substrate and covering at least a portion of a surface of each of the second channels. The second channels may be disposed at heights substantially the same as those of corresponding ones of the first channels, and a height of a lowermost one of the second channels may be greater than a height of a lowermost one of the first channels.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: February 14, 2023
    Inventors: Chang-Woo Noh, Jae-Hyeoung Ma, Dong-Îl Bae
  • Patent number: 11574889
    Abstract: A method of manufacturing a power module comprising two substrates is provided, wherein the method comprises disposing a compensation layer of a first thickness above a first substrate; disposing a second substrate above the compensation layer; and reducing the thickness of the compensation layer from the first thickness to a second thickness after the second substrate is disposed on the compensation layer.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: February 7, 2023
    Assignee: Infineon Technologies AG
    Inventors: Ottmar Geitner, Wolfram Hable, Andreas Grassmann, Frank Winter, Christian Neugirg, Ivan Nikitin