Patents Examined by Duy T Nguyen
  • Patent number: 10446695
    Abstract: A JFET having vertical and horizontal channel elements may be made from a semiconductor material such as silicon carbide using a first mask for multiple implantations to form a horizontal planar JFET region comprising a lower gate, a horizontal channel, and an upper gate, all above a drift region resting on a drain substrate region, such that the gates and horizontal channel are self-aligned with the same outer size and outer shape in plan view. A second mask may be used to create a vertical channel region abutting the horizontal channel region. The horizontal channel and vertical channel may each have multiple layers with varying doping concentrations. Angled implantations may use through the first mask to implant portions of the vertical channel regions. The window of the second mask may partially overlap the horizontal JFET region to insure abutment of the vertical and horizontal channel regions.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: October 15, 2019
    Assignee: United Silicone Carbide, Inc.
    Inventors: Anup Bhalla, Zhongda Li
  • Patent number: 10438796
    Abstract: Native oxides and residue are removed from surfaces of a substrate by performing a multiple-stage native oxide cleaning process. In one example, the method for removing native oxides from a substrate includes supplying a first gas mixture including an inert gas onto a surface of a material layer disposed on a substrate into a first processing chamber, wherein the material layer is a III-V group containing layer for a first period of time, supplying a second gas mixture including an inert gas and a hydrogen containing gas onto the surface of the material layer for a second period of time, and supplying a third gas mixture including a hydrogen containing gas to the surface of the material layer while maintaining the substrate at a temperature less than 550 degrees Celsius.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: October 8, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chun Yan, Xinyu Bao
  • Patent number: 10439432
    Abstract: An electrical distribution grid energy management and router device, or GER device, may be installed in a distribution grid, and route power from power supply to one or more power consumers. The GER devices described herein may provide platforms to add one or more features to a distribution transformer, provide additional features and benefits to both the utility company and end consumer, and may serve as a platform for providing other features. A GER device may include sensors to measure electrical properties of incoming and outgoing power, and may include an electrical circuit layer having a central DC power stage. A GER device may include a physical layer providing a communications platform for one or more communication devices that may communicate with other GER devices to form a micro-grid, a utility, power consumers, third parties, and other electrical devices.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: October 8, 2019
    Assignee: GRIDBRIDGE, INC.
    Inventors: Chad Eckhardt, Stephen Timothy Watts
  • Patent number: 10429976
    Abstract: A method for manufacturing a panel is provided, including forming a first conductive pattern including a first portion and a second portion, forming a second conductive pattern connecting between the first portion and the second portion, and thermally treating a mask pattern of an insulation material to form an insulation pattern substantially covering a side surface of the second conductive pattern. A panel manufactured by using the foregoing method is also provided. A horizontal distance between an outer side surface of the insulation pattern and an inner side surface adjacent to the second conductive pattern is less than 3 micrometers.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: October 1, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventor: Kai Pei
  • Patent number: 10431598
    Abstract: A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Stuart B. Molin, Michael A. Stuber
  • Patent number: 10424524
    Abstract: Disclosed is a method of manufacturing a semiconductor device that includes adhering a plurality of semiconductor substrates and a framing member to a supporting surface of a carrier substrate. The semiconductor substrates can be wafers that can be diced or cut into a plurality of dies. Thus, the wafers each have respective active surfaces and at least one respective integrated circuit region. The method can further include encapsulating the framing member and the plurality of semiconductor substrates within an encapsulant. Subsequently, the carrier substrate is removed and a redistribution layer (RDL) is formed on the semiconductor substrates and the framing member.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: September 24, 2019
    Assignees: CHENGDU ESWIN SIP TECHNOLOGY CO., LTD., BEIJING ESWIN TECHNOLOGY CO., LTD.
    Inventors: Minghao Shen, Xiaotian Zhou
  • Patent number: 10424657
    Abstract: A tri-gate FinFET device includes a fin that is positioned vertically above and spaced apart from an upper surface of a semiconductor substrate, wherein the fin has an upper surface, a lower surface opposite of the upper surface, a first side surface, and a second side surface opposite of the first side surface. The axis of the fin in a height direction of the fin is oriented substantially parallel to the upper surface of the semiconductor substrate, and the first side surface of the fin contacts an insulating material. A gate structure is positioned around the upper surface, the second side surface, and the lower surface of the fin, and a gate contact structure is conductively coupled to the gate structure.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: September 24, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Andreas Knorr
  • Patent number: 10412898
    Abstract: Bale measuring method for a rectangular baler includes the steps of: measuring a movement of a binding material that is being tied around a bale; using the measured movement of the binding material to calibrate a measurement and calculation tool for measuring a movement of the bale in the baler and for calculating a length of the bale based on said measurement; determining the length of the bale using the calibrated measurement and calculation tool as the bale moves backward in the baler.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: September 17, 2019
    Assignee: CNH Industrial America LLC
    Inventors: Tom Coen, Didier O. M. Verhaeghe
  • Patent number: 10416041
    Abstract: A combustion state parameter calculation method for an internal combustion engine, which is capable of continuously calculating a combustion state parameter while properly maintaining the accuracy of the calculated parameter even when part of in-cylinder pressure sensors is in failure. In the combustion state parameter calculation method, as a combustion state parameter, a first combustion state parameter dependent on the magnitude of in-cylinder pressure is calculated based on a detection value from an in-cylinder pressure sensor, on a cylinder-by-cylinder basis. When it is determined that a characteristic abnormality failure in which the magnitude of the detection value deviates from the actual in-cylinder pressure has occurred in part of the in-cylinder pressure sensors and has not occurred in the other in-cylinder pressure sensors, the first combustion state parameter of a failure-determined cylinder is calculated based on the detection value from the other in-cylinder pressure sensors.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: September 17, 2019
    Assignees: HONDA MOTOR CO., LTD., KEIHIN CORPORATION
    Inventors: Shusuke Akazaki, Taisuke Inoue, Shunichi Saito
  • Patent number: 10410904
    Abstract: Disclosed is a method of peeling a protective member from a wafer, the protective member composed of a resin and a film, the film attached to one side of the wafer through the resin in a state in which a protruding portion is formed. The method includes: a step of holding the other side of the wafer, with the protective member on the lower side; an outer circumferential edge adhered resin peeling step of grasping the protruding portion of the protective member, and pulling the protruding portion to an outer side than an outer circumferential edge of the wafer, to peel the resin adhered to the outer circumferential edge of the wafer from the outer circumferential edge of the wafer; and a step of peeling, after the outer circumferential edge adhered resin peeling step, the whole body of the protective member from the wafer.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: September 10, 2019
    Assignee: Disco Corporation
    Inventor: Kosei Kiyohara
  • Patent number: 10408970
    Abstract: A method of location of a device includes a displacement law containing a corrective factor of a bias combined by an arithmetical operation with a measured variable, and particles, each particle being associated with a current value of the corrective factor. The current value of the corrective factor being constructed at each iteration on the basis of a previous current value of the corrective factor, computed during a previous iteration, to which is added a random variable drawn according to a predefined probability law. The current values of various particles are initialized, before the first iteration, to various initial values, and during each iteration, for each particle whose coordinates are updated with the aid of this displacement law, the value of the corrective factor in the displacement law is taken equal to this corrective factor's current value associated with the particle.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: September 10, 2019
    Assignees: MOVEA, Commissariat à l'énergie atomique et aux énergies alternatives
    Inventor: Christophe Villien
  • Patent number: 10388814
    Abstract: Photovoltaic devices including direct gap III-V absorber materials and operatively associated back structures enhance efficiency by enabling photon recycling. The back structures of the photovoltaic devices include wide bandgap III-V layers, highly doped (In)GaAs layers, patterned oxide layers and metal reflectors that directly contact the highly doped (In)GaAs layers through vias formed in the back structures. Localized ohmic contacts are formed in the back structures of the devices.
    Type: Grant
    Filed: June 10, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10379563
    Abstract: A system for providing electric energy to users includes a server node, a set of supply nodes and a set of mobile terminals. One or more communication networks connect the server node to the supply nodes. Each supply node provides output energy via a remote-controlled outlet. Each mobile terminal communicates with the server node over a wireless interface. The supply nodes repeatedly send respective instruction inquiries to the server node, which also receives activation requests from the mobile terminals specifying a particular outlet and an identity of a mobile-terminal user. In response to an activation request, the server node checks if the user identity is authorized to activate the outlet, and if so; in response to an instruction inquiry from a first supply node associated with the outlet, sends an activation accept to the first supply node enabling output of electric energy from the outlet.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: August 13, 2019
    Assignee: EPSPOT AB
    Inventor: Jan Christian Olin
  • Patent number: 10374154
    Abstract: One illustrative method disclosed herein includes forming an MRAM memory array and a plurality of peripheral circuits for an integrated circuit product above a semiconductor substrate, forming a patterned layer of a metal-containing shielding material above the substrate, the patterned layer of metal-containing shielding material covering the MRAM memory array while leaving an area above the plurality of peripheral circuits exposed, and, with the patterned layer of metal-containing shielding material in position, performing a silicon dangling bond passivation anneal process on the integrated circuit product.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: August 6, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Dimitri Houssameddine, Chenchen Jacob Wang, Bin Liu
  • Patent number: 10365096
    Abstract: A bale measuring method for a rectangular baler having a bale chamber in which bales are formed. The bale measuring method includes steps of measuring a movement of crop material downstream of the bale chamber as the crop material moves backward in the baler, using the measured movement of the crop material downstream of the bale chamber to calibrate a measurement and calculation tool for measuring a movement of crop material in the bale chamber and for calculating a length of a bale being formed in the bale chamber based on the measurement, and determining the length of the bale being formed in the bale chamber using the calibrated measurement and calculation tool as the bale moves backward in the baler.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: July 30, 2019
    Assignee: CNH Industrial America LLC
    Inventors: Didier Verhaeghe, Tom Coen
  • Patent number: 10367080
    Abstract: A method for forming layers suitable for a V-NAND stack is disclosed. Specifically, the method may include multiple cycles for forming an oxide and a nitride in order to form an oxynitride layer.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: July 30, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Fu Tang, Qi Xie, Jan Willem Maes, Xiaoqiang Jiang, Michael Eugene Givens
  • Patent number: 10355747
    Abstract: An appliance can comprise a controller, a first memory, and a near field communication (NFC) tag having a second memory being coupled to the controller. The NFC tag is configured to dynamically set a web service address from an external server based upon a write command from a mobile device in communication with the NFC tag. The controller can parse the web service address to begin a set of diagnostic tests for the appliance and write a web service address to the NFC tag based upon a result of the diagnostic tests. The mobile device can read the written web service address and load a web page with detailed information for the particular appliance and the problem diagnosed therewith.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: July 16, 2019
    Assignee: Whirlpool Corporation
    Inventor: Wyndham Fairchild Gary, Jr.
  • Patent number: 10343896
    Abstract: A method for fabricating an integrated MEMS device and the resulting structure therefore. A control process monitor comprising a MEMS membrane cover can be provided within an integrated CMOS-MEMS package to monitor package leaking or outgassing. The MEMS membrane cover can separate an upper cavity region subject to leaking from a lower cavity subject to outgassing. Differential changes in pressure between these cavities can be detecting by monitoring the deflection of the membrane cover via a plurality of displacement sensors. An integrated MEMS device can be fabricated with a first and second MEMS device configured with a first and second MEMS cavity, respectively. The separate cavities can be formed via etching a capping structure to configure each cavity with a separate cavity volume. By utilizing an outgassing characteristic of a CMOS layer within the integrated MEMS device, the first and second MEMS cavities can be configured with different cavity pressures.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: July 9, 2019
    Assignee: mCube, Inc.
    Inventor: Te-Hsi “Terrence” Lee
  • Patent number: 10347774
    Abstract: A problem addressed by an embodiment of the present invention lies in providing a UBM structure which includes thin layers and can prevent diffusion of solder into an electrode. The UBM structure according to an embodiment of the present invention includes: a first UBM layer on an electrode, a second UBM layer on the first UBM layer, and a passivated metal layer between the first UBM layer and the second UBM layer. The passivated metal layer functions as a barrier layer with respect to solder diffusion.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: July 9, 2019
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Noriyuki Kishi, Tatsuhiro Koizumi, Hiroyuki Shiraki, Mitsuru Tamashiro, Masaya Yamamoto
  • Patent number: 10347505
    Abstract: A method includes exposing and developing a negative photo resist, and performing a treatment on the negative photo resist using an electron beam. After the treatment, a layer underlying the photo resist is etched using the negative photo resist as an etching mask.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Kuo Hsieh, Tsung-Hung Chu, Ming-Chung Liang