Patents Examined by Duy-Vu N. Deo
  • Patent number: 10478939
    Abstract: The present invention provides a means allowing achievement of sufficient planarization of the surface of an object to be polished containing two or more types of materials. The present invention is a polishing method for polishing an object to be polished containing two or more types of materials by using a polishing composition, the polishing method including equalization of the surface zeta potential of the object to be polished.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: November 19, 2019
    Assignee: FUJIMI INCORPORATED
    Inventors: Yukinobu Yoshizaki, Satoru Yarita, Shogo Onishi
  • Patent number: 10475658
    Abstract: Compositions useful for the selective removal of silicon-containing materials relative to germanium-containing materials, and vice versa, from a microelectronic device having same thereon. The removal compositions include at least one diol and are tunable to achieve the required Si:Ge removal selectivity and etch rates.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: November 12, 2019
    Assignee: ENTEGRIS, INC.
    Inventors: Steven Bilodeau, Emanuel I. Cooper
  • Patent number: 10475649
    Abstract: A patterning method includes the following steps. A hard mask layer is formed on a substrate. Mandrels are formed on the hard mask layer. Mask patterns are formed on the mandrels. Each of the mask patterns is formed on one of the mandrels. Spacers are formed on the hard mask layer. Each of the spacers is formed on a sidewall of one of the mandrels and on a sidewall of one of the mask patterns. A cover layer covering the hard mask layer, the spacers and the mask patterns is formed. A planarization process is performed to remove the cover layer on the mask patterns and the spacer and remove the mask patterns. A part of the cover layer remains between the spacers after the planarization process. The mandrels and the cover layer are removed after the planarization process.
    Type: Grant
    Filed: May 6, 2018
    Date of Patent: November 12, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Chen Chuang, Fu-Che Lee, Ming-Feng Kuo, Cheng-Yu Wang, Hsien-Shih Chu, Li-Chiang Chen
  • Patent number: 10465112
    Abstract: The disclosure is related to a composition for etching, a method for manufacturing the composition, and a method for fabricating a semiconductor using the same. The composition may include a first inorganic acid, at least one of silane inorganic acid salts produced by reaction between a second inorganic acid and a silane compound, and a solvent. The second inorganic acid may be at least one selected from the group consisting of a sulfuric acid, a fuming sulfuric acid, a nitric acid, a phosphoric acid, and a combination thereof.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: November 5, 2019
    Inventors: Jin Uk Lee, Jae Wan Park, Jung Hun Lim
  • Patent number: 10460938
    Abstract: Techniques disclosed herein provide a method of patterning for creating high-resolution features and also for cutting on pitch of sub-resolution features. Techniques include forming bi-layer or multi-layer mandrels and then forming one or more lines of material running along sidewalls of the mandrels. The different materials can have different etch resistivities to be able to selectively etch one or more of the materials to create features and create cuts and blocks where specified. Etching using an etch mask positioned above or below this multi-line layer further defines a pattern that is transferred into an underlying layer. Having a mandrel of two or more layers of material enables one of those materials to be sacrificial such as when etching a spin-on reversal overcoat material that has filled-in open spaces, but leaves an overburden.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: October 29, 2019
    Assignee: Tokyo Electron Limited
    Inventor: Anton J. deVilliers
  • Patent number: 10453696
    Abstract: The present invention provides a method and apparatus for etching a photomask substrate with enhanced process monitoring, for example, by providing for optical monitoring at certain regions of the photomask to obtain dual endpoints, e.g., etch rate or thickness loss of both a photoresist layer and an absorber layer. By monitoring transmissity of an optical beam transmitted through areas having photoresist layer and etched absorber layer at two different predetermined wavelength, dual process endpoints may be obtained by a signal optical detection.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: October 22, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Michael Grimbergen
  • Patent number: 10446408
    Abstract: A microelectronic method for etching a layer containing silicon nitride is provided, including the following successive steps: modifying the layer containing silicon nitride (SiN) so as to form at least one modified zone, the modifying including at least one implantation of ions made from hydrogen (H) in the layer containing SiN; and removing the at least one modified zone, the removing of the at least one modified zone including at least one step of etching of the at least one modified zone using a chemistry including at least: at least one compound chosen from the fluorocarbon compounds (CxFz) and the hydrofluorocarbon compounds (CxHyFz), and at least one compound chosen from SiwCl(2w+2) and SiwF(2w+2).
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: October 15, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Nicolas Posseme
  • Patent number: 10438806
    Abstract: Techniques herein include methods for selectively modifying chemical properties of organosilicates including periodic mesoporous organosilicates (PMOs) in situ for use in fabrication of semiconductor devices. With techniques herein, such materials are manipulated in their chemical properties after deposition and can accordingly be used as sacrificial patterning films and/or as patterning enabling materials. Using selective treatments such as annealing, curing, plasma exposure, and silylation, chemical properties such as etch resistance and hydrophobicity can be changed to enable a given patterning operation. A given film can be etch resistant for one patterning operation, and then changed to be etch removable for a subsequent patterning operation.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 8, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Kathleen Nafus, Serge Biesemans
  • Patent number: 10418224
    Abstract: In the plasma etching method, a sample is placed on a stage in a chamber. A first gas is introduced into the chamber. Electric field is supplied within the chamber to plasma is generated from the first gas. A first RF power of a first frequency, which is for generating a bias voltage in the sample for etching the sample with radicals which are generated in the plasma while the plasma is generated, is supplied to the stage. A second gas is introduced from a position in outer periphery of a surface of the stage, on which the sample is placed. A second RF power of a second frequency higher than the first frequency and capable of generating plasma from the second gas above the stage that allows radicals generated in the plasma generated from the second gas to be supplied in the outer periphery, is supplied to the stage.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: September 17, 2019
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Naoyuki Kofuji, Ken'etsu Yokogawa, Nobuyuki Negishi, Masami Kamibayashi, Masatoshi Miyake
  • Patent number: 10410861
    Abstract: Methods for void-free material filling of fine recessed features have been disclosed in various embodiments. According to one embodiment, the method includes a) providing a substrate containing a recessed feature having an opening, a sidewall and a bottom, the sidewall including an area of retrograde profile relative to a direction extending from a top of the recessed feature to the bottom of the recessed feature, b) depositing an amount of a material in the recessed feature, the material having a greater thickness at the bottom than on the sidewall of the recessed feature, c) stopping the depositing in step b) before the recessed feature is fully filled with the material, d) etching a portion of the material from the recessed feature, and e) depositing an additional amount of the material to fully fill the recessed feature with the material without any voids in the recessed feature.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: September 10, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara N. Tapily, Gerrit J. Leusink
  • Patent number: 10403492
    Abstract: Processes for surface treatment of a workpiece are provided. In one example implementation, organic radicals (e.g., methyl CH3 radicals) can be generated by exciting and/or dissociating hydrogen and/or inert gas (e.g., Ar, He, etc) molecules in a remote plasma source and a subsequent reaction with organic molecule (alkanes and alkenes). The organic radicals (e.g., methyl CH3 radicals) can be exposed to the silicon and/or silicon germanium surfaces. After exposure to the organic radicals, the silicon and/or silicon germanium surfaces can be stable in air for a time period (e.g., days) with reduced surface oxidation such that the silicon and/or silicon germanium surfaces can be effectively protected from oxidation. As such, native surface oxide removal process before subsequent process steps can be eliminated.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: September 3, 2019
    Assignee: Mattson Technology, Inc.
    Inventors: Michael X. Yang, Hua Chung, Xinliang Lu, Haochen Li, Ting Xie, Qi Zhang
  • Patent number: 10403518
    Abstract: A plasma processing method includes etching a removing target film by supplying onto a peripheral portion of a substrate being rotated a first processing liquid containing hydrofluoric acid and nitric acid at a first mixing ratio; and etching the removing target film by, after supplying the first processing liquid onto the substrate, supplying onto the peripheral portion of the substrate being rotated a second processing liquid containing the hydrofluoric acid and the nitric acid at a second mixing ratio in which a content ratio of the hydrofluoric acid is lower and a content ratio of the nitric acid is higher than in the first processing liquid. When removing the removing target film made of SiGe, amorphous silicon or polysilicon from the peripheral portion thereof, an underlying film, for example, a film made of SiO2, which exists under the removing target film, can be appropriately left.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: September 3, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiromitsu Nanba, Tatsuhiro Ueki
  • Patent number: 10381227
    Abstract: The invention includes a method of promoting atomic layer etching (ALE) of a surface. In certain embodiments, the method comprises sequential reactions with a metal precursor and a halogen-containing gas. The invention provides a solid substrate obtained according to any of the methods of the invention. The invention further provides a porous substrate obtained according to any of the methods of the invention. The invention further provides a patterned solid substrate obtained according to any of the methods of the invention.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: August 13, 2019
    Assignee: The Regents of the University of Colorado, a body corporate
    Inventors: Steven M. George, Younghee Lee
  • Patent number: 10381229
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. The spacer material layers are formed as, or are replaced with, electrically conductive layers. An insulating cap layer is formed over the alternating stack. After formation of memory stack structures through each layer of the alternating stack and the insulating cap layer, a line trench straddling a neighboring pair of rows of the memory stack is formed. Sidewalls of the line trench include a sidewall of each memory stack structure within the neighboring pair of rows of the memory stack structures. A drain select gate dielectric and a drain select electrode line are formed within the line trench. The drain select electrode line controls flow of electrical current through an upper portion of a vertical semiconductor channel within each memory stack structure below the drain regions to activate or deactivate the neighboring rows.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shinsuke Yada, Akihisa Sai, Kiyohiko Sakakibara
  • Patent number: 10373804
    Abstract: Systems and methods for tunable workpiece biasing in a plasma reactor are provided herein. In some embodiments, a system includes: a plasma chamber that performs plasma processing on a workpiece, a first pulsed voltage source, coupled directly to a workpiece, a second pulsed voltage source, coupled capacitively to the workpiece, and a biasing controller comprising one or more processors, and memory, wherein the memory comprises a set of computer instructions that when executed by the one or more processors, independently controls the first pulsed voltage source and the second pulsed voltage source based on one or more parameters of the first pulsed voltage source and the second pulsed voltage source in order to tailor ion energy distribution of the flux of ions directed to the workpiece.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: August 6, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Travis Koh, Philip Allan Kraus, Leonid Dorf, Prabu Gopalraja
  • Patent number: 10353127
    Abstract: The wire grid polarizer (WGP) comprises an array of parallel, elongated nanostructures located over a surface of a transparent substrate and a plurality of spaces, including a space between adjacent nanostructures. Each of the nanostructures can include (1) a plurality of parallel, elongated wires located on the substrate, including an inner-pair located between an outer-pair; (2) lateral-gaps between each wire of the outer-pair and an adjacent wire of the inner-pair; (3) and a center-gap between the two wires of the inner-pair.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: July 16, 2019
    Assignee: Moxtek, Inc.
    Inventors: Bin Wang, Hua Li, Brian Bowers
  • Patent number: 10329455
    Abstract: A CMP slurry including a carrier, a particulate material within the carrier including an oxide, carbide, nitride, boride, diamond or any combination thereof, an oxidizer including at least one material selected from the group of peroxides, persulfates, permanganates, periodates, perchlorates, hypocholorites, iodates, peroxymonosulfates, cerric ammonium nitrate, periodic acid, ferricyanides, or any combination thereof, and a material removal rate index (MRR) of at least 500 nm/hr and an average roughness index (Ra) of not greater than 5 Angstroms according to the Standardized Polishing test.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: June 25, 2019
    Assignee: SAINT-GOBAIN CERAMICS & PLASTICS, INC.
    Inventors: Ian T. Sines, Angela Kwapong, Carlijn L. Mulder, Douglas E. Ward, Vianney Le Roux
  • Patent number: 10319649
    Abstract: Methods and systems for etching substrates using a remote plasma are described. Remotely excited etchants are formed in a remote plasma and flowed through a showerhead into a substrate processing region to etch the substrate. Optical emission spectra are acquired from the substrate processing region just above the substrate. The optical emission spectra may be used to determine an endpoint of the etch, determine the etch rate or otherwise characterize the etch process. A weak plasma may be present in the substrate processing region. The weak plasma may have much lower intensity than the remote plasma. In cases where no bias plasma is used above the substrate in an etch process, a weak plasma may be ignited near a viewport disposed near the side of the substrate processing region to characterize the etchants.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: June 11, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Tae Seung Cho, Soonam Park, Junghoon Kim, Dmitry Lubomirsky, Shankar Venkataraman
  • Patent number: 10315285
    Abstract: The invention provides a chemical-mechanical polishing composition and a method of chemically-mechanically polishing a substrate, such as a nickel-phosphorous substrate. The composition contains water, silica particles, a first alcohol comprising one or more of monohydric alcohol, polyhydric alcohol, and diglycol, a second alcohol in the form of polyvinyl alcohol, a nickel complexing agent, and optionally hydrogen peroxide, pH adjuster, and/or biocide. The method involves contacting the substrate with a polishing pad and the chemical-mechanical polishing composition, moving the polishing pad and the polishing composition relative to the substrate, and abrading at least a portion of the substrate to polish the substrate.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: June 11, 2019
    Assignee: Cabot Microelectronics Corporation
    Inventors: Tong Li, Michael White, Selvaraj Palanisamy Chinnathambi, Ke Zhang
  • Patent number: 10316835
    Abstract: In a method of an embodiment, a pressure sensor is selected from first and second pressure sensors according to a set flow rate. A measurable maximum pressure of the second pressure sensor is higher than a measurable maximum pressure of first pressure sensor. The target pressure of a chamber is determined according to the set flow rate. Until the pressure of the chamber reaches the target pressure after gas is started to be output from the flow rate controller to the chamber at an output flow rate according to the set flow rate and a pressure controller provided between the chamber and an exhaust apparatus is closed, the pressure of the chamber is measured by the selected pressure sensor. The output flow rate of the flow rate controller is determined from a rate of rise of the pressure of the chamber.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: June 11, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jun Yamashima, Shinichiro Hayasaka, Toshihiro Tsuruta, Hiroshi Fujii, Junichi Akiba, Naoya Jami, Naotsugu Hoshi