Patents Examined by Duy-Vu N. Deo
  • Patent number: 11189497
    Abstract: A method includes forming a film over a substrate; increasing a surface roughness of the film; and planarizing the film using a first chemical mechanical planarization (CMP) process after increasing the surface roughness.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chin Nien, Gang Huang, William Weilun Hong
  • Patent number: 11189499
    Abstract: Methods for the atomic layer etch (ALE) of tungsten or other metal layers are disclosed that use in part sequential oxidation and reduction of tungsten/metal layers to achieve target etch parameters. For one embodiment, a metal layer is first oxidized to form a metal oxide layer and an underlying metal layer. The metal oxide layer is then reduced to form a surface metal layer and an underlying metal oxide layer. The surface metal layer is then removed to leave the underlying metal oxide layer and the underlying metal layer. Further, the oxidizing, reducing, and removing processes can be repeated to achieve a target etch depth. In addition, a target etch rate can also achieved for each process cycle of oxidizing, reducing, and removing.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: November 30, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yu-Hao Tsai, Du Zhang, Mingmei Wang, Aelan Mosden, Matthew Flaugh
  • Patent number: 11183392
    Abstract: According to an embodiment of the present disclosure, a method of manufacturing semiconductor device includes: forming a first mandrel and a second mandrel over a mask layer; depositing a spacer layer over the first mandrel and the second mandrel; forming a line-end cut pattern over the spacer layer between the first mandrel and the second mandrel; depositing a protection layer over the line-end cut pattern; etching the protection layer and exposing upper portion of the line-end cut pattern; reducing a width of the line-end cut pattern; etching the spacer layer to expose the first mandrel and the second mandrel; and patterning the mask layer using the etched spacer layer and the reduced line-end cut pattern as an etch mask.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: November 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jiann-Horng Lin, Chao-Kuei Yeh, Ying-Hao Wu, Tai-Yen Peng, Chih-Hao Chen, Chih-Sheng Tian
  • Patent number: 11183398
    Abstract: A process is provided in which a hard mask material comprising ruthenium is used. Ruthenium provides a hard mask material that is etch resistant to many of the plasma chemistries typically used for processing substrate patterning layers, including layers such as, for example, nitrides, oxides, anti-reflective coating (ARC) materials, etc. Further, ruthenium may be removed by plasma chemistries that do not remove nitrides, oxides, ARC materials, etc. For example, ruthenium may be easily removed through the use of an oxygen (O2) plasma. Further, ruthenium may be deposited as a thin planar 10 nm order film over oxides and nitrides and may be deposited as a planar layer.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: November 23, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Zhiying Chen, Alok Ranjan, Peter Ventzek
  • Patent number: 11161217
    Abstract: Semiconductor wafers are polished on both sides between polishing pads of a Shore A hardness of at least 80 and a compressibility of less than 3%, attached to upper and lower polishing plates, the polishing pads attached to the upper and lower polishing plates by bonding the polishing pads to the plates, and positioning an intermediate pad having a compressibility of at least 3% between the two bonded polishing pads as an intermediate layer and then pressing together the two polishing pads with the intermediate pad situated therebetween for a period of time.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: November 2, 2021
    Assignee: SILTRONIC AG
    Inventor: Vladimir Dutschke
  • Patent number: 11158528
    Abstract: Methods and systems for controlling temperatures in plasma processing chamber with a combination of proportional and pulsed fluid control valves. A heat transfer fluid loop is thermally coupled to a chamber component, such as a chuck. The heat transfer fluid loop includes a supply line and a return line to each of hot and cold fluid reservoirs. In an embodiment, an analog valve (e.g., in the supply line) is controlled between any of a closed state, a partially open state, and a fully open state based on a temperature control loop while a digital valve (e.g., in the return line) is controlled to either a closed state and a fully open state.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: October 26, 2021
    Assignee: Applied Materials, Inc.
    Inventor: Chetan Mahadeswaraswamy
  • Patent number: 11145517
    Abstract: The present disclosure relates to a semiconductor device manufacturing system. The semiconductor device manufacturing system can include a chamber, a slit valve configured to provide access to the chamber, a chuck disposed in the chamber and configured to hold a substrate, and a gas curtain device disposed between the chuck and the slit valve and configured to flow an inert gas to form a gas curtain. An example benefit of the gas curtain is to block an inflow of oxygen or moisture from entering the chamber to ensure a yield and reliability of the semiconductor manufacturing processes conducted in the chamber.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Kent Lin
  • Patent number: 11145514
    Abstract: Provided are a removal liquid for removing an oxide of a Group III-V element, an oxidation prevention liquid for preventing the oxidation of an oxide of a Group III-V element or a treatment liquid for treating an oxide of a Group III-V element, each liquid including an acid and a mercapto compound; and a method using each of the same liquids. Further provided are a treatment liquid for treating a semiconductor substrate, including an acid and a mercapto compound, and a method for producing a semiconductor substrate product using the same.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: October 12, 2021
    Assignee: FUJIFILM Corporation
    Inventors: Satomi Takahashi, Seongmu Bak, Atsushi Mizutani, Tadashi Inaba
  • Patent number: 11124412
    Abstract: A manufacturing method for a micromechanical window structure including the steps: providing a substrate, the substrate having a front side and a rear side; forming a first recess on the front side; forming a coating on the front side and on the first recess; and forming a second recess on the rear side, so that the coating is at least partially exposed, whereby a window is formed by the exposed area of the coatings.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: September 21, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Joerg Muchow, Rainer Straub, Stefan Pinter
  • Patent number: 11120986
    Abstract: A method includes etching a first oxide layer in a wafer. The etching is performed in an etcher having a top plate overlapping the wafer, and the top plate is formed of a non-oxygen-containing material. The method further includes etching a nitride layer underlying the first oxide layer in the etcher until a top surface of a second oxide layer underlying the nitride layer is exposed. The wafer is then removed from the etcher, with the top surface of the second oxide layer exposed when the wafer is removed.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: En-Ping Lin, Yi-Wei Chiu, Tzu-Chan Weng, Wen-Zhong Ho
  • Patent number: 11114304
    Abstract: A substrate processing method includes providing a processing target substrate having a pattern, forming a film on the substrate, forming a reaction layer on a surface layer of the substrate by plasma, and removing the reaction layer by applying energy to the substrate.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: September 7, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takayuki Katsunuma, Toru Hisamatsu, Shinya Ishikawa, Yoshihide Kihara, Masanobu Honda, Maju Tomura, Sho Kumakura
  • Patent number: 11111414
    Abstract: A polishing composition having a pH of less than 7, comprising an abrasive grain and an amide compound, wherein the amide compound has a group forming a ? conjugated system with a carbonyl group.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: September 7, 2021
    Assignee: FUJIMI INCORPORATED
    Inventor: Yusuke Kadohashi
  • Patent number: 11107682
    Abstract: A method of patterning a substrate includes forming mandrels on a target layer of a substrate, the mandrels being comprised of at least two layers of material, the mandrels including a bottom layer comprised of a first material, and a top layer comprised of a second material, the target layer being comprised of a fifth material. The method includes forming sidewall spacers on sidewalls of the mandrels, the sidewall spacers comprised of a third material. The method includes depositing a fill material on the substrate that at least partially fills open spaces defined between the sidewall spacers, the fill material being comprised of a fourth material. The method includes executing a chemical-mechanical polishing step that uses the bottom layer of the mandrels as a planarization stop material layer, the chemical-mechanical polishing step removing the third material above a top surface of the bottom layer of the mandrels.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: August 31, 2021
    Assignee: Tokyo Electron Limited
    Inventor: Anton J. deVilliers
  • Patent number: 11094838
    Abstract: The present disclosure relates to a method for preparing nano-textured surface on single side of a silicon wafer, including the following steps: (1) superimposing two silicon wafers to obtain a first silicon wafer superimposition structure; the side on which the silicon wafers is superimposed is recorded as an attached surface, and the side exposed outside is recorded as an exposed surface; and (2) performing nano-textured surface etching on the first silicon wafer superimposition structure; and providing each silicon wafer with nano-textured surface on the exposed surface and a nano-textured surface etched strip on the edge of the attached surface. In the present disclosure, while the nano-textured surface etching is performed, the edge of the attached surface is etched with nano-textured surface by selecting a specific etching rate, which reduces the pulling force for detaching the wafers and reduces the fragmentation rate during the detaching process.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: August 17, 2021
    Assignees: CSI CELLS CO., LTD., CSI SOLAR POWER GROUP CO., LTD.
    Inventors: Shuai Zou, Xiaoya Ye, Fang Cao, Xusheng Wang, Guoqiang Xing
  • Patent number: 11094554
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a wafer over a polishing platen. The wafer includes a metal layer and a dielectric layer. The metal layer covers the dielectric layer and fills an opening of the dielectric layer. The method also includes polishing the wafer using a first operation to thin down the metal layer. The first operation has a first polishing selectivity of the metal layer to the dielectric layer. The method further includes polishing the wafer using a second operation to further thin down the metal layer until the dielectric layer is exposed. The second operation has a second polishing selectivity of the metal layer to the dielectric layer. The second polishing selectivity is different from the first polishing selectivity. The first operation and the second operation are performed in-situ on the polishing platen.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Ho Lin, Jen-Chieh Lai, Jheng-Si Su, Zhi-Sheng Hsu, Po-Ting Huang
  • Patent number: 11091401
    Abstract: Compositions and methods are presented that selectively dissolve calcium from a variety of cementitious materials without dissolving or otherwise degrading calcium silica hydrate (CSH). Preferably, contemplated compositions comprise guanidine bisulfate hydrochloride, which can be prepared from a reaction of urea, hydrochloric acid, and sulfamic acid. Therefore, it is especially contemplated that the compositions contemplated herein are particularly suitable to clean or otherwise condition surfaces of cured concrete, Portland cement-based material, or an aggregate containing CSH.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: August 17, 2021
    Assignee: PROTOCOL ENVIRONMENTAL SOLUTIONS, INC.
    Inventor: Sergio Vitomir
  • Patent number: 11075087
    Abstract: A method includes mounting a wafer on a chuck disposed within a chamber of an etching system, the wafer being encircled by a focus ring. While etching portions of the wafer, an etch direction is adjusted to a first desired etch direction by adjusting a vertical position of the focus ring relative to the wafer to a first desired vertical position. While etching portions of the wafer, the etch direction is adjusted to a second desired etch direction by adjusting the vertical position of the focus ring relative to the wafer to a second desired vertical position. The second desired vertical position is different from the first desired vertical position. The second desired etch direction is different from the first desired etch direction.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chi Lin, Chin-Hsing Lin, Hung Jui Chang, Yi-Wei Chiu, Yu-Wei Kuo, Yu Lun Ke
  • Patent number: 11072858
    Abstract: An injecting assembly includes a nozzle that is formed with a mixture channel, a mixture opening communicating with the mixture channel, a shaper channel, and a shaper opening communicating with the shaper channel. A mixture of a precursor and a supercritical fluid (SCF) passes through the mixture channel. Waves of the mixture are periodically injected toward a surface of a substrate at the mixture opening. A stream of a shaping fluid flows through the shaper channel and is injected toward the substrate at the shaper opening. The stream of the shaping fluid confines the waves of the mixture. Molecules of the precursor penetrate into the substrate by impact of the wave fronts reaching the surface of the substrate. The molecules of the precursor can react with molecules of a material of the substrate to improve surface properties of the substrate.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: July 27, 2021
    Assignee: Nova Engineering Films, Inc.
    Inventor: Sang In Lee
  • Patent number: 11069520
    Abstract: A substrate processing method includes: supplying a treatment liquid to a substrate held in a horizontal position; substituting the treatment liquid supplied to the substrate with a solvent having a lower surface tension than the treatment liquid; and drying the substrate by shaking off the solvent on the substrate at a preset rotation number so that an intermediate portion of the substrate located between a central portion and a peripheral portion of the substrate is last dried.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: July 20, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hiroyuki Suzuki
  • Patent number: 11062912
    Abstract: A process for etching a film layer on a semiconductor wafer is disclosed. The process is particularly well suited to etching carbon containing layers, such as hardmask layers, photoresist layers, and other low dielectric films. In accordance with the present disclosure, a reactive species generated from a plasma is contacted with a surface of the film layer. Simultaneously, the substrate or semiconductor wafer is subjected to rapid thermal heating cycles that increase the temperature past the activation temperature of the reaction in a controlled manner.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: July 13, 2021
    Assignees: Mattson Technology, Inc., Beijing E-Town Semiconductor Technology Co., Ltd.
    Inventor: Shawming Ma