Abstract: A data processor processes data strings from memory where the data strings do not begin or end at a memory boundary. A string is defined in memory by a starting address, a byte count defining the total number of bytes in the string, and a byte offset defining the position of the first byte in the starting address location. The processor stores the byte count and decrements the byte count as each multi-byte word is processed. A byte count mask circuit generates a byte count mask which has all 1s for each byte count greater than the number of bytes per memory word. When the number of bytes remaining to be processed is below the number of bytes in a memory word, the byte count mask generates 1s only for the positions corresponding to the positions of bytes of the string in the last memory word. An offset register stores the offset defining the position of the first byte in the first memory word of the string.

Abstract: A plurality of memory areas which store various type of information having different formats such as address information, schedule information, memo information in units of type of information are provided. Information stored in one of memory areas can be displayed on the display section by operating one of mode designate keys each of which corresponds to each information to select a function mode. Information stored in another of memory areas can be registered and/or retrieved by using a data item such as a person's name consisting of part of the designated information by operating a menu key and menu selection key, i.e., ten key during when the designated information is being displayed in a designated function mode.

Abstract: A computer system comprising a microprocessor architecture capable of supporting multiple processors. Data transfers between data and instruction caches, I/O devices, and a memory are handled using a switch network. Access to memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes. A test and set bypass circuit is provided for preventing a loss of memory bandwidth due to spin-locking. A row match comparison circuit is provided for reducing memory latency by giving an increased priority to successive requests for access to memory locations having the same row address. Dynamic switch/port arbitration is provided by changing device priority based on the intrinsic priority of the device, the number of times that a request has been serviced based on a row match, the number of times that a device has been denied service, and the number of times that a device has been serviced.

Abstract: In an automated factory environment which uses a plurality of stations, each having a communication device that incorporates the Manufacturing Message Specification (MSS) and is joined with other stations in a network that provides for communication using the Manufacturing Automation Protocol (MAP) communication, a method and apparatus for permitting programmed control of the plurality of stations on the basis of user-defined named variables, rather than specific vendor-defined device addresses is provided. A conversion table that has registered therein a correspondence between the named variable and an address for a specific device is used for control and communication. The table is loaded with appropriate address and named variable information by use of conventional program loading services provided in the MSS standard. The input may be from a remote station, from a management terminal or from a Factory Automation (FA) device.

Abstract: In a data processor including a serial interface, the serial interface internally includes a transmission end flag formed of a RS flipflop which set in response to the starting of the transmission of data of one byte and reset in response to completion of the transmission of the data of one byte. When the operation is changed from a macroservice processing for a serial data transmission to a vector interrupt processing, a CPU watches and discriminates the condition of the transmission end flag in a programmed operation of the CPU, thereby detecting a timing where data to be transmitted is transferred to a transmission shift register in the serial interface.

Abstract: A computer architecture has a plurality of processing cells interconnected to perform programming tasks. Each cell contains both memory and processing elements. Memory packets contain an instruction, a data element, and a pointer to another memory packet. Tasks are executed by following a linked list of memory packets. Transmission packets communicate instructions and register values along the linked list. A plurality of computer processes may be executed simultaneously.

Abstract: An interrupt steering control mechanism includes an interrupt target register storing a code identifying a particular interrupt target processor to receive undirected interrupts within a multiple processor computer system. The computer operating system assigns a particular processor to be a current interrupt target by writing the identifying processor code in to the interrupt target register. A system interrupt pending register permits any processor to ascertain whether an interrupt source has requested service. Each interrupt service request is assigned an interrupt priority determining when the particular processor will service the interrupt in relation to other interrupts pending for that processor. An interrupt target mask register permits the current interrupt target processor to delay service of the interrupt request until some later time, and any processor may assert ownership of the current interrupt target.

Abstract: A system for distributing processing between terminals (T.sub.1 .about.T.sub.n) connected via a communication network (30). Each terminal (T.sub.i) is provided with at least one method group (32) and a memory unit (34) to store data files. An originating terminal, e.g., terminal (T.sub.1) accesses data elsewhere in the distributed system by generating a message. The message includes a terminal code identifying an object to access a terminal (T.sub.2) to execute an object, a method code identifying a method for accessing the data and a command name containing or identifying the desired data. The terminal, e.g., terminal (T.sub.2), containing the desired data, decodes the message and accesses a data file in the memory unit (34) containing the desired data identified by the command name. The message may also include a selector and reset conditions which control the sequence of data processing in the terminals (T.sub.0 and T.sub.n) so that the processing of the originating (T.sub.1) and data accessing (T.sub.

Abstract: Deadlock detection and masking systems are incorporated into a bus coupler intercoupling at least two buses, wherein at least one master is coupled to each bus and at least one slave is coupled to at least one of the buses. The bus coupler also includes an arbiter coupled to the buses to determine which master may control each bus. The deadlock detection system detects a potential arbitration deadlock condition between two master devices seeking control of a bus and access to a slave. Once a potential arbitration deadlock is detected, the masking system is activated to prohibit the second master from gaining control of the second bus for a random period of time. The random time delay acts as a mask to provide the first master device an opportunity to reaccess the slave device and avoid the deadlock situation. By providing a random masking period complementary, synchronized arbitration deadlocks are avoided.

Abstract: An arrangement is provided which enables one or more controllable pieces of equipment to be controlled by a control unit. Each piece of controllable equipment includes a control structure definition for that equipment. The controllable equipment is responsive to a request from the control unit to supply the control structure definitions to the control unit where it is used for programming that control unit. The control unit has a number of user operable input devices, at least some of which are programmable, and a programmable display. The control unit responds to an initial operation (e.g. an initial operation of one of the input devices) to transmit a message to the controllable equipment requesting the control structure definitions for programming the display and/or the input devices. The control unit responds to a message from the controllable unit to carry out the programming.

Abstract: A protection system for a computer is provided. This system is essentially based on the provision of an EEPROM (20) of unstandard access and containing configuration data of the computer as well as a password. As power-on, the contents of the EEPROM except eventually the password, are copied into a CMOS memory (16) which must conventionally be present in the computer. The invention eventually provides additional circuitry for irreversibly cutting the access to the EEPROM and specified peripheric devices.

Abstract: A priority encoder which, when an instruction for transferring a plurality of register contents is executed, encodes two or more register addresses to which the contents are to be transferred from a register list, and a data processor capable of transferring two or more register contents simultaneously by comprising the same,

Abstract: A bus architecture includes address lines, data lines, and control signals to allow a processor to communicate with a VLSI gate array. The address lines are interpreted by the VLSI gate array to select either multi-bit registers or single bit designators resident on the VLSI gate array depending on which control signal is received from the processor. Dual address decode logic on the VLSI gate array senses control signals indicating a request to read from a register, write to a register, and set, clear, or test a designator, and decodes the address received to select the appropriate storage location for the requested function.

Abstract: A network of digital modules having store-through and non-store-through cache memories, is provided with intercommunication capability by means of two sets of system busses each of which are replicates of each other. The system busses provide a higher throughput by both being available to each of the digital modules so that a requesting digital module can alternately use a second system bus if the first system bus happens to be busy. Failure of one system bus will allocate transmission service to the second operating system bus thus providing redundancy. Alternatively, each of the system busses can be isolated for partitioning the digital modules into two different operating systems which are independent of each other.

Abstract: A computer system having a bus connection and disconnection unit for connecting and disconnecting an ISA bus to and from a slave bus, the ISA bus being connected to a main processor. The slave bus is connected with a bus master. When accessing a device on the slave bus, the bus master requests the bus connection and disconnection unit to disconnect ISA bus from the slave bus. This allows the main processor to perform other processing without getting put on hold.

Abstract: An asynchronously concurrent matrix macroprocessor that consists of a substrate on which is carried an extended set of parallel-wired buses. An indefinitely large multi-dimensional rectangular array of substantially identical large scale integrated solid-state electronic modules each containing a plurality of ALUs are mounted on the substrate and communicate with each other via said extended set of parallel wired buses. The modules are located at the intersection nodes of said rectangular array with the set of parallel wired buses constituting congruent data and address buses. A control generates a unique location address for each node in the array, and a unique identifying address for each segment of external input data. A switch is contained in each module located at each node in the array for interconnecting data and address buses to route the information from a source node in the array to a target node.

Abstract: An optimized high-speed sorter has a plurality of process elements connected in series. Each process element includes a sorting unit used to store a sorted item, and a comparing/controlling unit coupled to the sorting unit. In this sorter, all sorted items are compared with the input item simultaneously, and then are divided into an LE-group wherein the sorted items are less than or equal to the input item, and a G-group wherein the sorted items are greater than the input item. We assume that the sorted items are arranged in a descending sequence from left to right. In the insertion operation, the sorted items in the LE-group are shifted rightwards simultaneously, and the input item is loaded in the position between the LE-group and G-group. In the deletion operation, only the sorted items in the LE-group are shifted leftwards simultaneously. In order to accelerate the operation speed, the sorter adopts a pre-shift strategy.

Abstract: A network management system includes a user interface, a virtual network and a device communication manager. The virtual network includes models which represent network entities and model relations which represent relations between network entities. Each model includes network data relating to a corresponding network entity and one or more inference handlers for processing the network data to provide user information. The system performs a fault isolation technique wherein the fault status of a network device is suppressed when it is determined that the device is not defective. User displays include hierarchical location views and topological views of the network configuration. Network devices are represented on the displays by multifunction icons which permit the user to select additional displays showing detailed information regarding different aspects of the corresponding network device.

Abstract: A shift circuit 213 used in arithmetic operations is provided with the shift width generating circuit 217 which generates a shift width data from lower bits of an access address and an access size, and a circuit is provided to generated data comprising the first select output circuit 214, the third select output circuit 216 and the like which generate a data by merging byte by byte selected from either an output of the shift circuit 213 or a value of a register of a register file 210 according to the combination of the lower bits of the access address and the access size. It is possible to align the data in the shift circuit 213 which is provided for the purpose of arithmetic operations, and exclusive alignment circuit is made unnecessary thereby enabling it to reduce the amount of hardware.

Abstract: A communications system for transmitting data utilizes one or more picoprocessors located logically out of the main data path for conducting calculations and control functions in a fashion which is decoupled or separate from the main data path. In particular, the system utilizes multiple picoprocessors for performing buffer management and high performance buffer chaining processes out of the main data path so that the main data path may be continually used in parallel. In this manner, data transfer is enhanced by offloading functions and responsibilities from the main system processor and removing unnecessary traffic from the main data path.