Abstract: A single-chip video compression/decompression (video codec) chip is connected to receive a video input from a NTSC-compatible or PAL-compatible camera and a transmit channel. Video information from the camera or other video input source is compressed by the video codec and transmitted out in compressed form on a transmit channel. Concurrently, compressed video information is input to the video codec from a receive channel, decompressed and output to the monitor or other video output device, e.g., a television set. Only a separate single module of dynamic random access memory (DRAM) is needed to provide storage for incoming and outgoing video data, compressed bit streams and reconstructed pictures for both compression and decompression procedures. The compression of video information is by spatial decorrelation of the intraframe information, and temporal decorrelation of the interframe information. The communication channel bit rate is further reduced by quantization and variable length coding.

Abstract: An asynchronous transfer mode LAN switching hub device using IEEE P1355 system and its control method.

Abstract: An interconnect mechanism for allowing use of an IDE compatible add-in card in a PCI compliant expansion slot. Unused PCI pins are exploited to provide for proper routing of necessary interrupt signals from an IDE add-in card. The presence of the IDE card in the PCI slot enables signaling circuitry for routing IDE interrupts to the computer system's interrupt controller and reroutes existing hard disk interrupt signals to the interrupt controller as a secondary hard disk interrupt. Another otherwise unused pin is exploited to provide a signal for lighting the computer system's hard disk active indicating LED. The gating circuitry is provided such that non-IDE, PCI-compliant add-in cards are provided with unaffected operation in the PCI slot.

Abstract: A computer system including separate digital and analog system chips which provides increased performance over current computer architectures. The computer system of the present invention includes a digital system chip which performs various digital functions, including multimedia functions and chipset functions, and a separate analog chip which performs analog functions, including digital to analog and analog to digital conversions. Thus the present invention optimizes silicon use and design by splitting up digital and analog functions on separate chips. The system of the present invention also separates digital noise from analog noise, allowing a higher degree of integration while increasing stability.

Abstract: A data transfer control device comprises an instruction storage units and for storing a data transfer instruction, an instruction decoding unit for reading the data transfer instruction from the instruction storage units and to decode the content thereof, a shared memory access unit for reading and writing the data through access to a shared memory in the same cluster, a data transfer unit for sending the data to a network among clusters and receiving the data from the network among clusters and a transfer control unit for controlling the shared memory access unit and the data transfer unit according to the data transfer instruction decoded by the instruction decoding unit, as well as for storing the data transfer instruction issued from another cluster into a second instruction storage unit when the data transfer unit receives the data transfer instruction from another cluster through the network among clusters.

Abstract: A digital signal processor (DSP) comprises a condition flag register directly accessible by the control microcomputer. Referring to a condition flag of the condition flag register every sampling period of the DSP, the DSP can change the content of a process every sampling period in accordance with the set status of the condition flag. The DSP sets the condition flag in the condition flag register at the beginning of a sampling period of the DSP by a set instruction, and resets the condition flag at the end of a sampling period by a reset instruction. The DSP may be modified to automatically reset the condition flag at the end of the sampling period in which the condition flag has been set.

Abstract: A computer system is described with a 32 bit arithmetic and logic unit which is coupled to a 64 bit data bus. A number of general purpose registers are provided which have 32 bits each and which are organized in two groups. Two 32 bit data words which are present on the data bus can be transmitted and stored in the two groups of the general purpose registers. From there, the two data words can be transmitted via two operand registers to the arithmetic and logic unit. Several further lines are provided for bypassing the general purpose registers and/or the arithmetic and logic unit, if desired. Due to the fact that two data words can always be transmitted, the performance of the computer system is enhanced.

Abstract: A data processing apparatus is provided which includes an instruction decoder, an input circuit, an input selecting circuit, a plurality of arithmetic logic circuits, an output selecting circuit, and an output circuit. The input circuit receives input data to provide a plurality of data signals. The input selecting circuit selects the data signals to distribute each of them to corresponding one of the arithmetic logic circuits according to a command from the instruction decoding circuit. The arithmetic logic circuits receive the data signals to perform arithmetic and logic operations and to provide operation output signals indicative of results of the arithmetic and logic operations. The output selecting circuit selects the operation output signals to distribute each of them to a given location of the output circuit. This architecture of the data processing apparatus allows a plurality of arithmetic and logic operations to be executed at high speed using the single input and output circuits.

Abstract: An output apparatus and method controls a combination of a plurality of font data stores and a plurality of conversion methods for converting font data to dot pattern data in accordance with a condition of a using right of a print data processing unit and a bit map pattern producing unit.

Abstract: A data processor transfers files at high speeds from a magnetic disk or other storage media to a network and shortens the processing time for the file transfers. An I/O processor includes (i) a channel to which a magnetic disk is connected, (ii) a LAN adapter to which a network is connected, (iii) a switch for switching and connecting the channel and LAN adapter, and (iv) a channel controller for controlling the channel, the LAN adapter, and the switch. The channel controller controls the channel, the LAN adapter, and the switch in accordance with a data transfer start instruction from an instruction processor. The channel reads data from the magnetic disk and transfers it to the LAN adapter via the switch. The LAN adapter sends the data to the network or reads data from the network and transfers it to the channel via the switch. The channel sends the data to the magnetic disk.

Abstract: An integrated circuit (110) includes, on a single chip, distinct supply voltage terminals and internal on-chip supply conductors connected respectively thereto, including a ground terminal (GND) and terminals for first and second supply voltages (VCC3, VCC5), and a terminal for a selectable supply voltage (VCCDK) and also has a power-good terminal (PWRGOOD5). A plurality of peripheral control circuits (910, 938, 932) are connected by an on-chip internal bus (904). The peripheral control circuits (910, 938, 932) connect to different ones of the internal on-chip supply conductors for operation on the first and second supply voltages (VCC3, VCC5), and the selectable supply voltage (VCCDK). Reset circuitry (2390) is provided for at least one of the peripheral control circuits. A control latch (PMU.sub.-- CNTRL) has a bit (VCCDRV5V) to which the reset circuitry (2390) is responsive.

Abstract: A method and system for mapping a node topology is disclosed. The node topology is based on a computer system comprised of a high performance acyclic serial bus and a plurality of nodes coupled to the acyclic serial bus. Each node further includes an identification packet. The mapping topology establishes a root node based upon information found in each identification packet and establishes at least one branch node among the nodes based on the information. Next, the topology mapping method selects a first available branch node among the available branch nodes based on the information. The system then identifies any of the nodes that are child nodes to the first available branch node. Upon identifying all child nodes of the branch node, the system selects a next available branch node based upon the information. The processing continues until the root node is processed as a branch node.

Abstract: A SCSI computer system is provided whereby a host computer gains access to a targeted but non-local peripheral device, which device or devices are individually responsive to either SCSI or non-SCSI commands, by sending SCSI commands via a SCSI bus to a connected SCSI target computer which emulates the targeted peripheral device local to the SCSI target computer, whether the targeted peripheral device is responsive to only SCSI or only non-SCSI commands, to cause the targeted peripheral device to carry out the initial SCSI commands.

Abstract: A computer system comprising a plurality of caching agents with a cache hierarchy, the caching agents sharing memory across a system bus and issuing memory access requests in accordance with a protocol wherein a line of a cache has a present state comprising one of a plurality of line states. The plurality of line states includes a modified (M) state, wherein a line of a first caching agent in M state has data which is more recent than any other copy in the system; an exclusive (E) state, wherein a line in E state in a first caching agent is the only one of the agents in the system which has a copy of the data in a line of the cache, the first caching agent modifying the data in the cache line independent of other said agents coupled to the system bus; a shared (S) state, wherein a line in S state indicates that more than one of the agents has a copy of the data in the line; and an invalid (I) state indicating that the line does not exist in the cache.

Abstract: A microcomputer including an EEPROM in which data may be stored and from which stored data may be read either under control of a central processing unit of the microcomputer or under direct external control. The microcomputer includes separate inputs for data input and data output signals when storing and reading is under the control of the central processing unit and when storing and reading of data is under direct external control. The central processing unit may inhibit direct external control of storing data in and reading data from the EEPROM.

Abstract: A method of detecting anomalous overflow conditions is used, in an exemplary embodiment, in implementing in a 486-type microprocessor, nonrestoring two's complement division for negative quotients using 2n bit dividends and n bit divisors. Each interative division step, an adder/subtractor is used to add/subtract the properly aligned divisor to/from the left shifted dividend, to produce a partial remainder and a carry out bit Cout. Complement Cout is assumed to be the same as the most significant bit of the partial remainder PR(MSB), such that PR(MSB) is used as the sign bit in further computations, with complement Cout being used to control quotient generation according to DVRS XOR Cout. The anomalous overflow test signals overflow when complement Cout is the different than the most significant bit of the first partial remainder PR1(MSB), such that the anomalous overflow test is implemented according to the logic equation: Cout XNOR PR1(MSB).

Abstract: In a system including a controller and peripherals connected to the controller, a plurality of statuses represents states of each of the peripherals. Most general statuses useful for controlling the peripheral are taken as statuses in a highest layer of a tree structure, and it is branched to statuses of lower layers successively. When a signal of a certain status, which has no lower statuses which branches further therefrom, signals of the statuses between the certain status and the most general status relevant to the certain status are changed successively. Simultaneously, the information of the statuses on which the signals are changed is transmitted to a controller. Thus, the status information can be transmitted surely to the controller.

Abstract: A data processing system providing an extensible register and method thereof. A new CPU has an extensible index register. The new CPU is object code compatible with the old CPU having an 8-bit index register, yet the index register of the new CPU can be effectively extended to 16 bits when new instructions are used. As a consequence, the user is able to make the choice between using assembly code software written for the old CPU and having the functionality of an 8-bit index register, or writing new assembly code software for the new CPU and having the functionality of a 16-bit index register.

Abstract: A method and device for generating the Grobner bases to reduce the memory usage and compute at a high speed. The method comprises the steps of a) selecting a prime number, b) computing the normalization format of the polynomial pair regarding p as the modulus, c) computing the normalization format on the rational number only when the normalization format in the modulus p is not 0, d) omitting the computation of the normalization format on the rational number regarding the normalization format on the rational number as 0, when the normalization format in the modulus p is 0, and e) obtaining the polynomial set F.sub.1 which is the Grobner basis candidate. Thus, the digits of the intermediate formula are reduced, the memory usage is saved and the computing speed is accelerated. It is also possible to execute the computing after homogenizing previously the polynomial set F which is an object and dehomogenizing it at the end.

Abstract: A vector processor including a vector register having a plurality of banks storing a plurality of elements of data, a plurality of vector operation units to perform a plurality of vector operations on the plurality of elements of data, a single mask register to store mask data indicating whether to mask the elements of data and controlling the vector operations performed on the elements of data by the plurality of vector operation units, a single decoder device, connected to the mask register, for generating a read address and a write address of the mask register, a serial-to-parallel converting device for receiving serial mask data from a second bus connected to the plurality of vector operation units, for converting the serial mask data into parallel mask data, and for writing the parallel mask data into the mask register at the write address generated by the decoder device, and a parallel-to-serial converting device for reading parallel mask data from the mask register at the read address generated by the