Patents Examined by E. Anderson
  • Patent number: 12256870
    Abstract: A utensil crock includes a receptacle having a base and a sidewall defining an open upper end of the receptacle. A dividing panel IS adapted to be removably positioned within an interior of the receptacle to divide the interior into separate compartments. The dividing panel has a first end portion opposite a second end portion, wherein when positioned in the interior the dividing panel has one of a first configuration where the second end portion has a first orientation relative to the first end portion, and a second configuration where the second end portion has a differing second orientation relative to the first end portion.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: March 25, 2025
    Assignee: HELEN OF TROY LIMITED
    Inventors: Carly Cheng, Kristopher Blake Wagner, Martin Mutch
  • Patent number: 12252335
    Abstract: A set of moulded panels, which can be assembled together to form a storage container for an automated storage and retrieval system, includes a rectangular base panel and four side panels. The base panel is moulded with a perimeter profile. Each of the side panels is moulded with a lower edge profile. The lower edge profiles of each side panel are slidingly engaged with the perimeter profile during assembly of the storage container. Each of the side panels are moulded with side edge profiles, which are to be slidingly engaged with the side edge profiles of adjacent side panels during assembly of the storage container.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: March 18, 2025
    Assignee: AutoStore Technology AS
    Inventor: Trond Austrheim
  • Patent number: 12246905
    Abstract: A soft-sided cooler includes a flexible exterior shell, and a lower frame member secured to the upper edge of the exterior shell. A lid is pivotally mounted on the lower frame member with at least one hinge. A latch is mounted on the lower fame member, opposite from the hinge. The surface of at least one of the lid or the upper frame member smoothly slope outwardly toward the other then inwardly away from the other on either side of the latch, peaking at a point intermediate the latch and the hinge, to increase the sealing force between the lid and the upper frame one each side of the cooler, between the latch and the at least one hinge.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: March 11, 2025
    Assignee: Bass Pro Intellectual Property, L.L.C.
    Inventors: Ronald D. Nelson, David P. Leif, Lucas C. Humphreys
  • Patent number: 12234948
    Abstract: A pressure vessel assembly includes a pressure vessel including a cylinder, a first side dome provided at one end of the cylinder, and a second side dome provided at the other end of the cylinder, a first protector that surrounds an outer surface of the first side dome, a second protector that surrounds an outer surface of the second side dome, and a connector that connects the first protector and the second protector such that the pressure vessel is interposed between the first protector and the second protector. The pressure vessel assembly can help to prevent damage and breakage of the pressure vessel caused by external impact and improve safety and reliability of the pressure vessel.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: February 25, 2025
    Assignees: Hyundai Motor Company, Kia Corporation
    Inventors: Seon Woo Yoo, Cheol Hwan Kim
  • Patent number: 12222069
    Abstract: A high-pressure hydrogen tank includes a metal circular cylinder configured to store high-pressure hydrogen therein, a cap part configured to cover each of opposite end portions of the metal circular cylinder, an outer cylinder surrounding an outer periphery of a circular-cylindrical portion of the metal circular cylinder, and a fastening part configured to fix the cap part to the outer cylinder.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: February 11, 2025
    Assignee: JFE STEEL CORPORATION
    Inventors: Toshio Takano, Hiroshi Okano, Akihide Nagao, Nobuyuki Ishikawa, Kazuki Matsubara
  • Patent number: 12209705
    Abstract: An organic composite gas storage tank 300 comprises a hollow central portion 306 which is substantially cylindrical and formed integrally with first and second end portions 302, 304, and which defines a longitudinal tank axis 301. The first end portion comprises a hollow truncated conical region which meets the hollow central portion at a first end thereof. The hollow central portion comprises first and second hollow truncated conical portions 306A, 306B, the external radius of a given hollow truncated conical portion decreasing in a direction towards a corresponding end portion. The tank comprises an organic composite fibre winding extending between first and second positions along the length of the tank which coincide with the first and second hollow truncated conical portions of the hollow central portion respectively, biassing these portions together and increasing the axial strength of the central portion.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: January 28, 2025
    Assignee: ROLLS-ROYCE plc
    Inventor: Eric W Dean
  • Patent number: 10137391
    Abstract: A filtration vessel is provided with improved sealing surfaces and alignment methods. The sealing surface is provided by a perforated sleeve within the filtration vessel. An alignment mechanism is provided which allows for improved servicing of the filtration vessel.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: November 27, 2018
    Assignee: PECOFacet (US), Inc.
    Inventors: David J. Burns, Daniel M. Cloud, Tyler Glenn Boswell, Artimus Charles Jones
  • Patent number: 5494297
    Abstract: A lacrosse stick head comprising a frame and netting attached to the frame. The frame has two sidewalls extending from a throat portion to a mouth portion thereof. Each sidewall includes an upper wall section and a lower section having an inner wall segment, that extends inwardly towards the central longitudinal axis of the frame, and an outer wall segment that extends downwardly from the upper wall section. The inner wall segment is shorter than the outer wall segment and spaced a selected distance away from the mouth portion. Each outer wall segment has a bottom edge with holes therein, these holes being provided to attach the netting. In a preferred version, there are several side-by-side holes arranged in a row along one or both sides of a shank end portion of the head. These holes are used to secure and adjust several longitudinal thongs of the netting.
    Type: Grant
    Filed: August 2, 1994
    Date of Patent: February 27, 1996
    Inventor: Ronald J. MacNeil
  • Patent number: 5349692
    Abstract: An computer program instruction sequence control system to allow parallel or simultaneous execution of instructions. The system begins by loading two instructions for sequence determination. The system then checks if either instruction reads from or writes into the other instruction, if both instructions reference the same address, or if either instruction will contend with a currently executing instruction for the registers, arithmetic unit, or main memory. If no interference occurs, both instructions will be issued in parallel or simultaneously.
    Type: Grant
    Filed: June 7, 1993
    Date of Patent: September 20, 1994
    Assignee: NEC Corporation
    Inventor: Naoki Nishi
  • Patent number: 5349686
    Abstract: A programmable element sequence selection circuit which selects a repeatable sequence of elements from a plurality of elements is provided. The sequence selection circuit includes a sequence storage circuit into which a sequence of element identifiers is loaded and accessed.
    Type: Grant
    Filed: July 14, 1992
    Date of Patent: September 20, 1994
    Assignee: MTI Technology Corporation
    Inventors: Kumar Gajjar, Anh Nguyen
  • Patent number: 5335339
    Abstract: An equipment for displaying a specification of behavior of a real time system includes a program memory for storing a plurality of program objects for simulating operations of objects indicative of an arrangement of the real time system and a plurality of graphical symbol objects for expressing operational states of the objects and relationships between the objects in the form of a graphical symbol representation on a display screen. In the equipment, the plurality of program objects are linked with the plurality of symbol objects through an inter-program communication control routine. Each of the program objects, when receiving a message from the communication control routine, is executed for simulation operation according to the received message to thereby generate a new message to be sent to the associated program routine and a new message indicative of an object state change to be sent to one of the symbol objects corresponding to the associated object.
    Type: Grant
    Filed: November 18, 1991
    Date of Patent: August 2, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Yukihito Maejima, Toko Ohtsubo, Mitsuyuki Masui, Noriyuki Abe, Katsuhiko Yuura, Kenji Mochizuki
  • Patent number: 5335327
    Abstract: A disk unit control apparatus (DKC) comprises a cache memory provided between a CPU and an external memory (DKU) storing the information exchanged with the CPU, the cache memory holding temporarily copies of the information stored in the DKU. A request from the CPU for access to the information stored in the DKU is met as far as possible by use of the information held in the cache memory. First transfer routes of information between the CPU and the cache memory is greater in number than second transfer routes of information between the cache memory and the DKU. This makes it possible that even when direct accesses to the DKU in the same number as the second transfer routes occur in each of the first transfer route, accesses to the cache memory which may arise from other CPUs are capable of being effected through the remaining ones of the first transfer routes.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: August 2, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Kiyoshi Hisano, Ken Hirashima, Hiroyuki Kurosawa, Kenji Kubota, Shuji Sugimoto
  • Patent number: 5327564
    Abstract: A system for protecting data in a CPU's internal register. To obtain write access to the protected register, a process must sequentially write first and second keywords to an access register, within a predetermined time window.
    Type: Grant
    Filed: June 13, 1991
    Date of Patent: July 5, 1994
    Assignee: Dallas Semiconductor Corporation
    Inventor: Wendell L. Little
  • Patent number: 5327579
    Abstract: A scanning system using tree structures is constituted by a propagation operating unit array having a tree structure in which propagation units are formed into groups on each layer, and each group of the propagation operating units is connected to a propagation operating unit belonging to the higher adjacent layer, and an interface element array connected to the propagation operating units of the lowermost layer. Each of the propagation operating units is constituted by a plurality of cascaded propagation elements. Each propagation element includes first and second selectors for selecting input signals DA.sub.i and DB.sub.i from the lower adjacent layer in accordance with two propagation signals from the immediately forwarding propagation element and a third selector for selecting two propagation signals from an adjacent propagation element in accordance with an input signal U from the upper adjacent layer.
    Type: Grant
    Filed: November 16, 1993
    Date of Patent: July 5, 1994
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventor: Tosio Kondo
  • Patent number: 5317700
    Abstract: A program history (P-history) listing of branch-type instruction addresses for pipelined data processing system that employs one or more pipelined processors is stored in a random access memory (RAM) which is also used to store other executive or task information. A set of three queue registers is used to respectively store, 1) the absolute "to" address to which a branch instruction will jump, 2) the relative "to" address, to which the branch instruction will jump, and 3) the relative "from" address, from which the branch instruction will jump. The queues allow the storage of the P-history in the RAM without interference with the use of the RAM by the other functions that access it and without interruption of the pipelined processor.
    Type: Grant
    Filed: May 1, 1992
    Date of Patent: May 31, 1994
    Assignee: Unisys Corporation
    Inventors: Gregory F. Hammitt, Scott D. Koenigsman
  • Patent number: 5317757
    Abstract: A common set of building block action modules perform specific tasks in the finite state machine and are strongly modular in structure. The set of building block action modules can be made up of modules for tasks generic to resource type and modules that are resource type independent. A finite state machine is created for each resource type to govern the steps of activation and deactivation of the resource. Each finite state machine, uniquely defines the new state and action processing for each resource type. To tie the building block action modules to each finite state machine, action vectors are created for each resource type. The action vector correlates a particular action selection by the finite state machine to the dispatching of one or more building block action modules. An action vector can contain a plurality of elements. Each of these elements identifies an action module to which control is passed and a function request pointer.
    Type: Grant
    Filed: February 6, 1992
    Date of Patent: May 31, 1994
    Assignee: International Business Machines Corporation
    Inventors: John A. Medicke, Paul Posharow
  • Patent number: 5303350
    Abstract: A circuit for initializing a D-latch of an input/output system. The circuit comprises first and second logic means, the first logic means generating an enable signal coupled to the clock input of the D-latch which changes state from inactive to active at a first time t1 and again at a subsequent time t2, in response to the system write control signal addressed to the D-latch and the system reset signal. The second logic means generates a local data signal, in response to the system reset signal and system data signal, to the data input of the D-latch. The D-latch is reset substantially at time t1 and the system data signal is strobed in the D-latch substantially at time t2.
    Type: Grant
    Filed: December 20, 1990
    Date of Patent: April 12, 1994
    Assignee: Acer Incorporated
    Inventors: Chieh-Chih Yu, Hugn-Chyuan Hsieh
  • Patent number: 5301303
    Abstract: A local net area network, or LAN, configuration is provided with a multiple generic LAN channel architecture which can be logically and dynamically changed. The configuration control can be applied to each module of the network and to each port of a module of a LAN hub. The architecture provides multiple LAN protocols to be used simultaneously, as needed, through protocol specific functions. Industry standard protocol such as: token bus, token ring, and fiber distributed data interface (FDDI), can be implemented using the generic channel architecture and its characteristics providing respective network functions. The architecture also provides a digital collision detection method and provides information necessary for precise network statistics monitoring. The token passing ring architecture provides a logical ring formation within the generic channel. A token passing bus architecture uses modified Ethernet.TM.
    Type: Grant
    Filed: April 16, 1991
    Date of Patent: April 5, 1994
    Assignee: Chipcom Corporation
    Inventors: Menachem Abraham, David Bartolini, Samuel Ben-Meir, Ilan Carmi, John L. Cook, III, Ira Hart, Alex Herman, Steven E. Horowitz, Yongbum Kim, Yoseph Linde, Brian Ramelson, Richard Rehberg, Gordon Saussy, Yuval Shohet, Igor Zhovnirovski
  • Patent number: 5283877
    Abstract: A data processing system includes a processor coupled to a system bus. A memory controller is also coupled to the system bus and to a memory bus in communication with a plurality of single in-line memory modules (SIMMs). Each SIMM comprises a plurality of DRAMS coupled to four cross bar switches (CBSs), such that address and data information is provided to the DRAMs through the cross bar switches. Each CBS includes a counter and decoder which controls a multiplexor. The multiplexor is coupled to enable ID logic, and four input registers (A.sub.R, B.sub.R, C.sub.R, D.sub.R), such that register A.sub.R is coupled to the output of the multiplexor, and the remaining registers are coupled to the input side of the multiplexor. An input buffer on the CBS is coupled to four input registers (A'.sub.W, B'.sub.W, C'.sub.W, D.sub.W). In addition, three of the input registers (A'.sub.W, B'.sub.W, C'.sub.W) are coupled to intermediate input registers A.sub.W, B.sub.W and C.sub.W.
    Type: Grant
    Filed: July 17, 1990
    Date of Patent: February 1, 1994
    Assignees: Sun Microsystems, Inc., Xerox Corporation
    Inventors: Jean A. Gastinel, Shen Wang, Stan Graham, Fred Cerauskis, Gil Chesley
  • Patent number: 5283889
    Abstract: A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer. In one embodiment of the invention, a System Control Processor Interface (SCPI) is provided between the central processing unit (CPU) and the system control processor (SCP) to maintain compatibility with the PC/AT bus. The combination of the faster SCP and the SCPI interface improves the overall system performance. Control circuitry is also provided for setting the A20 signal relatively quickly to allow memory access above one megabyte. In an alternate embodiment of the invention, a Mouse Keyboard Interface (MKI) is provided. The MKI provides even quicker switching of the Gate A20 signal by eliminating the need to interrupt the SCP. The MKI also provides support for a type PS/2 mouse.
    Type: Grant
    Filed: March 11, 1993
    Date of Patent: February 1, 1994
    Assignee: Zenith Data Systems Corporation
    Inventors: David J. DeLisle, Saifee Fakhruddin, Lloyd Gauthier, Robert A. Kohtz