Abstract: Three-dimensional diode arrays have been produced in semiconductor wafers by a two-step process involving laser drilling and solid-state diffusion.Holes are first produced in the wafer in various arrays by laser drilling. Under suitable conditions, laser drilling causes little or no damage to the wafer. Cylindrical P-N junctions are then formed around the laser-drilled holes by diffusing an impurity into the wafer from the walls of the hole. A variety of distinctly different ISFET devices is produced.

Abstract: A semiconductor element having a main part of a polycrystalline silicon semiconductor layer containing 0.01 to 5 atomic % of chlorine atoms.

Abstract: One or more silicon-integrated-circuit chips are attached, active side up, to the bottom side of a silicon wafer. A sloped-wall through-aperture is etched in the wafer in registry with a portion of the active side of each attached chip. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped walls to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.

Abstract: A thin film insulated gate field effect transistor having an opposite conductivity type island in its channel region. The island is electrically shorted to the transistor gate electrode.

Abstract: Three-dimensional diode arrays have been produced in semiconductor wafers by a two-step process involving laser drilling and solid-state diffusion.Holes are first produced in the wafer in various arrays by laser drilling. Under suitable conditions, laser drilling causes little or no damage to the wafer. Cylindrical P-N junctions are then formed around the laser-drilled holes by diffusing an impurity into the wafer from the walls of the hole. A variety of distinctly different ISFET devices is produced.

Abstract: A combined lateral MOS/bipolar transistor includes an intermediate semiconductor layer of the same conductivity type as the channel region which extends laterally from the channel region to beneath the drain contact region of the device. Additionally, a floating semiconductor layer of opposite conductivity type to that of the channel region is provided between the intermediate layer and the substrate of the device. Both the intermediate layer and the substrate are relatively lightly doped, to effectively isolate the floating layer from above and below. This structure substantially improves the operating chartacteristics of the device, thus permitting operation in both the source-follower and common-source modes, while also providing a compact structure which features a relatively low normalized "on" resistance.

Abstract: An MOS device having a gate electrode and interconnect of titanium nitride and especially titanium nitride which is formed by low pressure chemical vapor deposition. In a more specific embodiment the titanium nitride gate electrode and interconnect have a silicon layer thereover to improve oxidation protection.

Abstract: A protection element responsible for protecting a semiconductor element included in a semiconductor device from a voltage higher than the voltage which the semiconductor element is allowed to receive, the protection element virtually being a lateral bipolar transistor, in which an improvement is made to increase the voltage at which the protection element operates. The improvement being realized by separating the emitter from a region containing an impurity at a high concentration and which is a portion of the base of the lateral bipolar transistor.

Abstract: Three-dimensional diode arrays have been produced in semiconductor wafers by a two-step process involving laser drilling and solid-state diffusion.Holes are first produced in the wafer in various arrays by laser drilling. Under suitable conditions, laser drilling causes little or no damage to the wafer. Cylindrical P-N junctions are then formed around the laser-drilled holes by diffusing an impurity into the wafer from the walls of the hole. A variety of distinctly different ISFET devices is produced.

Abstract: Information storage medium comprising a semiconductor doped with first and second impurities or dopants. Preferably, one of the impurities is introduced by ion implantation. Conductive electrodes are photolithographically formed on the surface of the medium. Information is recorded on the medium by selectively applying a focused laser beam to discrete regions of the medium surface so as to anneal discrete regions of the medium containing lattice defects introduced by the ion-implanted impurity. Information is retrieved from the storage medium by applying a focused laser beam to annealed and non-annealed regions so as to produce a photovoltaic signal at each region.

Abstract: By the use of high-ohmic polycrystalline silicon (poly) in MIS elements, a depletion layer can be formed in the poly material which brings about an electric decoupling between the poly (gate) and the underlying semiconductor body. This effect can be utilized advantageously in various circuit elements, such as in CCD's, in order to obtain a favorable potential distribution in the substrate; in MOS transistors in order to reduce the parasitic capacities; and in high-voltage devices in order to increase the breakdown voltage at the edge of the field plate (resurf).

Abstract: By the use of high-ohmic polycrystalline silicon(poly) in MIS elements, a depletion layer can be formed in the poly material which brings about an electric decoupling between the poly (gate) and the underlying semiconductor body. This effect can be utilized advantageously in various circuit elements, such as in CCD's, in order to obtain a favorable potential distribution in the substrate; in MOS transistors in order to reduce the parasitic capacities; and in high-voltage devices in order to increase the breakdown voltage at the edge of the field plate (resurf).

Abstract: A diode structure is disclosed wherein the diode includes a body of a first type conductivity material; a first region of a second conductivity material in the body and having an opening therein through which a portion of the body projects; and a second region of the first conductivity material in the portion of the body that projects through the opening. The second region is rotationally positioned with respect to the first region so that it partially overlaps the first region at points of intersection of the two regions. These points of intersection are the rectifying junctions. The respective shapes of the opening and of the second region are arranged so that the sum of the areas of the breakdown junctions is a constant value notwithstanding that the second region may be displaced or misaligned with respect to the first region, provided that relative displacement or misalignment of the two regions is within defined limits.

Abstract: A semiconductor integrated circuit device is disclosed. A plurality of unit cells, each having at least a basic transistor device formed on one main surface of a semiconductor substrate, are arranged in a line to form a unit cell line. At least two of such unit cell lines are arranged adjacent to and in parallel with each other to form a basic cell line. A plurality of such basic cell lines are arranged in parallel with each other with a wiring region of a predetermined width being interleaved between adjacent basic cell lines.

Abstract: A non-volatile memory cell of the MNOS type, in which the sidewalk effect is avoided or at least considerably reduced by limiting the extension of the boundary layer, in which charge is stored, to a region which is smaller than the thin gate dielectric covered by the gate electrode. The gate electrode extends from the active region over a thin insulator, in which no charge storage takes place, to above the thicker field insulation.

Abstract: By the use of high-resistivity polycrystalline silicon (poly) in MIS elements, a depletion layer can be formed in the poly material which brings about an electric decoupling between the poly (gate) and the underlying semiconductor body. This effect can be utilized advantageously in various circuit elements, such as in CCD's, in order to obtain a favorable potential distribution in the substrate; in MOS transistors in order to reduce the parasitic capacities; and in high-voltage devices in order to increase the breakdown voltage at the edge of the field plate (resurf).

Abstract: A monolithically integrated resistive attenuator is autobiased from an input bipolar signal the amplitude of which is higher than the integrated circuit voltage supplies. The resistive attenuator is arranged in a first pocket formed in an epitaxial layer, and is connected between the input bipolar signal and ground. An intermediate tap produces an output signal. A diode and capacitor are formed in a second pocket. The diode is connected between the input bipolar signals and the epitaxial layer while the capacitor is connected between the epitaxial layer and the isolation walls thereof. The positive half-periods of the input bipolar signal charges the capacitor, which in turn biases the epitaxial layers. The attenuator, therefore, can be monolithically integrated into a silicon chip and remain isolated for all values of the input bipolar signal.

Abstract: An emitter contact structure is disclosed for alleviating forward bias beta degradation in a bipolar transistor. The structure comprises emitter contact metallurgy which travels over a dielectric insulating layer having an area of increased thickness adjacent to the area of contact between the metallurgy and the emitter.

Abstract: The inclusion of split power buses in standard cells enables the modification of IC performance through separate control over the width of the power bus and the size of active devices within the cell. This allows problems such as excessive voltage drop on power buses, insufficient power handling capability within the cell, excessive current consumption within the cell and so forth, to be corrected without major redesign of the cells or the IC.

Abstract: Concentric patterns of cells or macros (1) and conductive lines 13 conserve space on a substrate having two conductive levels. Macros (1) occupy only the first metal level and lines 13 are on the second metal level. The second metal level may also contain concentric patterns of power buses 20 and ground buses 20.