Patents Examined by Earl Taylor
  • Patent number: 10224358
    Abstract: Embodiments of the invention include a semiconductor light emitting device including a semiconductor structure. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region. A wavelength converting structure is disposed in a path of light emitted by the light emitting layer. A diffuse reflector is disposed along a sidewall of the semiconductor light emitting device and the wavelength converting structure. The diffuse reflector includes a pigment. A reflective layer is disposed between the diffuse reflector and the semiconductor structure. The reflective layer is a different material from the diffuse reflector.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: March 5, 2019
    Inventors: Dawei Lu, Oleg Shchekin
  • Patent number: 10211200
    Abstract: The present disclosure relates to a Silicon Controlled Rectifier (SCR) in non-planar technology to provide a robust ESD protection in System on Chip employing non-planar technologies. The disclosed SCR incorporates wire or fin shaped nanostructures extending from p-type tap to cathode, from the cathode to anode, and from the anode to n-type tap to provide parallel trigger paths to prevent problem of current crowding at the base emitter junction that limits efficient turn-on in conventional SCRs. The proposed structure helps in offering lower trigger and holding voltage, and therefore very high failure currents. The disclosed SCR has sub-3V trigger and holding voltage to provide an efficient and robust ESD protection in SOCs. The proposed device also offers three times better ESD robustness per unit area. Further the proposed SCR has no added capacitive loading and is compatible with standard process flow and design rules.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: February 19, 2019
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Mayank Shrivastava, Milova Paul, Christian Russ, Harald Gossner
  • Patent number: 10211151
    Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises etching a pattern of lines that contain notches that are narrower than other parts of the line. Thereafter, vias are created where the notches are located. The locations of the vias are such that the effect of blown-out areas is minimized. Thereafter, the lines are etched and the vias and line areas are filled. The layers are planarized such that the metal fill is level with a surrounding ultra-low-k dielectric. Additional metal layers, lines, and vias can be created. Other embodiments are also described herein.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Michael Rizzolo, Nicole A. Saulnier
  • Patent number: 10185043
    Abstract: Among other things, a detector unit for a radiation detector array is provided. The detector unit includes a radiation detection sub-assembly including a scintillator and a photodetector array. A first routing layer is coupled to the photodetector array of the radiation detection sub-assembly at a first surface of the routing layer. An electronics assembly includes an analog-to-digital converter that converts an analog signal to a digital signal. A second routing layer is disposed between the A/D converter and the first routing layer. A shielding element is disposed between the A/D converter and the second routing layer. The shielding element shields the A/D converter from the radiation photons. The second routing layer couples the electronics sub-assembly to the first routing layer. A first coupling element couples the A/D converter to the second routing layer.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: January 22, 2019
    Assignee: Analogic Corporation
    Inventors: Randy Luhta, Chris Vrettos
  • Patent number: 10186492
    Abstract: A package structure includes at least one die, an antenna element, and at least one through interlayer via. The antenna element is located on the at least one die. The at least one through interlayer via is located between the antenna element and the at least one die, wherein the antenna element is electrically connected to the at least one die through the at least one through interlayer via.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: January 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
  • Patent number: 10170534
    Abstract: A display device includes: a substrate; a plurality of display elements in a display area of the substrate, where each of the plurality of display elements includes a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode; a drive circuit on an outer side of the display area and including a thin film transistor; a first insulating layer on the drive circuit; a first power supply line layer on the first insulating layer and overlapping the drive circuit; a second insulating layer on the first power supply line layer; and a connection electrode layer on the second insulating layer, where the connection electrode layer electrically connects the first power supply line layer to the opposite electrode.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: January 1, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dongwook Kim, Wonkyu Kwak, Sunja Kwon, Seho Kim, Hansung Bae
  • Patent number: 10166747
    Abstract: A resin multilayer substrate includes insulating base materials integrated by thermocompression bonding and each including a thermoplastic resin as a main material. The insulating base materials include a first insulating base material with a first conductor pattern thereon, and a second insulating base material with a second conductor pattern thereon. The second insulating base material, an intermediate resin material layer, and the first insulating base material are stacked in this order. The intermediate resin material layer includes an intermediate region and an end region in contact with the surface on a first side of the second conductor pattern. The surface on the first side of the intermediate resin material layer is in contact with the first insulating base material, and, when seen in plan view, the first conductor pattern extends over the intermediate region and the end region.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: January 1, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Keisuke Ikeno, Shigeru Tago, Hirohumi Shinagawa, Kuniaki Yosui, Yuki Ito
  • Patent number: 10147905
    Abstract: A display device according to the present invention includes a display region arranged with a plurality of pixels, and a sealing layer covering the display region, wherein the sealing layer includes an insulation layer having a density pattern, the density pattern is a pattern including a low density region and a high density region, the low density region has the insulation layer with a lower density than an average density within the display region of the insulation layer, and the high density region has the insulation layer with a higher density than an average density within the display region of the insulation layer.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: December 4, 2018
    Assignee: Japan Display Inc.
    Inventor: Hiraaki Kokame
  • Patent number: 10147776
    Abstract: Disclosed are a display device and a method of manufacturing the same. In the disclosed display device, a pad cover electrode disposed on a pad area comes into contact with an upper surface and a side surface of a pad electrode since a planarization layer is disposed on an active area excluding the pad area, which may prevent contact failure between the pad cover electrode and a conductive ball. In addition, in the display device, a first electrode, which is connected to a thin film transistor via a pixel connection electrode, is formed via the same mask process as the planarization layer so that it has a line width similar to that of the planarization layer and overlaps the planarization layer, which may simplify a structure and a manufacturing process.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: December 4, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Seung-Hee Nam, Jeong-Oh Kim, Jung-Ho Bang, Jung-Sun Beak, Jong-Won Lee
  • Patent number: 10141275
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface; a pad disposed over the first surface; a first passivation disposed over the first surface and partially covering the pad; a redistribution layer (RDL) disposed over the first passivation, and including a conductive line extending over the first passivation and a second passivation partially covering the conductive line. The conductive line includes a via portion coupled with the pad and extended within the first passivation towards the pad, and a land portion extended over the first passivation, wherein the land portion includes a plurality of first protrusions protruded away from the first passivation.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: November 27, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Po Chun Lin
  • Patent number: 10128395
    Abstract: A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped region. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. The trench structure may include a textured surface for increased solar radiation collection. Among other advantages, the resulting structure increases efficiency by providing isolation between adjacent P-type and N-type doped regions, thereby preventing recombination in a space charge region where the doped regions would have touched.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: November 13, 2018
    Assignee: SunPower Corporation
    Inventor: David D. Smith
  • Patent number: 10128130
    Abstract: A compact and high-reliability semiconductor device is implemented. The bonding wires situated in the vicinity of a gate, and the bonding wires situated in the vicinity of a vent facing to the gate across the center of a semiconductor chip in a molding step have a loop shape falling inwardly of the semiconductor chip, have a weaker pulling force (tension) than those of other bonding wires, and are loosely stretched with a margin. The bonding wires situated in the vicinity of the gate in the molding step are, for example, a first wire and a fifth wire to be connected with a first electrode pad and a fifth electrode pad, respectively. Whereas, the bonding wires situated in the vicinity of the vent in the molding step are, for example, a third wire and a seventh wire to be connected with a third electrode pad and a seventh electrode pad, respectively.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: November 13, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Yuki Yagyu
  • Patent number: 10115742
    Abstract: In a transistor including an oxide semiconductor, a variation in electrical characteristics is suppressed and reliability is improved. A semiconductor device includes a transistor. The transistor includes a first gate electrode, a first insulating film over the first gate electrode, an oxide semiconductor film over the first insulating film, a second insulating film over the oxide semiconductor film, a second gate electrode over the second insulating film, and a third insulating film over the oxide semiconductor film and the second gate electrode. The oxide semiconductor film includes a channel region overlapping with the second gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The first gate electrode and the second gate electrode are electrically connected to each other.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: October 30, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kenichi Okazaki, Masashi Tsubuku, Haruyuki Baba, Sachie Shigenobu, Emi Koezuka
  • Patent number: 10115798
    Abstract: A semiconductor device is provided with: a semiconductor substrate; a first electrode disposed on a surface of the semiconductor device and configured to be soldered to a conductive member; and a second electrode disposed on the surface of the semiconductor device and configured to be wire-bonded to a conductive member. The first electrode includes first, second and third metal layers. The second metal layer is located between the first and third metal layers. A metallic material of the second metal layer is greater in tensile strength than a metallic material of each one of the first metal layer and the third metal layer. The second electrode includes a layer made of a same metallic material as one of the first metal layer and the third metal layer, and does not include any layers made of a same metallic material as the second metal layer.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: October 30, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Naoki Akiyama, Hiroki Tsuma, Takashi Kuno, Toshitaka Kanemaru, Kenta Hashimoto
  • Patent number: 10109611
    Abstract: An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit; a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than the total area of the electrode pads; and a resin package which seals the semiconductor chip.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: October 23, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Mamoru Yamagami, Kenji Fujii
  • Patent number: 10109638
    Abstract: A semiconductor device with embedded non-volatile memory (eNVM) is described. The device is formed on a silicon-on-insulator (SOI) substrate, such as a fully depleted SOI (FDSOI) substrate. The substrate includes a SOI region and a hybrid region. The SOI region includes the surface substrate, BOX and bulk substrate while the hybrid region includes only the bulk substrate. NVM and high voltage (HV) transistors are disposed in the hybrid region while a logic and radio frequency (RF) transistors are disposed in the SOI region. The gates of the various transistors have about coplanar top surfaces. As such, the hybrid region compensates for height differential of transistors, enabling transistors to have about coplanar top surfaces. In addition, the hybrid region enables transistors which suffer from floating body effects to be disposed therein.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Ming Zhu, Pinghui Li, Danny Shum, Fan Zhang, Yiang Aun Nga
  • Patent number: 10103055
    Abstract: An expansion sheet is adapted to be held and expanded by an expanding apparatus when a platelike workpiece is attached to the expansion sheet. The expansion sheet has a peripheral area around the workpiece where the expansion sheet is adapted to be held by first, second, third, and fourth holding units that are moveable away from each other. The expansion sheet includes a base sheet and an adhesive layer formed on the base sheet, the adhesive layer having adhesion adapted to be reduced by applying ultraviolet light. The adhesion of the adhesive layer in the peripheral area of the expansion sheet is lower than that in the other area of the expansion sheet.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: October 16, 2018
    Assignee: Disco Corporation
    Inventors: Shinichi Fujisawa, Ryoji Tanimoto
  • Patent number: 10103326
    Abstract: Methods, systems, and devices for memory arrays that use a conductive hard mask during formation and, in some cases, operation are described. A hard mask may be used to define features or components during the numerous material formation and removal steps used to create memory cells within a memory array. The hard mask may be an electrically conductive material, some or all of which may be retained during formation. A conductive line may be connected to each memory cell, and because the hard mask used in forming the cell may be conductive, the cell may be operable even if portions of the hard mask remain after formation.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: October 16, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Michael Bernhardt, Tony Lindenberg, Wenzhe Zhang, Douglas Capson
  • Patent number: 10090433
    Abstract: A semiconductor heterostructure including a polarization doped region is described. The region can correspond to an active region of a device, such as an optoelectronic device. The region includes an n-type semiconductor side and a p-type semiconductor side and can include one or more quantum wells located there between. The n-type and/or p-type semiconductor side can be formed of a group III nitride including aluminum and indium, where a first molar fraction of aluminum nitride and a first molar fraction of indium nitride increase (for the n-type side) or decrease (for the p-type side) along a growth direction to create the n- and/or p-polarizations.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: October 2, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Alexander Dobrinsky, Michael Shur
  • Patent number: 10091873
    Abstract: An apparatus comprising a printed circuit board (PCB) that includes: a multilayer lamination of layers; vias on a surface of the PCB; and bonding pads that couple a ball grid array of an integrated circuit (IC) package to layers through the vias, wherein the bonding pads includes: first bonding pads in a first area of the PCB, each first bonding pad being coupled to a via of the vias in the first area, second bonding pads arranged in a second area of the PCB, each second bonding pad being coupled to a via of the vias in the second area, and third bonding pads arranged in a third area of the PCB, each third bonding pad being coupled to two or more vias of the vias in the third area, wherein the third area is located between the first area and the second area is disclosed.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: October 2, 2018
    Assignee: Innovium, Inc.
    Inventor: Yongming Xiong