Abstract: A circuit board and a smart card module and a smart card employing the circuit board are provided. The circuit board includes a substrate and a pad region provided on the substrate. The pad region is configured for mounting an electronic component. The pad region comprises a plurality of pads spaced from each other and traces connected to their respective pads. At least one of the traces comprises an extension which extends along a perimeter of the pad region. The present invention provides a reliable adhesion between the chip and pad region.

Abstract: An electronic device may include at least one image sensor that includes a plurality of photo-sensing devices, a photoelectric device on one side of the semiconductor substrate and configured to selectively sense first visible light, and a plurality of color filters on separate photo-sensing devices. The plurality of color filters may include a first color filter configured to selectively transmit a second visible light that is different from the first visible light and a second color filter transmitting first mixed light including the second visible light. The electronic device may include multiple arrays of color filters. The electronic device may include different photoelectric devices on the separate arrays of color filters. The different photoelectric devices may be configured to sense different wavelength spectra of light.

Abstract: According to one embodiment, a thin-film transistor includes a polycrystalline semiconductor layer, a gate electrode opposing the polycrystalline semiconductor layer, a gate insulating film provided between the gate electrode and the polycrystalline semiconductor layer and in contact with the gate electrode, and an amorphous layer provided between the gate insulating film and the polycrystalline semiconductor layer, and in contact with the gate insulating film and the polycrystalline semiconductor layer.

Abstract: In pixels that are two-dimensionally arranged in a matrix fashion in the pixel array unit of a solid-state imaging element, a photoelectric conversion film having a light shielding film buried therein is formed and stacked on the light incident side of the photodiode. The present technique can be applied to a CMOS image sensor compatible with the global shutter system, for example.

Abstract: Incorporating at least one magnetic alignment structure on a microelectronic device and incorporating at least one alignment coil within a microelectronic substrate, wherein the alignment coil may be powered to form a magnetic field to attract the magnetic alignment structure, thereby aligning the microelectronic device to the microelectronic substrate. After alignment, the microelectronic device may be electrically attached to the substrate. Embodiments may include additionally incorporating an alignment detection coil within the microelectronic substrate, wherein the alignment detection coil may be powered to form a magnetic field to detect variations in the magnetic field generated by the alignment coil in order verify the alignment of the microelectronic device to the microelectronic substrate.

Abstract: According to one embodiment, an insulating layer is provided above a word line contact region portion. An upper surface of the insulating layer is at a height higher than an uppermost conductive layer. A first cover film is provided between the word line contact region portion and the insulating layer. A second cover film included in a first separation portion covers a side surface along a first direction of the insulating layer and a side surface along the first direction of the word line contact region portion. A third cover film is provided on the uppermost conductive layer. The third cover film covers a side surface along a second direction of the insulating layer. The first, second, and third cover films are of materials different from a material of the insulating layer.

Abstract: High electron mobility leads to better device performance and today is achieved by fabricating “gated devices” within a high-mobility two-dimensional electron gas (2DEG. However, the fabrication techniques used to form these devices lead to rapid degradation of the 2DEG quality which then can limits the mobility of the electronic devices. Accordingly, it would be beneficial to provide a process/technique which circumvents this processing and 2DEG layer damage. By exploiting a flip-chip methodology such damaging processing steps are separated to a second die/wafer which is then coupled to the 2DEG wafer. Extensions of the technique with two or more different semiconductor materials or material systems may be employed in conjunction with one or more electronic circuits to provide 2DEG enabled circuits in 2D and/or 3D stacked configurations. Further semiconductor materials providing EG elements may incorporate one or more of 2DEG, 1DEG, and “zero” DEG structures.

Abstract: A semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface; a pad disposed over the first surface; a first passivation disposed over the first surface and partially covering the pad; a redistribution layer (RDL) disposed over the first passivation, and including a conductive line extending over the first passivation and a second passivation partially covering the conductive line. The conductive line includes a via portion coupled with the pad and extended within the first passivation towards the pad, and a land portion extended over the first passivation, wherein the land portion includes a plurality of first protrusions protruded away from the first passivation.

Abstract: Disclosed is a light emitting device and a method of manufacturing the same. The light emitting device includes a body, a first electrode installed in the body and a second electrode separated from the first electrode, a light emitting chip formed on one of the first and second electrodes, and electrically connected to the first and second electrodes, and a protective cap projecting between the first and second electrodes.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a well region on the semiconductor substrate, a radio frequency circuit, a first guard ring adjacent to the RF circuit, and a first isolation region directly disposed between the RF circuit and the first guard ring. The well region has a first conductive type. The RF circuit includes a FIN field-effect transistor having a plurality of first fins and a plurality of first polys on the well region, wherein the first polys are perpendicular to the first fins. The first guard ring includes a plurality of second fins and a pair of second polys on the well region, wherein the second polys are perpendicular to the second fins. The first fins are arranged parallel to the second fins, and the first fins are separated from the second fins by the first isolation region.

Abstract: In one embodiment, a III-V high electron mobility semiconductor device includes a semiconductor substrate including a GaN layer, an AlGaN layer on the GaN layer wherein a 2 DEG is formed near an interface of the GaN layer and the AlGaN layer. An insulator may be on at least a first portion of the AlGaN layer and a P-type GaN gate region may be overlying a second portion of the AlGaN layer wherein the 2 DEG does not underlie the P-type GaN gate region.

Abstract: A semiconductor device with high design flexibility is provided. A first transistor and a second transistor having electrical characteristics different from those of the first transistor are provided over the same layer without significantly increasing the number of manufacturing steps. For example, semiconductor materials with different electron affinities are used for a semiconductor layer in which a channel of the first transistor is formed and a semiconductor layer in which a channel of the second transistor is formed. This allows the threshold voltages of the first transistor and the second transistor to differ from each other. Forming a gate electrode using a damascene process enables miniaturization and high density of the transistors. Furthermore, a highly-integrated semiconductor device is provided.

Abstract: A semiconductor device and a method are disclosed herein. The semiconductor device includes a device die, a molding layer surrounding the device die, a plurality of first vertical conductive structures formed within the molding layer, and a plurality of second vertical conductive structures formed within the molding layer. The first vertical conductive structures and the second vertical conductive structures are interlaced with each other, and an insulating structure is formed between the first vertical conductive structures and the second vertical conductive structures.

Abstract: In some embodiments, integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate are presented.

Abstract: There is provided a production method which enables stable formation of a p-type zinc oxide film and also is suitable for enlarging the area of the film. The method for producing a p-type zinc oxide film according to the present invention comprises the steps of: placing a target containing a zinc source and a substrate in a gas atmosphere containing a nitrogen source and an oxygen source and having a gas pressure of 0.1 Pa to 100 Pa, and exposing the target to arc discharge, thereby forming a precursor film containing zinc and oxygen on the substrate; and annealing the precursor film in an oxidizing atmosphere, thereby forming a p-type zinc oxide film.

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

Abstract: A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped region. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. The trench structure may include a textured surface for increased solar radiation collection. Among other advantages, the resulting structure increases efficiency by providing isolation between adjacent P-type and N-type doped regions, thereby preventing recombination in a space charge region where the doped regions would have touched.

Abstract: Methods, systems, and devices for memory arrays that use a conductive hard mask during formation and, in some cases, operation are described. A hard mask may be used to define features or components during the numerous material formation and removal steps used to create memory cells within a memory array. The hard mask may be an electrically conductive material, some or all of which may be retained during formation. A conductive line may be connected to each memory cell, and because the hard mask used in forming the cell may be conductive, the cell may be operable even if portions of the hard mask remain after formation.

Abstract: Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate. The device includes a metal-oxide-semiconductor transistor formed in a second region of the substrate comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and second silicide region overlying the second gate. A strain inducing structure overlies at least the NVM transistor and a surface of the substrate in the first region of the substrate.

Abstract: A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane; a first electrode having a first region in the SiC layer, the inclination angle of a side surface of the first region being 60 to 85 degrees; a second electrode; a first gate electrode; a second gate electrode facing the first gate electrode; first and second gate insulating layers; a first region of a first conductivity type in the SiC layer; a second region of a second conductivity type between the first region and the first gate insulating layer; a third region of the second conductivity type between the first region and the second gate insulating layer; a sixth region of the second conductivity type between the first region and the first region; and a seventh region of the second conductivity type between the first region and the sixth region.