Abstract: In the synthesis of frequency channel spacing in an RF transmission signal, a raster component of the desired frequency channel spacing is provided by an integer IF frequency synthesizer (44). Because the frequencies associated with the IF synthesizer are lower then those associated with an RF frequency synthesizer (48), the IF synthesizer can incorporate the desired raster using a lower feedback divisor (N) than can the RF synthesizer.

Abstract: A probability distribution transformer (110) in a multi-carrier modulation (MCM) transmitter (101) receives a MCM signal comprising data packets that represent amplitude values, where the amplitude values are characterized by a Gaussian probability density function. The probability distribution transformer (110), which is provided by a number of piecewise linear transforms, produce a transformed MCM signal comprising transformed data packets which represent transformed amplitude values, where the transformed amplitude values are characterized by a uniform probability density function. When transmitted, the transformed MCM signal results in reduced peak-to-average power ratio (PAPR). In a corresponding MCM receiver (102), a probability distribution inverter (180) inverts the transformation.

Abstract: A method and an arrangement are presented for processing received data blocks in a digital radio receiver. Received data blocks are equalized (306) and channel decoded, (309) after which they are checked (310) for errors. Additionally there is monitored (303) the amount of received but not yet equalized and channel decoded data. As a response to a finding indicating that an equalized and channel decoded data block contains errors (310), it is checked (313) whether the amount of received but not yet equalized and channel decoded data is below a certain threshold. As a response to a finding indicating that the amount of received but not yet equalized and channel decoded data is below said threshold, the data block which was found to contain errors is iteratively equalized and channel decoded. By adaptively allowing iterative equalization and channel decoding, retransmissions may be avoided.

Abstract: A variable-mode digital logic circuit is provided for accepting and serializing a parallel data word, so that the parallel data word may be transmitted from the digital logic circuit over a single one-bit wide trace. In some embodiments, the variable-mode digital logic circuit may include a plurality of parallel data traces for receiving the parallel dataword, a plurality of select-capable multiplexor circuits for sequentially activating certain ones of the parallel data traces and for multiplexing the received data into a serial data stream, a ring counter for controlling a frequency of specific operations performed within the circuit, and at least one additional multiplexor circuit array for receiving data output from the plurality of select-capable multiplexor circuits and for further serializing the received data for output on the single one-bit wide trace. The digital logic circuit may be adapted to operate according to one of a plurality of variable modes.

Abstract: In a duplex link (40, 60, 90, 116) coupling first and second frequency hopping wireless communication devices, either or both of the frequency hopping patterns that are respectively used in the downlink and the uplink can be selectively and dynamically extended. Extension of the frequency hopping pattern associated with the uplink (55, 74) can compensate for a power imbalance between the uplink and the downlink by improving the gain of the uplink. By extending the frequency hopping pattern associated with the downlink (106, 129), strong interfering frequencies that would otherwise interfere with many downlink frequencies can be avoided.

Abstract: The invention proposes a device for generating, from incoming signal values (Xi,n), soft-values (Yi,n) to be input into a channel decoder of a communication device for use in a wireless communication system, comprising truncation means (24, 26, 28) for truncating the incoming signal values (Xi,n) such as to fall within a predetermined limit value range, and normalization means (30, 32) for normalizing the truncated signal values (Xti,n) such as to fit to an input range of the decoder. According to the invention, the truncation means (24, 26, 28) are adapted to determine the boundaries of the limit value range in dependence on information representative of a signal-to-noise ratio of the incoming signal values (Xi,n). The truncated signal values (Xti,n), after normalization, then are output as said soft-values (Yi,n).

Abstract: Method and apparatus for time aligning first and second signals. The second signal is modulated by the first signal to provide a third signal. Frequency components of the third signal are then determined, the frequency components being indicative of time alignment between the first and second signals. The method and apparatus is particularly suitable for converting a Non-Return-to-Zero data signal to a Return-to-Zero data signal by modulating the Non-Return-to-Zero data signal with a Return-to-Zero pulse signal. The method and apparatus provides for the Non-Return-to-Zero data signal and the Return-to-Zero pulse signal being correctly time aligned in an automated manner without human intervention.

Abstract: A method and system for providing a frequency correction for a spread spectrum communication receiver. In the method and system, a frequency offset is determined by processing successive samples of a despread data signal. A correction sequence is generated from this determined offset and combined with a code-spread received signal prior to despreading. A filter may be included in order to reduce noise in the system.

Abstract: The purpose of the present invention is to offer a structure of a CDMA system having a power control method and interference cancellers which can effectively increase the system capacity and is resistant to sudden changes on the communication path, and to achieve a power control method with a fast response capable of preventing unnecessary increases in the transmission power (and multiple access interference) of the uplink by reflecting the values of the post-interference cancellation signal-to-interference power ratio in the generation of power control command information.

Abstract: A multimode clock recovery circuit for providing constant bit rate services in a cell relay network has an embedded digital phase locked loop including an input circuit capable of generating a phase signal from at least two types of input signal. The phase signal controlling the output of the phase locked loop generates clock signals for the constant bit rate services.

Abstract: A process for non coherent DP-MOK reception with combination of multiple paths and corresponding receiver. The process includes demodulation of orthogonal signals (MOK) which is combined with differential phase demodulation (DP) and diversity processing related to multiple paths in the radiofrequency channel. Diversity processing is achieved making use of differential demodulation by calculating a weighting factor, this factor then being used in the MOK part (before selecting and switching) and in the DP part to correct the calculated energy.

Abstract: An apparatus and method for calculating and implementing a Fibonacci mask for a code generator is disclosed herein. The first step receives a desired code offset from a reference code state in a Fibonacci field. Next, a field vector in a Galois field with the same code offset sought in the first field is calculated. In the next step, the first field vector is transformed into a second field vector, which is operable as a mask in the Galois LFSR. The transform step is accomplished by multiplying the Galois field vector by a linear N×N transformation matrix to obtain the Fibonacci field vector. And the N×N transformation matrix is obtained from iterated states of the Fibonacci LFSR.

Abstract: A highly-programmable Finite Impulse Response (FIR) digital filter overcomes the limitations of conventional configurations. Specifically, a compound FIR filter configuration is provided, offering the advantages of heightened programmability in both transfer function coefficients hf, hg and in degree of interpolation; distribution and sharing of resources between F and G filter portions, mode-switching capability between high-pass and low-pass modes, and programmable truncation/saturation.

Abstract: A system and method for training an equalizer structure of a digital data communication system in order to compensate for transmission impairments on the line particularly wherein one transceiver of the two is resource limited. In an exemplary embodiment, a line card provides equalization feedback to a modem whenever changes to the equalization are beneficial. The line card calculates a limited number of tap correction factors at one time, transfers the tap correction factors to the modem, and then trains up a new set of tap correction factors. The modem incorporates the tap correction factors into the taps of the corresponding frequency ranges. The process iterates indefinitely through the transmission resulting in a very high quality equalization.

Abstract: This invention is regarding a frequency shifting circuit suitable for a digital demodulator in a multi-carrier communications system. After converting analog signal vectors to the input signal vectors according to a predetermined sampling clock, control data is generated from a frequency difference between sub-carrier bands and center carrier band. A signal vector rotator is provided corresponding to each of the sub-carrier bands and rotates the input signal vectors on the I-Q plane by an angle determined depending on corresponding control data to shift the sub-carrier bands of the input signal vectors to the center carrier band. A band-pass filter passes an output signal vector of the center carrier band.

Abstract: Techniques to acquire the frequency of a signal instance based on a window of data samples covering a time period shorter than the time needed to achieve frequency lock. The window of data samples is initially captured and stored to a sample buffer. A segment of data samples is then retrieved from the sample buffer for processing. The retrieved data samples are rotated by a current frequency error estimate to provide frequency-translated data samples, which are further processed to provide one or more pilot symbols. An updated frequency error estimate for the frequency-translated data samples is then derived based on the pilot symbols using a frequency control loop. The window of data samples is processed for a number of iterations until frequency acquisition is achieved for the signal instance or termination is reached. For each iteration, one segment is processed at a time and typically in sequential order.

Abstract: An equalizer circuit includes a carrier sensor, first and second equalizer units, carrier sense controller, and reception signal switching unit. The carrier sensor senses the start of a reception signal on the basis of a signal representing the reception level of the reception signal. The first and second equalizer units equalize the reception signal. The carrier sense controller alternately enables the first and second equalizer units every frame reception in accordance with an output from the carrier sensor. The reception signal switching unit alternately switches between outputs from the first and second equalizer units every frame reception and outputs the selected output as demodulation data.

Abstract: Detection and identification of known sequences such as sequences composed of Walsh-Hadamard sequence and scrambling sequence are provided in a fast fading and frequency offset environment using a segmented correlator and FHT (Fast Hadamard Transform) architecture with frequency offset compensation. The incoming sequence of samples or data is segmented into blocks. Each block is individually detected using a correlator/FHT segment. Each sequence identifying output of each correlator/FHT segment is multiplied by a sinusoid for frequency offset compensation. The frequency offset compensated output from each correlator/FHT segment is summed with the corresponding frequency offset compensated output of other correlator/FHT segments. Each sum is compared with a threshold to determine whether a particular sequence has been detected and identified.

Abstract: A system and method of creating a pulse train signal of a pulse width modulator whose fundamental frequency is time-varying is disclosed. The electrical system includes a pulse width modulator which provides a pulse train signal. The system also includes a power source connected to the pulse width generator. The system further includes a binary counter having an input and a plurality of outputs, wherein the pulse train signal generated by the pulse width modulator is operatively coupled to the input of the binary counter. A plurality of resistors are operatively coupled to the plurality of outputs of the binary counter and operatively coupled to a node. A timing resistor is operatively coupled between a first voltage potential and the node, while a timing capacitor is operatively coupled between the node and a second voltage potential. The node is operatively coupled to an input of the pulse width modulator.

Abstract: A quadrature phase modulation receiver for a spread spectrum communications system includes a mixer for mixing a received spread spectrum signal with a heterodyne signal to convert the frequency of the received signal to an intermediate frequency. A regulated oscillators module is coupled to the receiver for producing the heterodyne signal and signal equal to the intermediate frequency signal. A frequency multiplier circuit is coupled to the mixer for receiving the intermediate frequency signal and multiplying the frequency of the signal by a predetermined multiplication factor. An oscillator control signal is produced based on the frequency multiplied signal to maintain synchronization between the receiver and the transmitter.