Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

Abstract: The present application provides a pixel unit, a sensor and a sensing array. The pixel unit includes a charge collecting area configured to receive radiation to generate photo-generated charge; a transmission gate connected between the charge collecting area and a floating diffusion node and configured to transfer the photo-generated charge from the charge collecting area to the floating diffusion node; an electric potential adjustment area disposed at a periphery of the charge collecting area and configured to concentrate the photo-generated charge to a side of a connection between the charge collecting area and the transmission gate.

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.

Abstract: A semiconductor module includes a heat dissipating plate; an insulating substrate disposed on an upper surface of the heat dissipating plate; a semiconductor element disposed an upper surface of the insulating substrate; a frame-shaped case bonded to the upper surface of the heat dissipating plate via an adhesive so as to surround peripheries of the insulating substrate and the semiconductor element; and a sealing resin that fills an inner space defined by the frame-shaped case and the heat dissipating plate so as to seal the insulating substrate and the semiconductor element, wherein at an interface between the heat dissipating plate and the frame-shaped case, a recess communicating with the inner space is formed in at least one of the frame-shaped case and the heat dissipating plate, and the sealing resin is filled in the recess.

Abstract: Fabrication of a magnetic memory element, including a via (125) in an interlevel dielectric layer (120), providing an electrical connection between an underlying metal region (110) and a magnetoresistive stack device, such as a magnetic tunnel junction (150), involves forming a transition metal layer (130) in the via by atomic layer deposition. The via optionally includes a tantalum-rich layer (140) above, and/or a cap layer (115) below, the transition metal layer, and may have a diameter less than or equal than a diameter of the magnetoresistive stack device.

Abstract: A display panel including a glass substrate having an opening area, and a display area at least partially surrounding the opening area; a thin film transistor on the display area including a semiconductor layer and a gate electrode; a display element electrically connected to the thin film transistor; a multi-layer including an insulating layer and a lower insulating layer. The insulating layer is between the glass substrate and the display element and the lower insulating layer is between the glass substrate and the insulating layer; and a thin-film encapsulation layer covering the display element including an inorganic encapsulation layer and an organic encapsulation layer. The multi-layer includes a first groove between the opening area and the display area. A first width of a portion of the first groove in the lower insulating layer is greater than a second width of a portion of the first groove in the insulating layer.

Abstract: An OLED device may include the following elements: a common electrode; a first pixel electrode overlapping the common electrode; a first emission layer positioned between the first pixel electrode and the common electrode; a second pixel electrode; a second emission layer positioned between the second pixel electrode and the common electrode; and a pixel defining layer including a first opening, a second opening, a first flat face, and an uneven surface structure, wherein the first opening partially exposes the first pixel electrode, wherein the second opening partially exposes the second pixel electrode, wherein the first flat face may be opposite the uneven surface and may be positioned between the first pixel electrode to the second electrode, and wherein the uneven surface may be positioned between the first opening and the second opening.

Abstract: A display device and method of fabricating the same are provided. The display device includes a substrate and a thin-film transistor formed on the substrate. The thin-film transistor includes a lower gate conductive layer disposed on the substrate, and a lower gate insulating film disposed on the lower gate conductive layer The lower gate insulating film includes an upper surface and sidewalls. The thin-film transistor includes an active layer disposed on the upper surface of the lower gate insulating film, the active layer including sidewalls. At least one of the sidewalls of the lower gate insulating film and at least one of the sidewalls of the active layer are aligned with each other.

Abstract: Devices, systems and methods for solid-state X-ray detection with high temporal resolution are described. An example method includes receiving an X-ray pulse in a semiconductor chip resulting in an electron cloud being formed in the semiconductor chip, applying a first set of voltages across a first plurality of drift cathode strips on a first side of the semiconductor chip and a second plurality of drift cathode strips on a second side of the semiconductor chip, applying a second set of voltages to across the first and the second plurality of drift cathode strips to form an electric field having a linear profile to cause the electron cloud to drift along the middle of the semiconductor chip, and activating a counter cathode on the second side and one or more readout anodes on the first side to collect the electron cloud after spreading in the middle section of the semiconductor chip.

Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

Abstract: A semiconductor device includes trench portions arrayed in a first direction on an upper surface side of a semiconductor substrate, a first conductivity type lower surface region provided in a part of a lower surface of the semiconductor substrate, a second conductivity type base region provided on the upper surface side, a first conductivity type first region disposed between the base region and the lower surface region, a first conductivity type upper surface region provided on an upper surface of the semiconductor substrate, and a second conductivity type bottom region disposed continuously in the first direction to be in contact with bottom portions of the trench portions. In a cross section along the first direction and perpendicular to the upper and lower surfaces and passing through the lower surface region, one end portion of the bottom region in the first direction locates directly above the lower surface region.

Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

Abstract: Image sensor, mobile terminal, image capturing method are provided. Pixel array of image sensor includes preset quantity of pixel units, pixel unit includes first and second pixels that are dual pixel focusing pixels, first pixel includes red, green, and blue subpixels, second pixel includes green subpixel and infrared subpixel, and at least one of red and blue subpixels, and each subpixel is arranged in four-in-one manner; position of infrared subpixel in second pixel is same as position of red subpixel, green subpixel, blue subpixel, first combination of subpixels, or second combination of subpixels in first pixel; or position of half the infrared subpixel in second pixel is same as position of half the red subpixel, half the green subpixel, or half the blue subpixel in first pixel, and half an infrared subpixel in each of two adjacent second pixels is combined to form entire infrared subpixel.

Abstract: A semiconductor structure and a method of fabricating therefor are disclosed. A second contact pad (500) is arranged lateral to a first contact pad (420) in an interconnect structure (400). As a result, during fabrication of the interconnect structure (400), the first contact pad (420) will not be present alone in a large bland area, due to the presence of the second contact pad (500). Thus, a pattern feature for the first contact pad (420) will not be over-resolved, increasing formation accuracy of the first contact pad (420) and thus guaranteeing good electrical transmission performance of the resulting interconnect structure (400).

Abstract: A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.

Abstract: An organic EL element includes a pixel electrode, a light emitting function layer that is formed on the pixel electrode, an electron injection layer formed on the light emitting function layer, and a counter electrode that is formed on the electron injection layer and that has semi-transmissive reflectivity, in which the counter electrode contains a reductive material that reduces material of the electron injection layer and Ag with atomic ratio of 75% or more, and an adsorption layer is formed on the counter electrode.

Abstract: A semiconductor device includes: first and second semiconductor elements, each of which has first and second electrodes; a first lead mounting the first semiconductor element; a second lead mounting the second semiconductor element; a sealing resin covering the first and second semiconductor elements; a third lead disposed apart from the first and second leads in a y direction, exposed from the sealing resin, and electrically connected to the first electrode of the first semiconductor element; a fifth lead disposed apart from the first and second leads on the opposite side to the third lead, exposed from the sealing resin, and electrically connected to the second electrode of the first semiconductor element; and a sixth lead disposed apart from the first and second leads on the same side as the fifth lead, exposed from the sealing resin, and electrically connected to the second electrode of the second semiconductor element.

Abstract: A semiconductor device includes a through-silicon via (TSV) in a TSV zone in a substrate and the TSV extends through the substrate; an ESD cell proximal to a first end of the TSV and in contact with the TSV zone, the ESD cell including a set of diodes electrically connected in parallel to each other; an antenna pad electrically connected to a second end of the TSV; and an antenna electrically connected to the antenna pad and extending in a first direction, the first direction is parallel to a major axis of the TSV. The semiconductor device includes a conductive pillar extending parallel to the TSV at a same side of the substrate as the antenna pad, wherein a first end of the conductive pillar electrically connects to the antenna pad, and a second end of the conductive pillar electrically connects to the set of diodes of the ESD cell.

Abstract: Provided is a packaging structure for packaging a display device, the packaging structure comprising: at least one composite film layer, wherein the composite film layer comprises an inorganic pattern and an organic pattern, the inorganic pattern comprises a plurality of curved structures arranged at intervals, the organic pattern comprises a first organic sub-pattern, and the first organic sub-pattern and the inorganic pattern are located in a same layer and are complementary in position; and wherein an orthographic projection of the composite film layer onto the display device at least covers a display area of the display device. A display substrate, a display apparatus, and a method for packaging a display device are also provided.

Abstract: An integrated optical display system includes a backplane with appropriate electronics, and an array of micro-devices. A touch sensing structure may be integrated into the system. In one embodiment, an integrated circuit and system is integrated on top of micro-devices transferred to a substrate. Openings in a planarization layer (or layers) may be provided to connect the micro-devices with electrodes and other circuitry. Light reflectors may be used to redirect the light, and color conversion layers or color filters may be integrated before the micro-devices or on the substrate surface opposite to the surface of micro-devices.