Patents Examined by Eduardo A. Rodela
  • Patent number: 11917806
    Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple active pillars arranged in an array on the substrate, where an outer surface layer of each of the active pillars has a concave-convex surface; forming a gate oxide layer on the substrate, where a filling region is formed between two adjacent active pillars in the same row; forming a word line and a first dielectric layer in the filling region; exposing a top surface of each of the active pillars; forming a contact layer on the top surface of each of the active pillars; and forming a capacitor structure on the contact layer.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: February 27, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xiaoling Wang, Hai-Han Hung
  • Patent number: 11916096
    Abstract: An integrated optical display system includes a backplane with appropriate electronics, and an array of micro-devices. A touch sensing structure may be integrated into the system. In one embodiment, an integrated circuit and system is integrated on top of micro-devices transferred to a substrate. Openings in a planarization layer (or layers) may be provided to connect the micro-devices with electrodes and other circuitry. Light reflectors may be used to redirect the light, and color conversion layers or color filters may be integrated before the micro-devices or on the substrate surface opposite to the surface of micro-devices.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: February 27, 2024
    Assignee: VueReal Inc.
    Inventors: Gholamreza Chaji, Yaser Azizi, Ehsanollah Fathi
  • Patent number: 11917851
    Abstract: Provided is a packaging structure for packaging a display device, the packaging structure comprising: at least one composite film layer, wherein the composite film layer comprises an inorganic pattern and an organic pattern, the inorganic pattern comprises a plurality of curved structures arranged at intervals, the organic pattern comprises a first organic sub-pattern, and the first organic sub-pattern and the inorganic pattern are located in a same layer and are complementary in position; and wherein an orthographic projection of the composite film layer onto the display device at least covers a display area of the display device. A display substrate, a display apparatus, and a method for packaging a display device are also provided.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: February 27, 2024
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Youyuan Hu, Mengyu Luan, Xinfeng Wu, Bowen Liu, Xinzhu Wang, Fei Li, Huihui Li
  • Patent number: 11908754
    Abstract: An etching apparatus is provided to be able to rotate or tilt a substrate holder on which a to-be-processed substrate is placed. According to a profile of a pre-process critical dimension of the substrate, the etching apparatus may rotate or tilt the substrate holder during an etching process in order to achieve a desired profile of a post-process critical dimension of the substrate that is related to the pre-process critical dimension.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jun Shimada, Chen-Fon Chang, Chih-Teng Liao
  • Patent number: 11908960
    Abstract: A method of making a plasmonic metal/graphene heterostructure comprises heating an organometallic complex precursor comprising a metal at a first temperature T1 for a first period of time t1 to deposit a layer of the metal on a surface of a heated substrate, the heated substrate in fluid communication with the precursor; and heating, in situ, the precursor at a second temperature T2 for a second period of time t2 to simultaneously form on the layer of the metal, a monolayer of graphene and a plurality of carbon-encapsulated metal nanostructures comprising the metal, thereby providing the plasmonic metal/graphene heterostructure. The heated substrate is characterized by a third temperature T3. The plasmonic metal/graphene heterostructures, devices incorporating the heterostructures, and methods of using the heterostructures are also provided.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: February 20, 2024
    Assignee: University of Kansas
    Inventors: Judy Z. Wu, Qingfeng Liu
  • Patent number: 11894365
    Abstract: Multiple bipolar transistors are disposed side by side in the first direction on a substrate. Multiple first capacitance devices are provided corresponding to the respective base electrodes of the bipolar transistors. A radio frequency signal is supplied to the bipolar transistors through the first capacitance devices. Resistive devices are provided corresponding to the respective base electrodes of the bipolar transistors. A base bias is supplied to the bipolar transistors through the resistive devices. The first capacitance devices are disposed on the same side relative to the second direction orthogonal to the first direction, when viewed from the bipolar transistors. At least one of the first capacitance devices is disposed so as to overlap another first capacitance device partially when viewed in the second direction from the bipolar transistors.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: February 6, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shaojun Ma, Yasunari Umemoto, Kenji Sasaki
  • Patent number: 11894258
    Abstract: There is provided a semiconductor device including: an anode electrode that is provided on a front surface side of a semiconductor substrate; a drift region of a first conductivity type that is provided in the semiconductor substrate; a first anode region of a first conductivity type that is in Schottky contact with the anode electrode; and a second anode region of a second conductivity type that is different from the first conductivity type, in which the first anode region has a doping concentration lower than or equal to a doping concentration of the second anode region, and is spaced from the drift region by the second anode region.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: February 6, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahiro Tamura, Michio Nemoto
  • Patent number: 11887858
    Abstract: A semiconductor device includes a semiconductor part, first and second electrodes. The semiconductor part is provided between the first and second electrodes. A method of manufacturing the device includes forming the first electrode covering a back surface of a wafer after the second electrode is formed on a front surface of the wafer; forming a first groove by selectively removing the first electrode; and dividing the wafer by forming a second groove at the front surface side. The wafer includes a region to be the semiconductor part; and the first and second grooves are provided along a periphery of the region. The first groove is in communication with the first groove. The second groove has a width in a direction along the front surface of the wafer, the width of the first groove being narrower than a width of the first groove in the same direction.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: January 30, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Shinji Nunotani, Shinji Onzuka
  • Patent number: 11881409
    Abstract: A method of cutting fins includes the following steps. A photomask including a snake-shape pattern is provided. A photoresist layer is formed over fins on a substrate. A photoresist pattern in the photoresist layer corresponding to the snake-shape pattern is formed by exposing and developing. The fins are cut by transferring the photoresist pattern and etching cut parts of the fins.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: January 23, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hao Huang, Chun-Lung Chen, Kun-Yuan Liao, Lung-En Kuo, Chia-Wei Hsu
  • Patent number: 11876024
    Abstract: The present disclosure provides a method of operating a benchmark device embedded on a semiconductor wafer. The method includes applying a first voltage to a first electrode of the benchmark device, and applying a second voltage to a second electrode of the benchmark device. The method further includes electrically isolating a first component of the benchmark device from a second component of the benchmark device through a disconnecting switch connected between the first component and the second component.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: January 16, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yi-Ju Chen, Jui-Hsiu Jao
  • Patent number: 11876058
    Abstract: According to one embodiment, an isolator includes a first electrode, a second electrode, a conductive body, and a first insulating layer. The second electrode is provided on the first electrode and separated from the first electrode. The conductive body is provided around the first and second electrodes along a first plane perpendicular to a first direction. The first direction is from the first electrode toward the second electrode. The first insulating layer is provided on the second electrode. The first insulating layer includes silicon, carbon, and nitrogen.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: January 16, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Kenichi Ootsuka, Mari Ootsuka
  • Patent number: 11856861
    Abstract: A spring (3, 3?) comprising a plurality of elements (30), each element (3) comprising a rigid portion (31) and a flexible beam (32), the extremities (320, 321) of the flexible beam being supported by the rigid portion (31), the flexible beam (32) having a single stable position, so that the flexible beam can be deformed when a pressure is exerted between said extremities in the direction of the rigid portion (31), and returns to said single stable position when the pressure is released, and wherein the rigid portion (31) of at least one element (30) is in contact with the flexible beam (32) of the next element between said extremities (320, 321) of the flexible beam (32), so that the spring has a negative stiffness over an operating range. The arrangement ensures a pure radial compression/expansion of the spring.
    Type: Grant
    Filed: November 23, 2018
    Date of Patent: December 26, 2023
    Assignee: Ecole Polytechnique Federale De Lausanne
    Inventors: Jonathan Chavanne, Yoan Civet, Yves Perriard
  • Patent number: 11856859
    Abstract: A piezoelectric device including a substrate, a metal-insulator-metal element, a hydrogen blocking layer, a passivation layer, a first contact terminal and a second contact terminal is provided. The metal-insulator-metal element is disposed on the substrate. The hydrogen blocking layer is disposed on the metal-insulator-metal element. The passivation layer covers the hydrogen blocking layer and the metal-insulator-metal element. The first contact terminal is electrically connected to the metal-insulator-metal element. The second contact terminal is electrically connected to the metal-insulator-metal element.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chih-Ming Chen
  • Patent number: 11855036
    Abstract: A bonding apparatus according to the present embodiment includes a first holder and a second holder. The first holder holds a first substrate. The second holder includes a plurality of suction portions that suck a second substrate and that are arranged on concentric circles about a center of the second substrate substantially evenly. The second holder bonds the second substrate to the first substrate while opposing the second substrate to the first substrate. A first gas supply portion has a plurality of first gas supply ports to supply gas toward a bonding position between the first substrate and the second substrate. The first gas supply ports are provided to correspond to at least a part of outermost suction portions that are farthest ones of the suction portions from a center of the second holder, and are concentrically arranged on a circle about the center substantially evenly.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: December 26, 2023
    Assignee: Kioxia Corporation
    Inventor: Masaharu Takizawa
  • Patent number: 11854969
    Abstract: A semiconductor structure and a method for forming the semiconductor structure are disclosed. The method includes the following operations. A first integrated circuit component having a fuse structure is received. A second integrated circuit component having an inductor is received. The second integrated circuit component is bonded to the first integrated circuit component. The inductor is electrically connected to the fuse structure, wherein the inductor is electrically connected to a ground through the fuse structure.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jen-Yuan Chang, Chia-Ping Lai
  • Patent number: 11848246
    Abstract: In an embodiment, a device includes: an interposer; a first integrated circuit device attached to the interposer; a second integrated circuit device attached to the interposer adjacent the first integrated circuit device; a heat dissipation die on the second integrated circuit device; and an encapsulant around the heat dissipation die, the second integrated circuit device, and the first integrated circuit device, a top surface of the encapsulant being coplanar with a top surface of the heat dissipation die and a top surface of the first integrated circuit device.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Sung-Feng Yeh
  • Patent number: 11837509
    Abstract: A method of packaging the silicon photonics wafer for fabricating custom optical-electrical modules includes fabricating a wafer with multiple dies of silicon photonics circuits based on custom design and conducting electrical and optical tests of the silicon photonics circuits in wafer level. The method further includes preparing the wafer for next point of use. Additionally, the method includes performing post-wafer processing on the wafer received at the next point of use. The method further includes conducting post-process electrical tests of the silicon photonics circuits in wafer level. Furthermore, the method includes preparing the wafer with known-good-dies or a known-good-wafer identified for custom use. Moreover, the method includes performing custom process on the know good dies.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: December 5, 2023
    Assignee: MARVELL ASIA PTE LTD
    Inventors: Hsu-Feng Chou, Keith Nellis, Loi Nguyen
  • Patent number: 11830932
    Abstract: A laterally diffused metal oxide semiconductor structure can include: a base layer; a source region and a drain region located in the base layer; first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; and a second conductor at least partially located on the voltage withstanding layer, where the first and second conductors are spatially isolated, and a juncture region of the first dielectric layer and the voltage withstanding layer is covered by one of the first and second conductors.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: November 28, 2023
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Budong You, Hui Yu, Meng Wang, Yicheng Du, Chuan Peng, Xianguo Huang
  • Patent number: 11830954
    Abstract: Microstructures of micro and/or nano holes on one or more surfaces enhance photodetector optical sensitivity. Arrangements such as a CMOS Image Sensor (CIS) as an imaging LIDAR using a high speed photodetector array wafer of Si, Ge, a Ge alloy on SI and/or Si on Ge on Si, and a wafer of CMOS Logic Processor (CLP) ib Si fi signal amplification, processing and/or transmission can be stacked for electrical interaction. The wafers can be fabricated separately and then stacked or can be regions of the same monolithic chip. The image can be a time-of-flight image. Bayer arrays can be enhanced with microstructure holes. Pixels can be photodiodes, avalanche photodiodes, single photon avalanche photodiodes and phototransistors on the same array and can be Ge or Si pixels. The array can be of high speed photodetectors with data rates of 56 Gigabits per second, Gbps, or more per photodetector.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: November 28, 2023
    Assignee: W&WSens Devices Inc.
    Inventors: Shih-Yuan Wang, Shih-Ping Wang
  • Patent number: 11817454
    Abstract: Described examples include a resistor having a substrate having a non-conductive surface and a patterned polysilicon layer on the non-conductive surface, the patterned polysilicon layer including polycrystalline silicon wherein at least 90% of the grains in the polycrystalline silicon are 30 nm or smaller. The resistor also has a first terminal in conductive contact with the patterned polysilicon layer and a second terminal in conductive contact with the polysilicon layer and spaced from the first contact.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: November 14, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Yanbiao Pan, Robert Martin Higgins, Bhaskar Srinivasan, Pushpa Mahalingam