Patents Examined by Eduardo A. Rodela
  • Patent number: 11417576
    Abstract: Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: August 16, 2022
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Rajesh Katkar, Liang Wang, Cyprian Emeka Uzoh, Shaowu Huang, Guilian Gao, Ilyas Mohammed
  • Patent number: 11417583
    Abstract: An LED module is disclosed. In an embodiment an LED module includes a thermally conductive substrate made of a multilayer ceramic, at least one LED on the substrate, passive SMD components arranged on the substrate, a passive component integrated in the substrate and a heat spreader configured to dissipate waste heat in horizontal and vertical directions.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: August 16, 2022
    Assignee: TDK ELECTRONICS AG
    Inventors: Thomas Feichtinger, Franz Rinner, Werner Rollett
  • Patent number: 11410927
    Abstract: A semiconductor structure and a method for forming the semiconductor structure are disclosed. The method includes receiving a first integrated circuit component having a seal ring and a fuse structure, wherein the fuse structure is electrically connected to a ground through the seal ring; receiving a second integrated circuit component having an inductor; bonding the second integrated circuit component to the first integrated circuit component; electrically connecting the inductor to the fuse structure, wherein the inductor is electrically connected to the ground through the fuse structure; and blowing the fuse structure after a treatment.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jen-Yuan Chang, Chia-Ping Lai
  • Patent number: 11411058
    Abstract: A flexible display device includes a flexible display panel and a chip on film (COF) bonded to the flexible display panel; wherein the flexible display panel is divided into a display region, a bonding region on a side of the display region, and a bending region between the display region and the bonding region; wherein the COF comprises a main body portion and two expansion bonding portions respectively disposed at two ends of one side of the main body portion; wherein an edge of the main body portion adjacent to the two expansion bonding portions are disposed with a plurality of connection pins; wherein the COF is bonded to the bonding region of the flexible display panel through the plurality of connection pins.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: August 9, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Bin Xu, Hongyu Xu
  • Patent number: 11411016
    Abstract: A semiconductor memory device includes a first chip and a second chip overlaid on the first chip. The second chip includes a memory cell array provided between a second semiconductor substrate and the first chip in a first direction, and first and second wires between the memory cell array and the first chip. The memory cell array includes three or more stacked bodies regularly arranged in a second direction perpendicular to the first direction and semiconductor layers extending in the stacked bodies in the first direction. Each of the stacked bodies includes gate electrodes stacked in the first direction. The first and second wires are aligned in the second direction with a gap therebetween.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: August 9, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Tomoya Sanuki, Keisuke Nakatsuka, Hiroshi Maejima, Kenichiro Yoshii, Takashi Maeda, Hideo Wada
  • Patent number: 11393878
    Abstract: A display panel and a display device are provided. The display panel includes a display region and a sensor region. The sensor region is provided with multiple sensors in the display panel. Multiple first pixels are arranged in the display region. The first pixels are arranged as a first array in the display region. Multiple second pixels are arranged in the sensor region, and the second pixels are arranged as a second array in the sensor region. A pixel unit area of the first array is equal to a pixel unit area of the second array, and the pixel unit area is a number of the pixels multiplied by an area of each pixel in a unit area. The display device includes the display panel and the sensors. The sensors are disposed on one side of the display panel.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: July 19, 2022
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Hong Gao, Mugyeom Kim, Yong Zhao
  • Patent number: 11387291
    Abstract: Disclosed herein is a photoelectric sensor, display panel and their manufacturing method. The photoelectric sensor may comprise a photodeformable unit and a piezoelectric unit in contact with the photodeformable unit.
    Type: Grant
    Filed: April 28, 2019
    Date of Patent: July 12, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Shuang Liang, Yingwei Liu, Zhanfeng Cao, Zhiwei Liang, Muxin Di
  • Patent number: 11387247
    Abstract: A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: July 12, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Go Oike
  • Patent number: 11374061
    Abstract: The present invention provides an organic light emitting diode (OLED) display panel and an intelligent terminal, including: an electronic element region in which sensor elements are disposed; and a pixel region provided with at least one light transmissive region. The electronic element region is arranged corresponding to the at least one light transmissive region, multiple sub-pixels are arranged in the pixel region. Pixel density of the sub-pixels is gradually decreased along a direction toward a center of the pixel region.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: June 28, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Min Zheng, Hong Gao, Mugyeom Kim, Yong Zhao
  • Patent number: 11361963
    Abstract: A semiconductor structure includes a substrate; a nucleation layer located above the substrate; and a metal nitride thin film located between the nucleation layer and the substrate. A diffusion of atoms in a material of the substrate is suppressed by depositing the metal nitride thin film between the substrate and the nucleation layer, so that a thickness of the nucleation layer is significantly reduced, and a total thermal resistance of the semiconductor structure is reduced.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: June 14, 2022
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 11362202
    Abstract: There is provided a semiconductor device including: an anode electrode that is provided on a front surface side of a semiconductor substrate; a drift region of a first conductivity type that is provided in the semiconductor substrate; a first anode region of a first conductivity type that is in Schottky contact with the anode electrode; and a second anode region of a second conductivity type that is different from the first conductivity type, in which the first anode region has a doping concentration lower than or equal to a doping concentration of the second anode region, and is spaced from the drift region by the second anode region.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: June 14, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahiro Tamura, Michio Nemoto
  • Patent number: 11349109
    Abstract: A method of manufacturing a display apparatus includes preparing a panel with a panel layer displaying images, a first protection film on a first surface of the panel layer with a first adhesion layer, and a second protection film on a second surface of the panel layer with a second adhesion layer, disposing the panel on a stage, cutting the panel on the stage along a closed-curve line to a predetermined depth extending from the second protection film to at least a portion of the first adhesion layer, and separating a first portion of the panel inside the closed-curve line from a second portion of the panel outside the closed-curve line, such that the second portion is removed simultaneously with the entire first protection film according to a first boundary by the line and a second boundary between the panel layer and the first protection film.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: May 31, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventor: Kwangnyun Kim
  • Patent number: 11348791
    Abstract: A bonding apparatus configured to bond a first substrate and a second substrate includes a first holder configured to hold the first substrate; a second holder configured to hold the second substrate; a first imaging device provided at the first holder and configured to image the second substrate held by the second holder; a first light irradiating device provided at the first holder and configured to irradiate light to the second substrate when the second substrate is imaged; a second imaging device provided at the second holder and configured to image the first substrate held by the first holder; and a second light irradiating device provided at the second holder and configured to irradiate light to the first substrate when the first substrate is imaged. Each of the first light irradiating device and the second light irradiating device is connected to a first light source configured to irradiate white light.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: May 31, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toshifumi Inamasu, Shinichi Shinozuka
  • Patent number: 11348797
    Abstract: A stacked wafer processing method for processing one wafer of a stacked wafer having at least two layers laminated, includes a sheet laying step of laying a thermocompression bonding sheet on an upper face of the one wafer, a thermocompression bonding step of thermocompression-bonding the thermocompression bonding sheet to an outer peripheral portion of the one wafer where a chamfered portion is formed, a modified layer forming step of irradiating the stacked wafer with a laser beam having a transmission wavelength to the thermocompression bonding sheet and the one wafer from the thermocompression bonding sheet side with a focal point of the laser beam positioned inside the outer peripheral portion of the one wafer, thereby continuously forming a modified layer inside the one wafer, and a chamfered portion removing step of expanding the thermocompression bonding sheet to break the chamfered portion, thereby removing the chamfered portion from the one wafer.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: May 31, 2022
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Yoshiaki Yodo, Koji Watanabe, Jinyan Zhao
  • Patent number: 11342426
    Abstract: A semiconductor device includes a semiconductor part, first and second electrodes. The semiconductor part is provided between the first and second electrodes. A method of manufacturing the device includes forming the first electrode covering a back surface of a wafer after the second electrode is formed on a front surface of the wafer; forming a first groove by selectively removing the first electrode; and dividing the wafer by forming a second groove at the front surface side. The wafer includes a region to be the semiconductor part; and the first and second grooves are provided along a periphery of the region. The first groove is in communication with the first groove. The second groove has a width in a direction along the front surface of the wafer, the width of the first groove being narrower than a width of the first groove in the same direction.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: May 24, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Shinji Nunotani, Shinji Onzuka
  • Patent number: 11335620
    Abstract: Embodiments include a microelectronic device package structure having an inductor at least partially embedded within a substrate. At least one thermal solution structure may be on a surface of the inductor, and may be thermally coupled with the inductor. The one or more thermal solution structures provide a thermal pathway for cooling for the inductor, and extend a thermal time constant of the inductor.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Michael J. Hill, Anne Augustine, Huong Do, William Lambert
  • Patent number: 11329105
    Abstract: A light absorbing member includes a first dichroic dye and a second dichroic dye. The first dichroic dye has an absorption peak wavelength between a first emission peak wavelength of the first light-emitting layer and a second emission peak wavelength of a second light-emitting layer. The second dichroic dye has an absorption peak wavelength between the second emission peak wavelength of the second light-emitting layer and a third emission peak wavelength of the third light-emitting layer. An angle of a molecule of the first dichroic dye in an absorption axis and an angle of a molecule of the second dichroic dye in an absorption axis with respect to a normal direction of the reflective layer are from 70 degrees to 90 degrees.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: May 10, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yasushi Asaoka, Tsuyoshi Kamada
  • Patent number: 11322453
    Abstract: A semiconductor package includes a die, through insulator vias, an encapsulant, and a pair of metallization layers. The through insulator vias are disposed beside the die. The encapsulant wraps the die and the through insulator vias. The pair of metallization layers is disposed on opposite sides of the encapsulant. One end of each through insulator via contacts one of the metallization layers and the other end of each through insulator via contacts the other metallization layer. The through insulator vias form at least one photonic crystal structure. A pair of the through insulator vias is separated along a first direction by a channel filled by the encapsulant. A width of the channel along the first direction is larger than a pitch of the photonic crystal structure along the first direction.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Sen-Kuei Hsu
  • Patent number: 11322558
    Abstract: A display panel and an electronic device. The display panel includes a substrate; a thin film transistor layer, the thin film transistor layer is located on the substrate; a light emitting layer, the light emitting layer is located on the thin film transistor layer, the light emitting layer includes a plurality of pixel points; the light emitting layer further includes a plurality of concentrating units, each of the concentrating units being located between two adjacent pixel points, and spaced apart from the pixel points.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: May 3, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Hanning Yang
  • Patent number: 11322436
    Abstract: A semiconductor module includes: a first metal plate including a first mount part joined with a bottom-surface electrode of a first switching element, a second mount part joined with a positive-electrode terminal, and a first narrow part between the first and second mount parts and being narrower than a part jointing the first switching element to the first mount part and the positive-electrode terminal; a second metal plate being joined with a bottom-surface electrode of a second switching element, and connected to a top-surface electrode of the first switching element; a third metal plate including a sixth mount part joined with a negative-electrode terminal, a seventh mount part connected to a top-surface electrode of the second switching element, and being narrower than the negative-electrode terminal, and a second narrow part between the sixth and seventh mount parts; and a snubber circuit connecting the first and second narrow parts.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: May 3, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hayato Nakano