Patents Examined by Eduardo A. Rodela
  • Patent number: 11004876
    Abstract: A method for producing a semiconductor chip (100) is provided, in which, during a growth process for growing a first semiconductor layer (1), an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer (1), such that a lateral variation of a material composition of the first semiconductor layer (1) is produced. A semiconductor chip (100) is additionally provided.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: May 11, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Christoph Eichler, Andre Somers, Harald Koenig, Bernhard Stojetz, Andreas Loeffler, Alfred Lell
  • Patent number: 10998254
    Abstract: A cooling system and method for using the cooling system are described. The cooling system includes a plurality of individual piezoelectric cooling elements spatially arranged in an array extending in at least two dimensions, a communications interface and driving circuitry. The communications interface is associated with the individual piezoelectric cooling elements such that selected individual piezoelectric cooling elements within the array can be activated based at least in part on heat energy generated in the vicinity of the selected individual piezoelectric cooling elements. The driving circuitry is associated with the individual piezoelectric cooling elements and is configured to drive the selected individual piezoelectric cooling elements.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: May 4, 2021
    Assignee: Frore Systems Inc.
    Inventors: Suryaprakash Ganti, Seshagiri Rao Madhavapeddy
  • Patent number: 10998234
    Abstract: Embodiments of the present invention are directed to a method that prevents punch-through of a bottom isolation layer and improves the quality of the source/drain epitaxial growth in a nanosheet semiconductor structure. In a non-limiting embodiment of the invention, a bottom isolation structure is formed over a substrate. The bottom isolation structure includes a tri-layer stack in a first region of the substrate and a bi-layer stack in a second region of the substrate. A nanosheet stack is formed over the bottom isolation structure in the first region of the substrate. A gate is formed over a channel region of the nanosheet stack.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Veeraraghavan Basker, Nicolas Loubet, Balasubramanian Pranatharthiharan
  • Patent number: 10998416
    Abstract: A laterally diffused metal oxide semiconductor device can include: a well region having a second doping type; a reduced surface field effect layer of a first doping type formed by an implantation process in a predetermined region of the well region, where a length of the reduced surface field effect layer is less than a length of the well region; a body region of the first doping type extending from a top surface of the well region into the well region; a drain portion of the second doping type extending from the top surface of the well region into the well region; and an insulating structure located between the body region and the drain portion, at least a portion of the insulating structure is located on the top surface of the well region.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: May 4, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Budong You, Hui Yu, Meng Wang, Yicheng Du, Chuan Peng, Xunyi Song
  • Patent number: 10991601
    Abstract: A method for treating a substrate includes a substrate treating step of treating the substrate by dispensing a treating liquid onto the substrate while rotating the substrate supported on a support plate in a processing space of a processing vessel and a vessel cleaning step of cleaning the processing vessel by dispensing a cleaning solution onto a jig while rotating the jig supported on the support plate. In the substrate treating step, the substrate is clamped to the support plate by a first vacuum pressure applied to the substrate. The vessel cleaning step includes a first clamping step of clamping the jig to the support plate by applying a second vacuum pressure to the jig. The first vacuum pressure and the second vacuum pressure are different from each other.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: April 27, 2021
    Assignee: SEMES CO., LTD.
    Inventors: Hwangsoo Park, Jun Ho You, Doo Young Oh, Jaehun Jeong
  • Patent number: 10978540
    Abstract: A method of manufacturing an organic light-emitting display apparatus includes: forming an auxiliary electrode including: a first conductive layer; and a second conductive layer disposed on the first conductive layer, the second conductive layer having a resistance higher than a resistance of the first conductive layer; forming a first intermediate layer on the auxiliary electrode; exposing the first conductive layer includes forming a first opening in the first intermediate layer and an opening portion in the second conductive layer by removing a portion of the first intermediate layer and a portion of the second conductive layer of the auxiliary electrode; and forming an opposite electrode on the first intermediate layer and the first conductive layer, wherein the opposite electrode is disposed contacting the first conductive layer exposed through the first opening of the first intermediate layer and the opening portion of the second conductive layer.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: April 13, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seho Lee, Taehyung Kim, Byoungseong Jeong
  • Patent number: 10978306
    Abstract: Methods, apparatuses, and systems related to forming a recess in a semiconductor structure are described. An example method includes etching the semiconductor structure using an elevated temperature dilution of acid and water. The method further includes etching the semiconductor structure using a room temperature wet etch of acid and water and a surface modification chemistry.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jerome A. Imonigie, Adriel Jebin Jacob Jebaraj, Brian J. Kerley, Sanjeev Sapra, Ashwin Panday
  • Patent number: 10971426
    Abstract: A semiconductor package is provided. The semiconductor package includes a first package comprising a first substrate and a first semiconductor chip, a second package arranged on the first package, and the second package comprising a second substrate and a second semiconductor chip, a first solder ball and a supporter layer arranged between the first package and the second package, and a dam arranged between the first package and the second package, the dam being in contact with a sidewall of the supporter layer, and the dam completely surrounding the sidewall of the supporter layer.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jae Wook Yoo
  • Patent number: 10971652
    Abstract: A semiconductor device comprises: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region, wherein the active region comprises multiple alternating well layers and barrier layers, the active region further comprises an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; an electron blocking region between the second semiconductor structure and the active region; a first aluminum-containing layer between the electron blocking region and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the first electron blocking layer; and a p-type dopant above the bottom surface of the active region and comprising a concentration profile comprising a peak shape having a peak concentration value, wherein the peak concentration value lies at a distance of between 15 nm and 60 nm from the upper surface of the active region.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: April 6, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Chia-Ming Liu, Chang-Hua Hsieh, Yung-Chung Pan, Chang-Yu Tsai, Ching-Chung Hu, Ming-Pao Chen, Chi Shen, Wei-Chieh Lien
  • Patent number: 10964671
    Abstract: A semiconductor device includes first and second chips that are stacked such that first surfaces of their element layers face each other. Each chip has a substrate, an element layer on a first surface of the substrate, pads on the element layer, and vias that penetrate through the substrate and the element layer. Each via is exposed from a second surface of the substrate and directly connected to one of the pads. The vias include a first via of the first chip directly connected to a first pad of the first chip and a second via of the second chip directly connected to a second pad of the second chip. The pads further include a third pad of the second chip which is electrically connected to the second pad by a wiring in the element layer of the second chip and to the first pad through a micro-bump.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: March 30, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Masaru Koyanagi
  • Patent number: 10964797
    Abstract: A semiconductor structure and a method for forming same, the forming method including: providing a base, where a dummy gate structure is formed on the base, an interlayer dielectric layer is formed on the base the dummy gate structure exposes, and the interlayer dielectric layer exposes the top of the dummy gate structure; forming an isolation structure in the interlayer dielectric layer between adjacent dummy gate structures, where the isolation structure further extends into the base; after forming the isolation structure, removing the dummy gate structure and forming a gate opening in the interlayer dielectric layer; filling a gate electrode material into the gate opening, where the gate electrode material further covers the top of the interlayer dielectric layer; and performing at least one polishing treatment to remove the gate electrode material above the top of the interlayer dielectric layer and retaining the gate electrode material in the gate opening as a gate electrode layer, where the step of the
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: March 30, 2021
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventors: Zhang Qing, Jin Yi, Jiang Li, Ji Deng Feng, Liu Lu
  • Patent number: 10964780
    Abstract: The semiconductor device includes a semiconductor substrate of first conductivity type including a cell area and a peripheral area surrounding cell area on a principal surface thereof, a first diffusion layer which is disposed in peripheral area, surrounds the cell area and has a second conductivity type different from the first conductivity type, an electrode which is disposed in the peripheral area, is in contact with the principal surface through an opening provided in an insulating member and is connected to the first diffusion layer, and a second diffusion layer of the first conductivity type which is formed on the principal surface of a region enclosed in the electrode distant from the first diffusion layer when viewed in a direction perpendicular to the principal surface and includes a linear portion having a first width and a curved portion having a portion with a second width greater than the first width.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: March 30, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Kenichi Furuta, Toshifumi Kobe, Toshiyuki Orita, Tsuyoshi Inoue, Tomoko Yonekura, Masahiro Haraguchi, Yoshinobu Takeshita, Kiyofumi Kondo
  • Patent number: 10964838
    Abstract: The present disclosure discloses a display substrate, a manufacturing method thereof, a display panel, and a display device. The display substrate includes a base substrate, a black matrix disposed on the base substrate, and a switching unit and an optical detection unit that are disposed at a side of the black matrix away from the base substrate. The optical detection unit is electrically connected to the switching unit, and an orthographic projection of at least one of the switching unit and the optical detection unit on the base substrate is located in an orthographic projection of the black matrix on the base substrate. Since the orthographic projection of at least one of the switching unit and the optical detection unit on the base substrate is located in the orthographic projection of the black matrix on the base substrate, the aperture ratio of the display substrate may increase.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: March 30, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guoying Wang, Zhen Song
  • Patent number: 10964801
    Abstract: A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Patent number: 10953319
    Abstract: A STT-MRAM comprises apparatus, a method of operating a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having a bias voltage controlled perpendicular anisotropy of a recording layer through an interlayer interaction to achieve a lower spin-transfer switching current. The anisotropy modification layer is under an electric field along a perpendicular direction with a proper voltage between a digital line and a bit line from a control circuitry, accordingly, the energy switch barrier is reduced in the spin-transfer recording while maintaining a high thermal stability and a good retention.
    Type: Grant
    Filed: January 12, 2014
    Date of Patent: March 23, 2021
    Inventor: Yimin Guo
  • Patent number: 10943781
    Abstract: A manufacturing method for a light emitting device, a light emitting device, and a hybrid light emitting device, the manufacturing method comprises the following steps: step S1: disposing a mask plate having a plurality of hollow portions on a substrate; step S2: applying, by using a solution method, ink on a surface of the substrate by using the hollow portions; and step S3: drying or solidifying the ink on the surface of the substrate to form a light emitting layer or a functional layer.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: March 9, 2021
    Assignee: Najing Technology Corporation Limited
    Inventors: Changgua Zhen, Xinyan Gu
  • Patent number: 10937836
    Abstract: A pixel arrangement structure and a display device are provided. The pixel arrangement structure includes a plurality of repeating units. The repeating units include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. Center points of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel in a same repeating unit form a quadrilateral. Four adjacent sub-pixels in adjacent repeating units constitute a shared pixel, and the shared pixel includes at most two sub-pixels belonging to the same repeating unit.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: March 2, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Zheng Wang
  • Patent number: 10937851
    Abstract: A method of manufacturing an organic light-emitting display apparatus includes: forming an auxiliary electrode including: a first conductive layer; and a second conductive layer disposed on the first conductive layer, the second conductive layer having a resistance higher than a resistance of the first conductive layer; forming a first intermediate layer on the auxiliary electrode; exposing the first conductive layer includes forming a first opening in the first intermediate layer and an opening portion in the second conductive layer by removing a portion of the first intermediate layer and a portion of the second conductive layer of the auxiliary electrode; and forming an opposite electrode on the first intermediate layer and the first conductive layer, wherein the opposite electrode is disposed contacting the first conductive layer exposed through the first opening of the first intermediate layer and the opening portion of the second conductive layer.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: March 2, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seho Lee, Taehyung Kim, Byoungseong Jeong
  • Patent number: 10937958
    Abstract: A method of forming a magnetoresistive element comprises of forming a novel Boron-absorbing cap layer provided on the top surface of an amorphous CoFeB (or CoB, FeB) ferromagnetic recording layer. As the magnetoresistive film is thermally annealed, a crystallization process occurs to form bcc CoFe grains having epitaxial growth with (100) plane parallel to the surface of the tunnel barrier layer as Boron elements migrate into the novel Boron-absorbing cap layer. Removing the top portion of the Boron-absorbing cap layer by means of sputtering etch or RIE etch processes followed by optional oxidization process, a thin thermally stable portion of cap layer is remained on top of the recording layer with low damping constant. Accordingly, a reduced write current is achieved for spin-transfer torque MRAM application.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: March 2, 2021
    Inventor: Yimin Guo
  • Patent number: 10930763
    Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Chieh Su, Zhi-Chang Lin, Ting-Hung Hsu, Jia-Ni Yu, Wei-Hao Wu, Yu-Ming Lin, Chih-Hao Wang