Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

Abstract: A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

Abstract: Integrated circuit devices may include a plurality of word line structures and a plurality of insulating films that are stacked alternately. Sides of the plurality of word line structures and the plurality of insulating films define a side of a channel hole extending through the plurality of word line structures and the plurality of insulating films. The devices may also include a blocking dielectric film on the side of the channel hole, and a plurality of charge storage films on the blocking dielectric film and on the sides of the plurality of word line structures, respectively. Each of the plurality of charge storage films may include a first charge storage film and a second charge storage film sequentially stacked on a respective one of the sides of the plurality of word line structures. A surface of the second charge storage film may include a recess in a middle portion thereof.

Abstract: An integrated circuit read only memory (ROM) structure includes a first ROM transistor with a first gate electrode, a first source, and a first drain, and a second ROM transistor with a second gate electrode, a second source, and a second drain. A drain conductive line is over the first drain and the second drain, and is between the first drain and the second drain. The first drain, the drain conductive line and the second drain are between the first gate electrode and the second gate electrode, and a first trench isolation structure electrically isolates the first drain from the first source is below the first gate electrode.

Abstract: A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.

Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

Abstract: Provided are a flexible body and a method for controlling the flexible body to deform. The flexible body comprises one or more flexible units, wherein each of the flexible units comprises: a first electrode, a second electrode, an electroactive polymer layer, and a thin film transistor, wherein a source electrode or a drain electrode of the thin film transistor is electrically connected to the second electrode. The first electrode and the second electrode are configured to provide an electric field acting on the electroactive polymer layer, and the electroactive polymer layer is configured to deform in response to the electric field provided by the first electrode and the second electrode.

Abstract: A cooling system and method for using the cooling system are described. The cooling system includes a plurality of individual piezoelectric cooling elements spatially arranged in an array extending in at least two dimensions, a communications interface and driving circuitry. The communications interface is associated with the individual piezoelectric cooling elements such that selected individual piezoelectric cooling elements within the array can be activated based at least in part on heat energy generated in the vicinity of the selected individual piezoelectric cooling elements. The driving circuitry is associated with the individual piezoelectric cooling elements and is configured to drive the selected individual piezoelectric cooling elements.

Abstract: A semiconductor device includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor connected to an output node of the first PMOS and NMOS transistors. The first PMOS transistor includes first nanowires, first source and drain regions on opposite sides of each first nanowire, and a first gate completely surrounding each first nanowire. The first NMOS transistor includes second nanowires, second source and drain regions on opposite sides of each second nanowire, and a second gate extending from the first gate and completely surrounding each second nanowire. The second NMOS transistor includes third nanowires, third source and drain regions on opposite sides of each third nanowire, and a third gate, separated from the first and second gates, and completely surrounding each third nanowire. A number of third nanowires is greater than that of first nanowires. The first and second gates share respective first and second nanowires.

Abstract: Disclosed is a field-effect transistor and a method for manufacturing a field-effect transistor. The method comprises: forming an NMOSFET region and a PMOSFET region on a substrate; forming a hard mask on the NMOSFET region and the PMOSFET region, and patterning through the hard mask; forming a multiple of stacked nanowires in the NMOSFET region and a multiple of stacked nanowires in the PMOSFET region; forming a first array of nanowires in the NMOSFET region and a second array of nanowires in the PMOSFET region; and forming an interfacial oxide layer, a ferroelectric layer, and a stacked metal gate in sequence around each of the nanowires included in the first array and the second array. Wherein the NMOSFET region and the PMOSFET region are separated by shallow trench isolation.

Abstract: A chip package including a first semiconductor die, a support structure and a second semiconductor die is provided. The first semiconductor die includes a first dielectric layer and a plurality of conductive vias, the first dielectric layer includes a first region and a second region, the conductive vias is embedded in the first region of the first dielectric layer; a plurality of conductive pillars is disposed on and electrically connected to the conductive vias. The second semiconductor die is stacked over the support structure and the second region of the first dielectric layer; and an insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.

Abstract: A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

Abstract: A power semiconductor module includes an insulating circuit substrate; a printed circuit board disposed over the insulating circuit substrate; and a plurality of terminals each having a rod-shaped portion and including a first protrusion and a second protrusion each protruding laterally form a side face of the rod-shaped portion; wherein at least one of the plurality of terminals is inserted to one of the through-holes of the printed circuit board and is locked to the one of the through-holes via the first protrusion, and wherein at least another one of the plurality of terminals is inserted to another one of the through-holes of the printed circuit board and is locked to said another one of the through-holes via the second protrusion, and an end of the at least another one of the plurality of terminals is electrically connected to a conductive plate on the insulating circuit substrate.

Abstract: An organic EL element includes a pixel electrode, a light emitting function layer that is formed on the pixel electrode, an electron injection layer formed on the light emitting function layer, and a counter electrode that is formed on the electron injection layer and that has semi-transmissive reflectivity, in which the counter electrode contains a reductive material that reduces material of the electron injection layer and Ag with atomic ratio of 75% or more, and an adsorption layer is formed on the counter electrode.

Abstract: An apparatus and method for debonding a pair of bonded wafers are disclosed herein. In some embodiments, the debonding apparatus, comprises: a wafer chuck having a preset maximum lateral dimension and configured to rotate the pair of bonded wafers attached to a top surface of the wafer chuck, a pair of circular plate separating blades including a first separating blade and a second separating blade arranged diametrically opposite to each other at edges of the pair of bonded wafers, wherein the first and the second separating blades are inserted between a first and a second wafers of the pair of bonded wafers, and at least two pulling heads configured to pull the second wafer upwardly so as to debond the second wafer from the first wafer.

Abstract: There is provided a technique that includes: loading a substrate having a metal film composed of a single metal element formed on a surface of the substrate into a process chamber; generating reactive species by plasma-exciting a processing gas containing hydrogen and oxygen; and modifying the metal film by supplying the reactive species to the substrate, wherein in the act of modifying the metal film, the metal film is modified such that a crystal grain size of the metal element constituting the metal film is larger than that before performing the act of modifying the metal film.

Abstract: A display device including: a substrate element including a base layer, a circuit layer, and a device layer, the base layer forming a plane defined by a first direction and a second direction perpendicular to each other; an encapsulation element provided on the substrate element to seal the device layer; a sealing element provided along edges of the encapsulation element to connect the encapsulation and substrate elements to each other; an optical element provided on the encapsulation element; a window element provided on the substrate element; an adhesive element provided between the optical and window elements to connect the optical element to the window element; and a filling element provided between the window element and the substrate element, wherein the filling element is spaced apart from the optical element and the adhesive element, and is overlapped with the sealing element when viewed in a direction normal to the plane.

Abstract: A semiconductor package includes a die pad, a semiconductor die mounted on the die pad and comprising a first terminal facing away from the die pad and a second terminal facing and electrically connected to the die pad, an interconnect clip electrically connected to the first terminal, an encapsulant body of electrically insulating material that encapsulates the semiconductor die and the interconnect clip, and a first opening in the encapsulant body that exposes a surface of the interconnect clip, the encapsulant body comprises a lower surface, an upper surface opposite from the lower surface, and a first outer edge side extending between the lower surface and the upper surface, and the first opening is laterally offset from the first outer edge side.

Abstract: A piezoelectric sensor includes: a lower substrate; a plurality of sensing transistors that are disposed on the lower substrate; a lower electrode that is disposed to cover the plurality of sensing transistors; a piezoelectric material layer that is disposed on the lower electrode; and an upper electrode that is disposed on the piezoelectric material layer. The piezoelectric material layer has a first thickness in a plurality of first areas in which the plurality of sensing transistors are disposed and has a second thickness which is greater than the first thickness in a second area in which the plurality of sensing transistors are not disposed. Accordingly, it is possible to further accurately and finely detect various types of biometric information.

Abstract: A power module has a plurality of packaged power semiconductors, a printed circuit board, a heat sink, and possibly a sealing compound. The power semiconductors have electrically conductive connection elements and heat removal areas on respective outer sides. The power semiconductors are arranged on a cooling surface of the heat sink and has its heat removal area connected to the cooling surface of the heat sink to conduct heat, and the printed circuit board is arranged on a side of the power semiconductors that is opposite the heat sink in an orthogonal direction, wherein the connection elements of the power semiconductors make electrical contact with pads on the printed circuit board regions, for example, laterally beside an edge of the heat sink, in which a projection of the heat sink onto the printed circuit board in the orthogonal direction does not cover the connection elements.