Abstract: First and second trenches are provided in a semiconductor body. A mesa dividing structure is provided between the first and second trenches and comprises non-semiconductor material. A first semiconductor mesa is provided between the first trench and the non-semiconductor material of the mesa dividing structure. The first semiconductor mesa includes emitter, body and drift regions. The first and second trenches are formed by a masked etching technique with a minimum trench separation distance, and the first semiconductor mesa is provided to have a lateral width that is less than the minimum trench separation distance.

Abstract: Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.

Abstract: A semiconductor device includes: a semiconductor substrate; a first transistor provided at an upper surface of the semiconductor substrate; and a first capacitor provided above the first transistor and connected to a gate of the first transistor. A tunnel current is able to flow between the gate and the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor substrate having a drift region, and an edge terminal structure portion provided between the active region and an end portion of the semiconductor substrate on an upper surface of the semiconductor substrate. The edge terminal structure portion includes a plurality of guard rings of a second conductivity type which are in contact with the upper surface, and a high concentration region of the first conductivity type which has a higher doping concentration than the drift region and is provided, between adjacent two of the guard rings, from a position shallower than lower ends of the guard rings to a position deeper than the lower ends of the guard rings. Each of the guard rings has a region that is not covered by the high concentration region as viewed from a lower surface side.

Abstract: A method of fabricating air gaps in advanced semiconductor devices for low capacitance interconnects. The method includes exposing a substrate to a gas pulse sequence to deposit a material that forms an air gap between raised features.

Abstract: A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

Abstract: A semiconductor power device has: a die, with a front surface and a rear surface, and with an arrangement of projecting regions on the front surface, which define between them windows arranged within which are contact regions; and a package, which houses the die inside it. A metal frame has a top surface and a bottom surface; the die is carried by the frame on the top surface; an encapsulation coating coats the frame and the die. A first insulation multilayer is arranged above the die and is formed by an upper metal layer, a lower metal layer, and an intermediate insulating layer; the lower metal layer is shaped according to an arrangement of the projecting regions and has contact projections, which extend so as to electrically contact the contact regions, and insulation regions, interposed between the contact projections, in positions corresponding to the projecting regions.

Abstract: Disclosed in the present invention are a method for manufacturing a thin-film transistor, an array substrate, and a display device. The method includes: forming a buffer layer on a substrate; forming a polysilicon layer on the buffer layer; performing a patterning process on the polysilicon layer, to form an active layer; depositing a gate insulating layer on the active layer; depositing a gate metal layer on the gate insulating layer, and performing dry etching on the gate metal layer by using the patterning process and by using a gas containing CO as an etching gas, to form a gate; performing ion implantation on the active layer by using the gate as a mask, to form a source region and a drain region; and depositing a passivation layer on the gate, forming through holes in the gate insulating layer and the passivation layer, and manufacturing a source and a drain.

Abstract: An integrated circuit includes a photodetector. The photodetector includes a circular optical grating formed in an annular trench in a semiconductor substrate. The circular optical grating includes dielectric fins and photosensitive fins positioned in the annular trench. The circular optical grating is configured to receive incident light and to direct the incident light around the annular trench through the dielectric fins and the photosensitive fins until the light is absorbed by one of the photosensitive fins.

Abstract: Disclosed is a field-effect transistor and a method for manufacturing a field-effect transistor. The method comprises: forming an NMOSFET region and a PMOSFET region on a substrate; forming a hard mask on the NMOSFET region and the PMOSFET region, and patterning through the hard mask; forming a multiple of stacked nanowires in the NMOSFET region and a multiple of stacked nanowires in the PMOSFET region; forming a first array of nanowires in the NMOSFET region and a second array of nanowires in the PMOSFET region; and forming an interfacial oxide layer, a ferroelectric layer, and a stacked metal gate in sequence around each of the nanowires included in the first array and the second array. Wherein the NMOSFET region and the PMOSFET region are separated by shallow trench isolation.

Abstract: A method includes providing a semiconductor substrate having a first side and a second side opposite to the first side, forming at least one radio frequency device at the first side; thinning the semiconductor substrate from the second side; and processing the second side of the thinned semiconductor substrate to reduce leakage currents or to improve a radio frequency linearity of the at least one radio frequency device.

Abstract: A device substrate comprising a substrate, a first pad, a second pad, a plurality of first power lines, a plurality of second power lines, and a plurality of control units is provided. The first pad is disposed on the first side of the device substrate. The second pad is disposed on the second side of the device substrate. The second side is opposite the first side. The first power lines are electrically connected to the first pad. The second power lines are electrically connected to the second pad. The control unit is electrically connected to at least one of the first power line and the second power line. The first pad does not overlap the second pad in a first direction perpendicular to the first side or in a second direction perpendicular to the second side. A display panel is also provided. A tiled display is also provided.

Abstract: According to an embodiment, a sensor package includes an electrically insulating substrate including a cavity in the electrically insulating substrate, an ambient sensor, an integrated circuit die embedded in the electrically insulating substrate, and a plurality of conductive interconnect structures coupling the ambient sensor to the integrated circuit die. The ambient sensor is supported by the electrically insulating substrate and arranged adjacent the cavity.

Abstract: According to one aspect of the technique described herein, there is provided a technique including: forming a film on a substrate by performing a cycle a predetermined number of times, wherein the cycle includes sequentially performing: (a) supplying source gas to a substrate accommodated in a reaction tube; (b) exhausting the source gas remaining in the reaction tube through an exhaust pipe connected to the reaction tube; (c) supplying a reactive gas reacting with the source gas to the substrate; and (d) exhausting the reactive gas remaining in the reaction tube through the exhaust pipe, wherein at least in (a) and (c), a temperature of the reaction tube is set to a first temperature lower than a thermal decomposition temperature of the source gas and higher than a condensation temperature of the source gas and a temperature of the exhaust pipe is set to a second temperature equal to or higher than the first temperature.

Abstract: A chip package including a first semiconductor die, a support structure and a second semiconductor die is provided. The first semiconductor die includes a first dielectric layer and a plurality of conductive vias, the first dielectric layer includes a first region and a second region, the conductive vias is embedded in the first region of the first dielectric layer; a plurality of conductive pillars is disposed on and electrically connected to the conductive vias. The second semiconductor die is stacked over the support structure and the second region of the first dielectric layer; and an insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.

Abstract: A semiconductor package includes a mounting substrate, a first semiconductor chip on the mounting substrate and electrically connected to the mounting substrate, a heat dissipation element on an upper surface of the first semiconductor chip, where the heat dissipation element comprises a sidewall comprising an inclined surface and an upper surface directly connected to the inclined surface, and a package molding portion on the mounting substrate and the inclined surface of the heat dissipation element. The package molding portion exposes at least a portion of the upper surface of the heat dissipation element, the upper surface of the heat dissipation element is parallel to the upper surface of the first semiconductor chip, and an angle formed by the upper surface of the heat dissipation element and the inclined surface of the heat dissipation element is an obtuse angle.

Abstract: Methods of producing a self-aligned structure comprising a metal chalcogenide are described. Some methods comprise forming a metal-containing film in a substrate feature and exposing the metal-containing film to a chalogen precursor to form a self-aligned structure comprising a metal chalcogenide. Some methods comprise forming a metal-containing film in a substrate feature, expanding the metal-containing film to form a pillar and exposing the pillar to a chalogen precursor to form a self-aligned structure comprising a metal chalcogenide. Some methods comprise directly forming a metal chalcogenide pillar in a substrate feature to form a self-aligned structure comprising a metal chalcogenide. Methods of forming self-aligned vias are also described.

Abstract: Integrated circuit devices may include a plurality of word line structures and a plurality of insulating films that are stacked alternately. Sides of the plurality of word line structures and the plurality of insulating films define a side of a channel hole extending through the plurality of word line structures and the plurality of insulating films. The devices may also include a blocking dielectric film on the side of the channel hole, and a plurality of charge storage films on the blocking dielectric film and on the sides of the plurality of word line structures, respectively. Each of the plurality of charge storage films may include a first charge storage film and a second charge storage film sequentially stacked on a respective one of the sides of the plurality of word line structures. A surface of the second charge storage film may include a recess in a middle portion thereof.

Abstract: A semiconductor device includes a semiconductor substrate SUB, a semiconductor layer EP formed on the semiconductor substrate SUB, a buried layer PBL formed between the semiconductor layer EP and the semiconductor substrate SUB, an isolation layer PiSO formed in the semiconductor layer EP so as to be in contact with the buried layer PBL, and a conductive film FG formed over the isolation layer PiSO via an insulating film IF, whereby a first capacitive element including the conductive film FG as an upper electrode, the insulating film IF as a capacitive insulating film, and the isolation layer PiSO as a lower electrode, is formed over the semiconductor substrate SUB.

Abstract: A method for manufacturing a light emitting device includes: providing a wafer that includes, successively from an upper face side, an electrode structure that includes multilayer wiring, a semiconductor layer electrically connected to the electrode structure, and a growth substrate; bonding the wafer to a support substrate; exposing the semiconductor layer by removing the growth substrate from the wafer; separating the semiconductor layer into a plurality of light emitting elements, which comprises forming grooves on a semiconductor layer side surface of the wafer; and forming a phosphor layer having protrusions and recesses at a surface thereof such that the phosphor layer covers surfaces of the light emitting elements, which comprises: forming a coating film on surfaces of the light emitting elements by applying a slurry comprising phosphor particles contained in a solvent, and vaporizing the solvent in the coating film to form the phosphor layer.