Abstract: A MOS type semiconductor device including capacitors connected in series between the source electrode and the peripheral electrode. Alternately, a MOS type semiconductor device including constant voltage diodes connected in series between the source electrode and the peripheral electrode.

Abstract: The inventive multilayer semiconductor integrated circuit has a columnar semiconductor region provided between adjacent two layers and a control electrode provided in the vicinity of the columnar semiconductor region. The transference of a signal between the adjacent two layers is carried out through the columnar semiconductor region the electric conductivity of which is controlled by a control signal applied to the control electrode. That is, the area corresponding to the columnar semiconductor region functions as an active element.

Abstract: Trenches (2) are formed in three rows in a major surface of a semiconductor substrate (1). The major surface of the semiconductor substrate (1) including the inside of the trenches (2) is thermally oxidized. A first oxide film (4) filling the trenches is formed by thermal oxidation, a second oxide film (4) is formed in a region of the semiconductor substrate interposed between the trenches, and a third oxide film (3) is formed on the major surface of the semiconductor substrate excluding the region interposed between the trenches. The upper surfaces of the first, second and third oxide films (3, 4) are etched away to be flattened, whereby the semiconductor substrate (1) is exposed so that an interconnection (5) is formed on the remaining first and second oxide films (4).

Abstract: In a homo-junction bipolar transistor suitable for a low temperature operation below 200 K. (particularly below 77 K.), the maximum value of the impurity concentration of an intrinsic base region is set to be at least 1.times.10.sup.18 /cm.sup.3 and the impurity concentration of an emitter region is set to a value lower than this maximum value. Thus, a base resistance can be reduced and a high speed operation becomes possible. Furthermore, bandgap narrowing develops in the intrinsic base region and a common-emitter current gain in the low temperature operation can be kept at a sufficient value. When this homo-junction bipolar transistor is formed together with complementary insulated gate field effect transistors on the surface of a semiconductor substrate, there can be obtained a Bi-CMOS device capable of a high speed operation even in the low temperature operation.

Abstract: According to the present invention, roughness are formed on the surface of III-V group compound semiconductor to prevent total reflection, and SiNx film is formed on rough surface. This makes it possible to increase external quantum efficiency by surface roughness. Further, bond strength is increased because SiNx film is furnished on the roughness. As the result, the detachment of SiNx film is prevented, moisture resistant property is improved, and service life of LED is extended by preventing oxidation.

Abstract: An avalanche transistor has a heterojunction emitter-base junction. The avalanche transistor includes a spacer layer provided between an emitter layer and a base layer. The spacer layer has an energy band gap between that of the base layer and that of the emitter layer, a carrier concentration lower than that of the base layer, and a thickness so that the whole spacer layer becomes a depletion layer at thermal equillibrium so that a neutral region is produced in the spacer layer at a voltage lower than the threshold voltage of the emitter-base junction. Thus, the same element is both bistable with the base current as a parameter and has an S-shaped negative differential resistance with the base voltage as a parameter.

Abstract: A compact, high speed EEPROM is disclosed. The design features mirror-image pairs of cells with a common junction buried under a thick oxide. The oxide also supports a portion of the control and floating gates. A single erase gate, also above the oxide, is capable of erasing two rows of cells at once. Each cell also has a second junction which contacts the semiconductor substrate surface. The second junction has a conductive landing pad which facilitates small cell size.

Abstract: In a semiconductor integrated circuit device using a field effect transistor, such as MOS, having the end part of the drain overlapped with the gate electrode, a novel gate-drain overlap structure of excellent performance and reliability is presented. A manufacturing method for this device is also presented.

Abstract: A method for manufacturing a Bi-CMOS device by preparing both of bipolar and MOS standard cells in a library is provided. A substrate of a first conductivity type is provided and a plurality of buried layers of a second conductivity type are formed on selected locations of the substrate. Then an epitaxial layer of the first conductivity type is formed on the substrate covering the buried layers. Then a plurality of wells of the second conductivity type are formed in the epitaxial layer such that each of the wells extends through the epitaxial layer from the top surface to at least a portion of the corresponding buried layer to thereby define a plurality of electrically isolated islands in the epitaxial layer. Then a bipolar transistor is formed in at least one of the islands with a MOS transistor formed in at least another of the islands.

Abstract: An image sensor for sequentially reading signals from photoelectric converting elements disposed in a matrix and formed on a substrate in which both an image sensor and a photometry sensor are incorporated on the same substrate. The sensor includes a light-shielding layer disposed over the area of the substrate except the area of the photoelectric elements, the light-shielding layer forming a lower electrode. A pn-junction photodiode layer is disposed over the light-shielding layer, and an upper transparent electrode layer is disposed at least over the photodiode layer. The upper transparent electrode layer is divided into a plurality of pattern areas. If desired, at least one of the pattern areas of the upper transparent electrode layer may be further divided into a plurality of very small areas and color filters formed over the very small areas.

Abstract: Electronic device packaging structures useful for electrically interconnecting an electronic device to a substrate. The structure contains at least two metallization layers with dielectric layers between adjacent to metallization layers. The dielectric layers can have variable thickness. Beam leads can project inwardly in cantilevered fashion over a central aperture through the dielectric layers. The inner ends of the beam leads lie substantially in one plane and can be bonded to contact pads on integrated circuit electronic devices. Beam leads can project outwardly from the metallization layers over outer edges of the dielectric layers for bonding to contact pads on a substrate. Signal leads on metallization layers can be symmetrically arranged between ground and voltage leads to provide optimal impedance properties. These structures are useful for tape automated bonding applications.

Abstract: A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.

Abstract: A dual-polarity nonvolatile MOS analog memory cell is disclosed that comprises two pairs of complementary metal oxide field effect transistors. Each pair includes a p-channel and an n-channel transistor. The gates of each transistor are all operably coupled in common to form a common floating gate. The sources of the transistors of the first transistor pair are operably coupled to a common ground. The sources of the second pair of transistors are operably coupled together to form an output junction. Positive voltage applied to the drain of the n-channel transistor of the first transistor pair causes a positive analog value to be stored in memory when there previously was no value stored in memory, or increases a value previously stored in memory. Negative voltage applied to the drain of the p-channel transistor of the first transistor pair causes a negative analog value to be stored in memory when there previously was no value stored in memory, or decreases a value previously stored in memory.

Abstract: A process for the formation of pillars (28) in connection with the fabrication of a semiconductor device (10) is disclosed. The process first aligns a lead pattern (30) with an existing structure (24) in the semiconductor device (10). Next, the process aligns a pillar pattern (32) with the lead pattern (30). These two patterns (30, 32) are then transferred downward into respective conductive layers (26, 28) of the semiconductor device (10). An insulating layer (34) is deposited over the conductive layers (26, 28) and etched-back to expose a portion of the pillar (28). A conductive layer (42) is applied over the exposed pillar (28).

Abstract: A lateral conduction high power MOSFET chip with integrated control circuits in disclosed for high-side switching applications. A first surface field reduction region disposed between drain and source regions extends from the chip surface and into its body and has a charge density of about 1.times.10.sup.12 ions/cm.sup.2. A second surface field reduction region extends below the first region and the source and drain regions and has a charge density of from about 1.5.times.10.sup.12 to 2.0.times.10.sup.12 ions/cm.sup.2. A substrate extends below the second region and is isolated from both drain and source regions to enable the use of the device as a high-side switch.

Abstract: The invention provides a nonvolatile semiconductor memory component comprising: field region of thick oxide, the first and second active regions surrounded with the field region, the first and second gate insulating layers on the first and second active regions, the first gate of a low resistance formed on the first and second gate insulating layer, the third insulating layer on the first gate of a low resistance the second gate of a low resistance formed on the third insulating layer, the channel region below the first gate insulating layer formed by the first gate, and the highly doped drain and source separated by channel region opposite to the type of the substrate. In addition, the process for forming the transistor with one channel and the substrate diffusion can be achieved on the semiconductor substrate or opposite type well formed on the semiconductor substrate. Programming at a low voltage may be possible and the reliability characteristics of the cell may be improved according to present invention.

Abstract: A resonant tunneling device includes a superlattice layer which includes an interlaminated structure of three semiconductor layers each having a narrow energy bandgap and serving as a quantum well layer and four semiconductor layers each having a wide energy bandgap and serving as a barrier layer and in which three quantum levels are formed in the quantum well layers. A resonant tunneling phenomenon produced between the quantum levels provides peak current values which are substantially equal to each other, peak voltages which can be set independently from each other, and peak-to-valley (P/V) ratios which are high, thereby realizing a resonant tunneling device which has an excellent performance as a three state logic element for a logic circuit. By increasing the number of quantum well layers and the number of barrier layers, a logic element of four or more states can be realized for a logic circuit.

Abstract: The disclosure concerns integrated circuits and, more particularly, their protection against electrostatic discharges. To protect a metallized pad in a CMOS circuit on an N substrate with P wells, an NPN type lateral bipolar transistor formed in a P-type well is used. The emitter is an N+ region connected to the pad. The collector is an N+ region connected to a metallization which is itself connected, like the substrate N, to the high supply voltage Vcc of the circuit. The well is taken to the potential of the pad to be protected by means of an ohmic contact by a P+ surface diffusion of the well. In the preferred embodiment of the invention, the region that acts as a collector includes a part extending laterally outside the P well, and it is in this external part that the contact with the metallization occurs. The contact is at a sufficient distance from the well for there to be no risk of damage to the trench/substrate junction when the density of current flowing through the metallization is high.

Abstract: A contact image sensor for use in facsimile machines is described. A light window is opened through a photosensitive semiconductor film deposited on a glass sustrate. Light rays are passed through the light window, reflected on an original and absorbed by the semiconductor film in order to produce image signals containing visual information of the original. Provided on the light incident side of the semiconductor film is a light blocking electrode which prevents incident light rays from directly entering the semiconductor film therethrough without reflection on the original. The opposing electrode formed on the other side of the semiconductor film is made of a transparent film covering the side surface of the light window. The opposing electrode on the side surface functions to eliminate noise signals caused by undesirable light rays incident through the side surface, which otherwise, would deteriorate the output signals of the image sensor.

Abstract: A CMOS inverter which comprises a series of connected p-channel and n-channel MOS FETs of which gate electrodes, drain contact electrodes, and voltage source lines are arranged on different insulation layers stacked on each other. The drain contact electrodes are formed by a conductor, including a silicide of high melting point metal, such as, tungsten or molybdenum. They are coated by an insulation layer over which the voltage source lines and signal lines for transferring output to a succeeding stage are arranged. By doing so, the device area is decreased, and the substrate can be reflowed to smooth the surface of the insulator so as to prevent disconnecting of the wirings.