Abstract: A method for grounding or electrically biasing an integrated circuit chip without using a conductive die attach material comprises affixing the chips to a substrate using a thermoplastic polyimide adhesive. A metallization layer electrically connects the sides of the chips, which act as grounding surfaces, to a biased or grounded conductive layer on the substrate. The top surfaces of the integrated circuit chips which include the interconnection pads are protected against undesired metallization by a removable protective layer while the metallization layer is applied. Metal electroplated on the metallization layer serves the functions of a heat sink for the chip and a ground plane between chips.

Abstract: A bipolar transistor includes a p-type external base region formed on the major surface of an n-type semiconductor substrate, a plurality of p-type internal base regions formed to be surrounded by the external base region, and emitter regions of a first conductivity type respectively formed in the internal base regions. An oxide film and a nitride film, stacked on each other, extend outward from an outer peripheral portion of the external base region on the major surface of the semiconductor substrate, and define openings therein. A p-type semiconductor film is formed on the external base region in the openings. A first conductive layer having a p-type semiconductor is formed on the nitride film and the semiconductor film. Side-wall-like oxide films are formed on side wall portions, of the semiconductor film and the first conductive layer, opposite to the emitter regions.

Abstract: An insulated lead frame is disclosed. The lead frame has a first plurality of lead fingers and a second plurality of lead fingers. It also has a power supply bus lying between the first plurality of lead fingers and the second plurality of lead fingers. An insulating strip lies on a face of the power supply bus near an edge of the face. Examples of a suitable dielectric strip are an adhesive type tape, such as a polyimide tape, and a nonconductive liquid, such as liquid polyimide. An insulated lead frame is useful in the manufacture of packaged semiconductor integrated circuit devices to reduce the possibility of wire bond shorting to the power supply busses. One example is a dynamic random access memory, DRAM, die having centrally disposed bonding pads mounted to a lead on chip lead frame.

Abstract: A semiconductor integrated circuit device including a semiconductor substrate having a main surface; a first conductive region formed on the main surface; a second conductive region formed on the main surface, spaced apart from the first conductive region and to be electrically connected to the first conductive region; and a capacitor having a storage node connecting the first and second conductive regions. The storage node serves to connect the first and second conductive regions and simultaneously stores charges. In other aspects of the invention, there are provided a memory cell having a structure described above, and a method of manufacturing the above-described semiconductor integrated circuit device.

Abstract: An improved VLSI or ULSI structure and a method of forming the same are provided. The structure starts with a base member having a plurality of supports formed thereon and extending upwardly therefrom. A selectively removable material is deposited on the base member and around the supports. An insulating cap is formed over the supports and the removable material. Access openings are provided through the cover (or base) and the removable material is removed through the access openings. Thereafter a partial vacuum is formed in the space evacuated by the removable material, and the access openings sealed to provide a dielectric medium around the supports and between the base and cap member having a dielectric constant of less than 2.0.

Abstract: A thin diode device comprises a diode structure (14), for example an amorphous silicon p-i-n structure, carried on a substrate (12), a pair of conductive layers (16,20) contacting the opposing sides of the structure, and passivating material surrounding the structure which comprises an insulating layer (22) adjacent the structure and a light-absorbing semi-insulating semiconductor layer (24), for example comprising amorphous silicon material, over the insulating layer to reduce photocurrent produced in the diode structure due to incident light. The diode devices are particularly suited for use in an active matrix addressed liquid crystal display device having an array of display elements (30), the devices serving as switches, for example in a diode ring configuration, connected in series between respective display element electrodes and associate address conductors (32).

Abstract: A thin-film transistor circuit (10) has a main thin-film transistor (Trl) and an input gate protection device (11) formed by first and second subsidiary thin-film transistors (Tr2) and (Tr3) connected in series and to the gate electrode (1) of the main thin-film transistor (Tr1). The gates (4 and 7) and one of the main electrodes (5 and 9) of each of the first and second subsidiary thin-film transistors (Tr2 and Tr3) are connected. The other main electrodes (6 and 8) of the first and second subsidiary thin-film transistors (Tr2 and Tr3) are connected together so that only one of the first and second subsidiary thin-film transistors (Tr3 and Tr3) conducts when a voltage above a threshold voltage is applied to the gate electrode (1) of the main thin-film transistor (Tr1).

Abstract: A field effect transistor including a gate electrode, a source electrode and a drain electrode which are formed on a major surface of a silicon substrate. An impurity contained in the source electrode and the drain electrode is diffused into the silicon substrate by heat treatment of thereby form source and drain areas of the transistor. The source electrode and the drain electrode are electrically insulated from the gate electrode by a side-wall insulating film. The side-wall insulating film and the gate insulating film are formed by separate steps, so can each be formed in optimum thickness.

Abstract: A heterojunction field effect transistor structure having a plurality of vertically stacked field effect devices. Two or more devices having electrically independent source and drain regions are formed such that a single gate electrode controls current flow in each of the devices. Each of the vertically stacked FETs have electrically isolated channel regions which may be controlled by a single gate electrode. Vertically stacked devices provide greater device packing density.

Abstract: An insulated gate field effect transistor comprises a non-single-crystalline semiconductor layer formed on a substrate, a gate electrode is formed on a portion of the surface of said semiconductor layer, and a gate insulated film is disposed between said gate electrode and said semiconductor layer. A non-single-crystalline channel region is defined within said semiconductor layer just below said gate electrode. A source region and a drain region are transformed from and defined within said semiconductor layer immediately adjacent to said channel region in an opposed relation, said source and drain regions being crystallized to a higher degree than that of said channel region by selectively irradiating portions of said semiconductor layer using said gate electrode as a mask.

Abstract: An aligned metal gate is formed on a semiconductor substrate surface between a source region and a drain region of the substrate. Precise alignment of the boundaries of the gate with the boundaries of the source and drain regions is obtained by shadowing a photoresist coating over metal deposited onto the substrate surface, while photochemically dissociating the photoresist over metal deposited onto an oxide layer formed over the source and drain regions of the substrate. The developed photoresist is removed, and the undeveloped photoresist is hard-baked to serve as a protective coating for the metal between the source and drain regions. The metal over the source and drain regions is etched away, leaving the metal between the source and drain regions to function as an electronic gate.

Abstract: A vertical CMOS semiconductor device and a method of making the device. A polysilicon gate post rises normal to a surface of a substrate. An annular transistor encircles the gate post. The transistor consists of a channel layer sandwiched between a pair of source/drain layers. Each layer lies directly above the layer beneath, with the gate post projecting up through the layers. One or more additional transistors of the same or differing polarities may be stacked above the first transistor, the various transistors being suitably spaced apart from each other. Electrical connections with the gate post and the various source/drain layers may be configured to provide a complementary inverter or some other circuit as desired.

Abstract: In this invention, a distributed constant line on a microwave IC is formed of a Schottky metal, and a semiconductor conductive layer contacting the distributed constant line at least at one position and an ohmic contact electrode contacting the semiconductor conductive layer are arranged. According to this invention, characteristics of ICs can be optimized against a variation in elements combined with a circuit comprising the distributed constant line after the manufacture of ICs.

Abstract: According to the present invention, an improved chip and leadframe package assembly and method of making the same is provided. The package assembly is comprised of a metal leadframe having a chip bond pedestal centrally located and a plurality of discrete leads surrounding the pedestal. An I/C (integrated circuit) semiconductor chip is mounted on the pedestal, the chip having a plurality of connection or bonding pads disposed around the periphery. An interposer having a layer of dielectric material and discrete metal lines formed thereon is mounted on an apron of the chip bonding pedestal between the location of the chip and the inner discrete leads of the leadframe. Connections are provided between the bonding pads on the chip and the respective lines on the interposer and connections are also provided between the fingers and the respective lines on the leadframe.

Abstract: A high-voltage metal-oxide-semiconductor transistor device having a semiconductor-on-insulator structure comprises a substrate, an insulator layer provided on the substrate, a semiconductor layer of a first conductive type provided on the insulator layer, a source region of a second conductive type defined in the semiconductor layer, a drain region of the second conductive type defined in the semiconductor layer, a gate insulator film provided on the semiconductor layer so as to cover a part of the surface of the semiconductor layer adjacent to the source region, a gate electrode provided on the gate insulator film, an offset region defined in the semiconductor layer between the part of the semiconductor layer covered by the gate insulator film and the drain electrode, a less-doped region defined within the offset region at an upper part thereof, a control electrode provided between the substrate and the insulator layer so as to extend along a boundary between the insulator layer and the substrate at least un

Abstract: A semiconductor structure includes a single crystal silicon body, a relatively thin single crystal aluminum arsenide layer disposed on the silicon body, a relatively thin single crystal gallium arsenide layer disposed on the aluminum arsenide layer, and a relatively thick single crystal compound semiconductor layer disposed on the gallium arsenide layer.

Abstract: An integrated circuit vertical bipolar transistor includes monocrystalline emitter, base and collector contacts for electrically contacting the transistor's emitter, base and collector regions, respectively. The collector, base contact and emitter contact are preferably insulated from one another by oxide regions which are formed from the monocrystalline collector and monocrystalline base contacts. Since all of the contacts are formed of monocrystalline material and the oxide isolation is formed from monocrystalline material, high performance devices are formed. The process of forming the transistor self aligns the base to the collector and the emitter to the base. The monocrystalline base contact is also self aligned to the base and the monocrystalline emitter contact is self aligned to the emitter. The process preferably uses epitaxial lateral overgrowth and selective epitaxial growth from a mesa region to form the monocrystalline contacts.

Abstract: In order to reduce the rate of (hot charge-carrier) degradation of semiconductor devices formed in a semiconductor body, a neutral impurity--such as germanium in silicon MOS transistors--is introduced into the body in a neighborhood of an intersection of a p-n junction with a surface of the body.

Abstract: A radiation member (10) for a semiconductor device is formed by an aluminum alloy member having a low thermal expansion aluminum alloy section (11) and a high radiation aluminum alloy section (12) which are joined and integrally formed with each other. A semiconductor device (13) is carried on the major surface of the low thermal expansion aluminum alloy section (11). The low thermal expansion coefficient aluminum alloy has an average thermal expansion coefficient of not more than 17.times.10.sup.-6 /.degree.C. The high radiation aluminum alloy is larger in thermal conductivity than the low thermal expansion aluminum alloy.

Abstract: A semiconductor device includes a composite semiconductor substrate formed by disposing first and second semiconductor substrates in close contact with each other. At least one dielectric layer is formed in the composite semiconductor substrate. At least one polycrystalline layer is formed adjacent to the dielectric layer.