Patents Examined by Edward Waddy, Jr.
  • Patent number: 9104529
    Abstract: A method, computer program product, and computing system for copying a cache system from a first machine to a second machine, wherein the cache system includes cache content and a content directory, thus generating a duplicate cache system on the second machine. The duplicate cache system includes duplicate cache content and a duplicate content directory. A plurality of data requests concerning a plurality of data actions to be taken on a data array associated with the first machine are received on the first machine. The plurality of data requests are stored on a tracking queue included within the data array associated with the first machine.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: August 11, 2015
    Assignee: EMC Corporation
    Inventors: Philip Derbeko, Assaf Natanzon, Anat Eyal, David Erel
  • Patent number: 9081673
    Abstract: A microprocessor according to the present invention includes instruction execution unit that executes an instruction to output an access request to a memory according to a first protocol; memory control unit that converts the access request according to the first protocol to an access request according to a second protocol to perform an access control to an external memory to output the access request; selection unit that selects whether to access the external memory using the memory control unit; and interface unit that externally outputs one of the access request according to the first protocol and the access request according to the second protocol based on the selection result in the selection unit.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: July 14, 2015
    Assignee: NEC CORPORATION
    Inventor: Satoru Tagaya
  • Patent number: 9075764
    Abstract: A multiprocessor system includes a main memory and multiple processing cores that are configured to execute software that uses data stored in the main memory. In some embodiments, the multiprocessor system includes a data streaming unit, which is connected between the processing cores and the main memory and is configured to pre-fetch the data from the main memory for use by the multiple processing cores. In some embodiments, the multiprocessor system includes a scratch-pad processing unit, which is connected to the processing cores and is configured to execute, on behalf of the multiple processing cores, a selected part of the software that causes two or more of the processing cores to access concurrently a given item of data.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: July 7, 2015
    Assignee: APPLE INC.
    Inventor: Idan Saar
  • Patent number: 9076528
    Abstract: Memory system controllers can include non-volatile memory control circuitry including a plurality of channel control circuits. Each of the plurality of channel control circuits can be configured to be coupled to a respective number of logical units (LUNs). Memory management circuitry can be coupled to the non-volatile memory control circuitry and configured to allocate a write block cluster for host writes based on an information width of a host bus and a protocol of the host bus. The write block cluster can include one block from fewer than all of the LUNs.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: July 7, 2015
    Assignee: Micron Technology, Inc.
    Inventor: A. Kent Porterfield
  • Patent number: 9070453
    Abstract: To store, successively, in a plurality of memory cells, first and second pluralities of input bits that are equal in number, a first transformation transforms the first input bits into a first plurality of transformed bits. A first portion of the cells is programmed to store the first transformed bits according to a mapping of bit sequences to cell levels, but, if the first transformation has a variable output length, only if there are few enough first transformed bits to fit in the first cell portion. Then, without erasing a second cell portion that includes the first portion, if respective levels of the cells of the second portion, that represent a second plurality of transformed bits obtained by a second transformation of the second input bits, according to the mapping, are accessible from the current cell levels, the second portion is so programmed to store the second transformed bits.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: June 30, 2015
    Assignee: Ramot at Tel Aviv University Ltd.
    Inventors: Eran Sharon, Idan Alrod, Simon Litsyn, Ishai Ilani
  • Patent number: 9070420
    Abstract: A memory sharing system includes a master control device, a slave control device and a memory device. The master control device selectively generates a clock signal to the memory device. The slave control device receives and tracks the clock signal via a delay phase locked loop (DLL) to generate and align an output signal with the clock signal. The master control device arbitrates an access right.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: June 30, 2015
    Assignee: MStar Semiconductors, Inc.
    Inventors: Chunkai Derrick Wei, Po-Sung Huang, Yi Ling Chen, Ming-Chieh Yeh, Chih-Chieh Lee
  • Patent number: 9058112
    Abstract: The invention relates to retrieving data from a storage system. One embodiment of the invention comprises receiving a write operation, establishing a correspondence relationship between a logic block address and a physical block address of the write operation, and determining whether a valid data percentage in a mapping table is greater than a predetermined threshold after the correspondence relationship is added in stored metadata. In response to the valid data percentage being less than the predetermined threshold, the embodiment adds the correspondence relationship to a B-tree data structure of stored metadata.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: June 16, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Min Fang, Hui X. Gu, Xiao Yan Li, Fan G. Zeng
  • Patent number: 9053033
    Abstract: A method, computer program product, and computing system for defining a first assigned cache portion within a cache system, wherein the first assigned cache portion is associated with a first machine. At least one additional assigned cache portion within the cache system is defined. The at least one additional assigned cache portion is associated with at least one additional machine. Content received by the first machine is written to the first assigned cache portion. After the occurrence of a reclassifying event, the first assigned cache portion is reclassified as a public cache portion that is added to an initial cache portion within the cache system. The public cache portion is associated with the first machine and the at least one additional machine.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: June 9, 2015
    Assignee: EMC Corporation
    Inventors: Philip Derbeko, Anat Eyal, Roy E. Clark
  • Patent number: 9046914
    Abstract: Embodiments of the invention relate to reducing memory required to store an array of formulas and values corresponding to a formula-array. A set of formula-array representations is provided and arranged in a successive order. Each formula-array representation is evaluated for an associated memory requirement to support use thereof, followed by conversion to a structure of the formula-array representation at a successive level. Selection of the formula-array representation is determined based upon a minimal memory requirement from the formula-array representations in the order.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: June 2, 2015
    Assignee: International Business Machines Corporation
    Inventors: James J. Rhodes, Hovey Raymond Strong, Jr.
  • Patent number: 9046915
    Abstract: A circuit for use in a computing system including a bus interface unit and an autoload controller. The autoload controller has an input to receive an initialization signal. In response to receiving the initialization signal, the autoload controller searches for a signature using the bus interface unit and, in response to finding the signature at a signature address, loads a plurality of base addresses corresponding to a plurality of controllers from memory locations having a predetermined relationship to the address, and provides the plurality of base addresses to a control output thereof.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: June 2, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Xiao Gang Zheng, Ming L. So
  • Patent number: 9043533
    Abstract: A method is used in sizing volatile memory (VM) cache based on flash-based cache usage. A user selection for a flash-based cache is received. Based on the selection, configuration and sizing factors are provided, by a flash based cache driver, to VM cache size determination logic. Based on the configuration and sizing factors and a sizing formula and rules, a requested VM cache size is produced by the VM cache size determination logic. Based on the requested VM cache size, the VM cache is caused, via VM cache resizing logic, to be resized to the requested VM cache size.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: May 26, 2015
    Assignee: EMC Corporation
    Inventors: Peter Shajenko, Jr., Kevin S. Labonte, Charles H. Hopkins, Thomas E. Linnell, Feng Zhou
  • Patent number: 9015430
    Abstract: Systems and methods for copy on write storage conservation are presented. In one embodiment a copy on write storage conservation method includes creating and mounting a snapshot; mounting a snapshot; monitoring interest in the snapshot; initiating a copy on write discard process before a backup or replication is complete; and deleting the snapshot when the backup or replication is complete. In one embodiment the method also includes marking a file as do not copy on write. In one embodiment, the copy on write discard process includes discarding copy on write data when a corresponding read on the file in the snapshot is successful. Initiating a copy on write discard process can be done at a variety of levels (e.g., a file level, an extent level, a block-level, etc.).
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: April 21, 2015
    Assignee: Symantec Corporation
    Inventor: Dilip Madhusudan Ranade
  • Patent number: 9009438
    Abstract: An approach to efficient space reclamation in multi-layered thinly provisioned systems. A parent storage volume is thinly provisioned, and uses one or more child storage volumes that are also thinly provisioned for storage. A reclamation command sent to the device providing the parent thinly provisioned storage volume identifies that data has been released, and that the physical storage storing that data can be placed in a free pool and used to satisfy future write requests in the parent storage volume. An identify module identifies which child storage volumes supporting the parent storage volume are thinly provisioned. The data is released at the level of the parent storage volume, and the reclamation command is sent to the child storage volumes supporting the parent storage volume and that are themselves thinly provisioned. The storage is thus released by all affected thinly provisioned storage volumes, and not just the parent storage volume that received the reclamation command.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Rahul M. Fiske, Carl E. Jones, Subhojit Roy
  • Patent number: 9009416
    Abstract: A method, computer program product, and computing system for reclassifying a first assigned cache portion associated with a first machine as a public cache portion associated with the first machine and at least one additional machine after the occurrence of a reclassifying event. The public cache portion includes a plurality of pieces of content received by the first machine. A content identifier for each of the plurality of pieces of content included within the public cache portion is compared with content identifiers for pieces of content included within a portion of a data array associated with the at least one additional machine to generate a list of matching data portions. The list of matching data portions is provided to at least one additional assigned cache portion within the cache system that is associated with the at least one additional machine.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: April 14, 2015
    Assignee: EMC Corporation
    Inventors: Philip Derbeko, Anat Eyal, Roy E. Clark
  • Patent number: 8990536
    Abstract: A constrained computing device is provided. The constrained computing device includes a memory, a processor coupled to the memory, and a journaling component executed by the processor in kernel mode. The journaling component is configured to receive information descriptive of a device control, allocate, in the memory, a variable record structured according to a variable definition associated with the device control, store the information within the variable record, receive updated information descriptive of the device control, allocate, in the memory, an update record structured according to an update variable definition, store the updated information within the update record, and link the variable record to the update record.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: March 24, 2015
    Assignee: Schneider Electric IT Corporation
    Inventor: Sean White
  • Patent number: 8949525
    Abstract: A method of setting up a redistribution scheme for redistributing digital data packages within a digital data storage system comprising a plurality of nodes, wherein the data packages are associated with respective keys and are distributed among the nodes according to a first distribution configuration within the digital data storage system. The method includes: determining a second distribution configuration, in accordance with which it is intended to redistribute the data packages; applying a migration function to the respective keys of each of the data packages, which function yields a migration value associated with each of the data packages; and assigning a migration time to each of the data packages based on its associated migration value, at which times it is intended to migrate the respective data packages to conformity with the second distribution configuration. A corresponding digital data storage system is described.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: February 3, 2015
    Assignee: Spotify, AB
    Inventors: Fredrik Niemela, Matthias deZalenski, Gunnar Kreitz, Tommie Gannert, Peter Schuller
  • Patent number: 8935500
    Abstract: Distributed storage resources having multiple storage units are managed based on data collected from online monitoring of workloads on the storage units and performance characteristics of the storage units. The collected data is sampled at discrete time intervals over a time period of interest, such as a congested time period. Normalized load metrics are computed for each storage unit based on time-correlated sums of the workloads running on the storage unit over the time period of interest and the performance characteristic of the storage unit. Workloads that are migration candidates and storage units that are migration destinations are determined from a representative value of the computed normalized load metrics, which may be the 90th percentile value or a weighted sum of two or more different percentile values.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: January 13, 2015
    Assignee: VMware, Inc.
    Inventors: Ajay Gulati, Irfan Ahmad, Carl A. Waldspurger, Chethan Kumar
  • Patent number: 8874846
    Abstract: Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michele M. Franceschini, Ashish Jagmohan, John P. Karidis, Luis A. Lastras-Montano, Moinuddin K. Qureshi
  • Patent number: 8863139
    Abstract: The present invention provides a technique capable of improving use efficiency of storage devices. In this regard, a computer system of the present invention includes: a plurality of storage subsystems; an information processing apparatus coupled to the storage subsystems and including a virtual layer for virtually providing information from the storage subsystems; and the a management system that manages the plurality of storage subsystems and the information processing apparatus. The management system manages, on a memory, configuration information of logical volumes allocated to virtual instances managed on a virtual layer of the information processing apparatus and operation information of hardware resources included in the storage subsystems. The management system evaluates use efficiency of the virtual instances based on the configuration information of the logical volumes and the operation information of the hardware resources and outputs an evaluation result.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: October 14, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Tomoaki Kakeda, Takato Kusama
  • Patent number: 8862805
    Abstract: A storage system has a plurality of flash packages, and a storage controller for receiving a write request from a host and sending a write-data write request based on data conforming to this write request to a write-destination flash package. A virtual capacity, which is larger than the physical capacity of the flash package, is defined in the storage controller. The storage system compresses the write data, and writes the compressed write data to the write-destination flash chip.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: October 14, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Masayuki Yamamoto