Abstract: An apparatus having processing circuitry configured to execute applications involving access to memory may include a CPU and a cache controller. The CPU may be configured to access cache memory for execution of an application. The cache controller may be configured to provide an interface between the CPU and the cache memory. The cache controller may include a bitmask to enable the cache controller to employ a two-level data structure to identify memory exploits using hardware. The two-level data structure may include a page level protection mechanism, and a sub-page level protection mechanism.

Abstract: A page table is a data structure used by a virtual memory system in a computer system to store the mapping between virtual addresses and physical addresses. Embodiments herein use a tree to map a virtual memory address space in the page table. The tree may be an N-ary tree where N is a power of two (e.g., 2, 4, 8, 16, etc.). The tree may include multiple levels that each correspond to a different page table size. For example, an octree includes eight different entries for each child node which may include per-thread sub-entries. Child nodes in the first level of the octree may each correspond to a 512 GiB page, while child nodes in the second level, however, may each have eight entries that correspond to a 64 GiB page. In this manner, an N-ary tree may be used to support a computing system with varying page sizes.

Abstract: Systems and methods are disclosed for identifying disk drives and processing data access requests. A disk drive may be identified as an Advanced Host Controller Interface (AHCI) drive, a Non-Volatile Memory Express (NVME) drive, and/or an ATA packet interface (ATAPI) drive. Data access requests for the disk drive may be translated to NVME commands, AHCI commands, or ATAPI commands, based on whether the drive is identified as a NVME drive, an AHCI drive, and/or an ATAPI drive.

Abstract: An improved technique for storing I/O metrics includes assigning metric values to data buckets held in kernel memory. Each data bucket covers a particular range of values of a respective metric and is configured as a counter, whose count is incremented each time the multipathing driver obtains or computes a metric value that falls within the range of the data bucket. Bucket counts can be read by an external program to obtain aggregate information about I/O metrics over time. The aggregate information can be fed back to the multipathing driver to enable improved selections of paths for conveying data to and from a storage array.

Abstract: Techniques are provided for anonymizing data in a data stream.

Abstract: An embodiment is a memory card including a rectangular printed circuit card having a first side and a second side, a first length of between 151.35 and 161.5 millimeters, and first and second ends having a second length smaller than the first length. The memory card also includes a first plurality of pins on the first side extending along a first edge of the rectangular printed circuit card that extends along a length of the card, a second plurality of pins on the second side extending on the first edge of the rectangular printed circuit card, and a positioning key having its center positioned on the first edge of the rectangular printed circuit card and located between 94.0 and 95.5 millimeters from the first end of the rectangular printed circuit card. The memory card also includes a memory module, a hub device and pins for boundary scan signals.

Abstract: The invention relates to retrieving data from a storage system. One embodiment of the invention comprises receiving a write operation, establishing a correspondence relationship between a logic block address and a physical block address of the write operation, and determining whether a valid data percentage in a mapping table is greater than a predetermined threshold after the correspondence relationship is added in stored metadata of stored metadata.

Abstract: Memory system controllers can include non-volatile memory control circuitry including a plurality of channel control circuits. Each of the plurality of channel control circuits can be configured to be coupled to a respective number of logical units (LUNs). Memory management circuitry can be coupled to the non-volatile memory control circuitry and configured to allocate a write block cluster for host writes based on an information width of a host bus and a protocol of the host bus. The write block cluster can include one block from fewer than all of the LUNs.

Abstract: Analyzing a managed runtime cache is provided. A heap associated with a managed runtime environment, where the heap includes an N-generation cache or a plurality of objects associated with a program operating within a managed runtime environment is identified. A snapshot of the heap is produced, wherein the snapshot identifies a memory location for each object of the plurality of objects at which the object is stored. A generation of each of the plurality of objects based, at least in part, on the memory location of the object is determined. One or more suggestions based, at least in part, on the memory location of the plurality of objects is provided.

Abstract: Systems and methods for multicast tree-based data distribution in a distributed shared cache. An example processing system comprises: a plurality of processing cores, each processing core communicatively coupled to a cache; a tag directory associated with caches of the plurality of processing cores; a shared cache associated with the tag directory; a processing logic configured, responsive to receiving an invalidate request with respect to a certain cache entry, to: allocate, within the shared cache, a shared cache entry corresponding to the certain cache entry; transmit, to at least one of: a tag directory or a processing core that last accessed the certain entry, an update read request with respect to the certain cache entry; and responsive to receiving an update of the certain cache entry, broadcast the update to at least one of: one or more tag directories or one or more processing cores identified by a tag corresponding to the certain cache entry.

Abstract: Computer-readable storage media, computing apparatuses and methods associated with persistent memory are discussed herein. In embodiments, a computing apparatus may include one or more processors, along with a plurality of persistent storage modules that may be coupled with the one or more processors. The computing apparatus may further include system software, to be operated by the one or more processors, to receive volatile memory allocation requests and persistent storage allocation requests from one or more applications that may be executed by the one or more processors. The system software may then dynamically allocate memory pages of the persistent storage modules as: volatile type memory pages, in response to the volatile memory allocation requests, and persistent type memory pages, in response to the persistent storage allocation requests. Other embodiments may be described and/or claimed.

Abstract: Described herein are systems and methods to process efficiently, according to a certain order, a plurality of data sets arranged in data blocks. In one embodiment, a first compute element receives from another compute element a first set of instructions that determine an order in which a plurality of data sets are to be processed as part of a processing task. Relevant data sets are then streamed into a cache memory associated with the first compute element, but the order of streaming is not by order of storage but rather by the order conveyed in the first set of instructions.

Abstract: A mechanism is provided for thin provisioning. An original time-domain sequence of a load parameter of storage resources already allocated to an application program is collected. A future load peak time period of the storage resources already allocated to the application program is determined based on the collected original time-domain sequence of the load parameter. A new storage resource unit from a high-speed storage is allocated in response to receipt of a request to allocate the new storage resource unit to the application program in the future load peak time period. On an occasion of thin provisioning, whether the physical storage resources newly allocated to the application program are located in a low-speed storage or a high-speed storage is determined according to the accesses of the application program to the already-allocated physical storage resources.

Abstract: A method for processing an error directory of a node in a cache coherence non-uniform memory access (CC-NUMA) system and a node are provided. The method effectively reduces a possibility of a breakdown of the system caused by accumulation of the error bits in the directory memory of the CC-NUMA system. The method comprises: when a quantity of bits of a correctable error of a directory stored in a directory memory of the node is greater than a preset threshold, controlling all processors in the CC-NUMA system to write dirty data in a corresponding cache back to a corresponding main memory, flush the dirty data, and directly flush clean data in the corresponding cache; and controlling the CC-NUMA system to enter a quiescent state, clearing a record stored in the directory memory to zero, and controlling, after the zero clearing is completed, the CC-NUMA system to exit the quiescent state.

Abstract: Device for selecting a level for at least one read voltage for reading data stored in a multi-level memory device. The multi-level memory device includes a plurality of memory blocks, in which each of the memory blocks includes a plurality of word lines, each of the word lines being allocated to a plurality of memory pages and being indexed by a word line index. The device includes a first mapping unit for mapping each of the word line indices to one bin label, in which the number of bin labels is smaller than the number of word lines, and a second mapping unit for mapping each of the bin labels to a voltage information being indicative for at least one read voltage, in which the level for the at least one read voltage for reading data is selectable for each word line based on the respective word line index.

Abstract: Described herein are systems and methods to redirect data read requests from the first tier to the second tier of a two-tier distributed memory. The first tier includes memory modules with data sets. Data interfaces associated with the first tier memory modules, receive from a second tier including compute elements and associated cache memories, requests to fetch data from the first tier. If a data set has not recently been fetched by the second tier, then the data interface will send the data set from the first tier to the cache memory associated with the requesting compute element. If a data set has recently been fetched by the second tier, the data interface will redirect the requesting compute element to fetch the data set from the cache memory in which the data set is currently located.

Abstract: The present embodiments describe systems and methods for a dynamically updated user data cache for persistent productivity. In an embodiment, the system includes caching mechanism optimized to support user productivity in the case of a primary storage failure. For example, an embodiment of a method includes establishing a cache for caching user data in a persistent data storage device that is accessible by a first operating system and a second operating system. The method may also include identifying a set of user data to be stored in the cache. Additionally, the method may include storing the set of user data into the cache. The method may also include accessing the set of user data stored in the cache with the second operating system in response to the first operating system being in a degraded condition.

Abstract: In one embodiment, a method for managing data includes determining that a cache access count for a given data block is greater than an average cache access count, receiving a list of active applications accessing the given data block with an anticipated access count for each active application, receiving a list of applications that are anticipated to access the given data block within a time window with an anticipated future access count for each anticipated application, determining that a block application access weight is greater than a block application access threshold, determining that a cache profile weight for the given data block is greater than zero, and sending the cache profile weight to a file system. Other systems, methods, and computer program products are described according to more embodiments.

Abstract: Methods, apparatus and computer program products for a distributed system include dividing logical volume data into data subsets, and defining at least one distributedly storage configuration for the logical volume. Metadata for the logical volume is written to a first set of first metadata tables, and the first set of first metadata tables is divided into metadata subsets having a one-to-one correspondence with the data subsets. The metadata subsets are distributed among the multiple digital information devices, and the metadata is copied from the first set of first metadata tables to a second set of corresponding second metadata tables in a one-to-one correspondence with the first metadata tables, and the second metadata tables are distributed among the multiple digital information devices.

Abstract: Apparatuses, systems, and methods are disclosed for managing cache pools. A storage request module monitors storage requests received by a cache. The storage requests include read requests and write requests. A read pool module adjusts a size of a read pool of the cache to increase a read hit rate of the storage requests. A dirty write pool module adjusts a size of a dirty write pool of the cache to increase a dirty write hit rate of the storage requests.