Patents Examined by Eliseo Ramos-Feliciano
  • Patent number: 10304700
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Shih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Patent number: 10297551
    Abstract: A method of manufacturing a redistribution circuit structure and a method of manufacturing an INFO package at least include the following steps. An inter-dielectric layer is formed over a substrate. A seed layer is formed over the inter-dielectric layer. A plurality of conductive patterns are formed over the seed layer. The seed layer and the conductive patterns include a same material. While maintain a substantially uniform pitch width in the conductive pattern, the seed layer exposed by the conductive patterns is selectively removed through a dry etch process to form a plurality of seed layer patterns. The conductive patterns and the seed layer patterns form a plurality of redistribution conductive patterns.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui-Jung Tsai, Hung-Jui Kuo, Yun-Chen Hsieh
  • Patent number: 10177109
    Abstract: The present invention includes: preparing a semiconductor substrate having a first main surface and a second main surface that is located on an opposite side of the first main surface; forming a first electrode on the first main surface; forming a solder-bonding metal film (a first solder-bonding metal film) on the first electrode; forming a sacrificial film on the first solder-bonding metal film; grinding the second main surface after forming the sacrificial film; performing heat treatment after the grinding (forming an element structure on the third main surface side); removing the sacrificial film after the performing heat treatment; and solder-bonding the first solder-bonding metal film and a first external electrode.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: January 8, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yosuke Nakata
  • Patent number: 10177196
    Abstract: Methods and apparatus for use in the manufacture of a display device including pixels. Each pixel includes a plurality of sub-pixels, each sub-pixel configured to provide light of a given wavelength. The method may include: performing, using a pick up tool (PUT), a first placement cycle comprising picking up first light emitting diode (LED) dies, and placing a first LED die on a substrate of the display device at a location corresponding to a sub-pixel the display device. The method further includes performing one or more subsequent placement cycles comprising picking up a second LED die, and placing the second LED die on the substrate of the display device at a second location corresponding to the sub-pixel of the display device. Multiple first and second LED dies may be picked and placed during each placement cycle to populate each pixel of the display device to provide redundancy of LED dies at each sub-pixel.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: January 8, 2019
    Assignee: Facebook Technologies, LLC
    Inventors: Patrick Joseph Hughes, Vincent Brennan, Joseph O'Keeffe, Christopher Percival, William Padraic Henry, Tilman Zehender
  • Patent number: 10068956
    Abstract: An organic light emitting display can include a substrate, a first capacitor formed on the substrate, the first capacitor including a first capacitor lower electrode, a first capacitor upper electrode, and a gate insulating layer between the first capacitor lower upper electrodes, a first passivation layer over the first capacitor, a second capacitor on the first passivation layer, the second capacitor including a second capacitor lower electrode, a second capacitor upper electrode, and a second passivation layer interposed between the second capacitor lower upper electrodes, an organic insulating layer over the second capacitor, a pixel electrode on the organic insulating layer, an organic layer on the pixel electrode, the organic layer including at least a light emitting layer, and an opposite electrode on the organic layer, and the width of the second capacitor lower electrode is greater than that of the second capacitor upper electrode.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: September 4, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Jinwoo Park
  • Patent number: 10038048
    Abstract: A display apparatus and a method of manufacturing a display apparatus, the apparatus including a plurality of pixels on a substrate, wherein a first pixel of the plurality of pixels includes a scanning line extending in a first direction; a plurality of wires extending in a second direction crossing the first direction; at least one insulating layer between the scanning line and the plurality of wires; a thin film transistor electrically connected to the scanning line and the plurality of wires; and a pixel electrode electrically connected to the thin film transistor, wherein at least one of the plurality of wires includes a first line and a second line spaced apart from each other in the second direction, and a connection line electrically connecting the first line and the second line, the at least one insulating layer being between the connection line and the first and second lines.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: July 31, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Sun Park
  • Patent number: 9960216
    Abstract: An organic light emitting display apparatus includes a substrate; an anode electrode on the substrate; an auxiliary electrode on the substrate; an organic emission layer on the anode electrode; a cathode electrode on the organic emission layer and on the auxiliary electrode; an insulating bank on the auxiliary electrode, the bank overlapping a first portion of the auxiliary electrode and exposing a second portion of the auxiliary electrode; a first partition wall on the auxiliary electrode; a second partition wall on the first partition wall and covering the exposed second portion of the auxiliary electrode in plan view. A separation space is between the second partition wall and the bank, the cathode electrode is electrically connected to the auxiliary electrode through the separation space between the second partition wall and the bank, and the second partition wall is supported by the first partition wall and the bank.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: May 1, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Joonsuk Lee, Se June Kim
  • Patent number: 9929295
    Abstract: In various embodiments, photovoltaic modules are hermetically sealed by providing a first glass sheet, a photovoltaic device disposed on the first glass sheet, and a second glass sheet, a gap being defined between the first and second glass sheets, disposing a glass powder within the gap, and heating the powder to seal the glass sheets.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: March 27, 2018
    Assignee: SIVA POWER, INC.
    Inventor: Markus Eberhard Beck
  • Patent number: 9929082
    Abstract: Receiving structure for electrically connecting a nano-object on a surface thereof and re-establish electrical contact with the nano-object on the opposite surface, and methods for manufacturing the structure. The invention, that can be used for molecular characterisation, makes use of a support (44) to connect a nano-object (50) onto its top face and continue the electrical contact on its bottom face. At least two interconnects (52, 54) pass through the support. The two faces of the support comprise contact continuity zones (56, 58, 60, 62) for the interconnects. According to the invention, at least the zones (56, 58) in the top face are doped zones each having a pattern adapted to the fan out of the interconnect associated with it, on this face.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: March 27, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Xavier Baillin, Patrick Leduc
  • Patent number: 9893315
    Abstract: A display device includes a display device including a substrate, and a display unit disposed on the substrate. An encapsulating unit encapsulates the display unit. The encapsulating unit includes a barrier organic layer. The barrier organic layer includes a plurality of organic materials and a plurality of inorganic materials. The inorganic materials are arranged in free volumes between the organic materials.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 13, 2018
    Assignees: SAMSUNG DISPLAY CO., LTD., INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
    Inventors: Seungyong Song, Hyojeong Kwon, Seunghun Kim, Myungmo Sung, Kwanhyuck Yoon
  • Patent number: 9887080
    Abstract: A method of forming a SiOCN material layer and a method of fabricating a semiconductor device are provided, the method of forming a SiOCN material layer including supplying a silicon source onto a substrate; supplying a carbon source onto the substrate; supplying an oxygen source onto the substrate; and supplying a nitrogen source onto the substrate, wherein the silicon source includes a non-halogen silylamine, a silane compound, or a mixture thereof.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: February 6, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kang-hun Moon, Yong-suk Tak, Gi-gwan Park
  • Patent number: 9875925
    Abstract: A method of fabricating a semiconductor device includes forming a doped polysilicon layer on a substrate, forming a barrier layer on the doped polysilicon layer, forming an oxidized barrier layer by oxidizing a surface of the barrier layer, and forming a metal layer on the oxidized barrier layer.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: January 23, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung-ho Kong, Jeong-hee Park, Taek-jung Kim, Han-young Kim, Keon-seok Seo, Jong-myeong Lee, Hee-sook Park
  • Patent number: 9870950
    Abstract: A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of dummy gates on a substrate. Each of the dummy gates includes a gate mask disposed on an upper surface of each of the dummy gates. A spacer is disposed on at least two sides of the dummy gates. An insulating interlayer is formed on the gate mask and the spacer. A first polishing including chemical mechanical polishing is performed on portions of the gate mask and the insulating interlayer by using a slurry composite having a first mixing ratio. A second polishing including chemical mechanical polishing is formed on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of the plurality of dummy gates, by using a slurry composite having a second mixing ratio.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: January 16, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Sun Hwang, Ja-Eung Koo, Jong-Hyung Park, Ho-Young Kim, Leian Bartolome, Bo-Un Yoon, Hyoung-Bin Moon
  • Patent number: 9870940
    Abstract: Methods of forming nanosheets for a semiconductor device are provided including providing a silicon on insulator (SOI) handle wafer, the SOT handle wafer including a silicon layer and a dielectric layer on the silicon layer; providing a first donor wafer; bonding the SOI handle wafer and the first donor wafer together to provide a bonded structure; debonding the bonded structure to provide an intermediate wafer including a plurality of silicon or non-silicon nanosheets and a plurality of dielectric layers alternately stacked; and bonding the intermediate wafer to a second donor wafer to provide a final wafer including a plurality of silicon or non-silicon layers and a plurality of dielectric layers alternately stacked, wherein the final wafer includes at least one more pair of silicon or non-silicon and dielectric layers than the intermediate wafer.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: January 16, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wei-E Wang, Mark Rodder, Borna Obradovic
  • Patent number: 9842748
    Abstract: Embodiments of the present disclosure provide a liner assembly including a plurality of individually separated gas passages. The liner assembly enables tenability of flow parameters, such as velocity, density, direction and spatial location, across a substrate being processed. The processing gas across the substrate being processed may be specially tailored for individual processes with a liner assembly according to embodiment of the present disclosure.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: December 12, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Mehmet Tugrul Samir, Shu-Kwan Lau
  • Patent number: 9837629
    Abstract: An organic light emitting diode display including a substrate, a first electrode disposed on the substrate, a second electrode disposed on the substrate and separated from the first electrode, a pixel defining layer disposed on the first electrode and the second electrode, a first organic emission layer disposed on the first electrode corresponding to the first opening, a second organic emission layer disposed on the second electrode corresponding to the second opening, and a common electrode disposed on the first organic emission layer and the second organic emission layer. The first electrode includes a first dent portion. The second electrode includes a second dent portion having a different size from the first dent portion. The pixel defining layer includes a first opening exposing the first electrode corresponding to the first dent portion and a second opening exposing the second electrode corresponding to the second dent portion.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: December 5, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hae Young Yun, Jun Young Kim, Jung-Hyun Cho
  • Patent number: 9818969
    Abstract: An OLED display device includes a driving semiconductor layer on a substrate, a gate insulating layer covering the driving semiconductor layer, a driving gate electrode and etching preventing layer on the gate insulating layer, a passivation layer on the gate insulating layer, driving gate electrode, and etching preventing layer, and including a plurality of protruding and depressed patterns, driving source and drain electrodes on the passivation layer, a pixel electrode on the protruding and depressed pattern, and exposed etching preventing layer, the pixel electrode having a protruding and depressed shape, a pixel definition layer on the passivation layer, and the driving source and drain electrodes, and having a pixel opening exposing the pixel electrode, an organic emission layer on the exposed pixel electrode, and a common electrode on the organic emission layer and pixel definition layer. The protruding and depressed pattern partially exposes the etching preventing layer.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: November 14, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kyung Hoon Park, Sun Park, Chun Gi You
  • Patent number: 9812335
    Abstract: A method of fabricating a semiconductor device is disclosed. The method may include forming an target layer on a substrate, forming a mask pattern on a target layer, performing a first process to etch the target layer and form a first sub-trench, and performing a second process to further etch the target layer and form a second sub-trench. First and second sidewall patterns may be formed on a sidewall of the mask pattern to be used as an etch mask in the first and second processes, respectively. Outer sidewalls of the first and second sidewall patterns may be formed to have different angles with respect to a top surface of the substrate.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: November 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Je-Woo Han, Junho Yoon, Kyohyeok Kim, Dongchan Kim, Sungyeon Kim, Jaehong Park, Jinyoung Park, KyungYub Jeon
  • Patent number: 9768412
    Abstract: A composition which can be used as an organic water/oxygen barrier material, an OLED display device and manufacturing method thereof are disclosed. The composition includes: 15-25 wt % of parylene, 15-25 wt % of polyvinyl chloride, 5-15 wt % of acetone, 5-15 wt % of trichloroethylene, 10-20 wt % of polyvinyl acetate, 5-15 wt % of polyvinyl alcohol, 0-5 wt % of SiO2 nanoparticles, and 8-12 wt % of an organic solvent, wherein all weight percent values are based on the total weight of the composition. When a water/oxygen barrier layer fabricated by the composition is disposed between a luminescent layer of OLED and a light extraction layer, water vapor and oxygen gas can be prevented from entering the OLED luminescent layer, thereby prolonging the service life of the OLED luminescent layer.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: September 19, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Haidong Wu
  • Patent number: 9765430
    Abstract: A plasma processing apparatus for alternately performing a first plasma processing step using first and second processing gases and a second plasma processing step using third and fourth processing gases. The apparatus includes: a processing container that has a dielectric window in a ceiling and removably accommodates a workpiece; an exhaust unit that evacuates the processing container; a processing gas supply unit that supplies the first, second, third, and fourth processing gases into the processing container; a first gas introduction unit including a top plate gas injection port, a dielectric window gas flow path, and a first external gas flow path; a second gas introduction unit including a sidewall gas injection port, a sidewall gas flow path, and a second external gas flow path; an electromagnetic wave supply unit that supplies electromagnetic waves into the plasma generating space; a bypass exhaust path; and an opening/closing valve.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: September 19, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takehisa Saito, Takenao Nemoto, Koji Yamagishi, Hiroshi Kaneko