Patents Examined by Emily Yue Chan
  • Patent number: 4707802
    Abstract: A semiconductor IC device such as a peripheral interface LSI device used in a data processing system comprises an address memory for storing the chip address of the device itself and a comparator for comparing an address signal input thereto from an external circuit with the content of the address memory. Address data existing on a bus line in an initial setting status is previously stored in the address memory as a chip address of the device. The device enters a chip selected condition depending on the coincidence between the address signal from the external circuit and the content of the address memory.
    Type: Grant
    Filed: September 20, 1983
    Date of Patent: November 17, 1987
    Assignee: Fujitsu Limited
    Inventor: Hitoshi Takahashi
  • Patent number: 4706215
    Abstract: A method and associated apparatus is provided for protecting the accounting data stored in an electronic postage meter having multiple non-volatile memories for the storage of accounting data, including the steps of and associated apparatus for providing a first non-volatile memory; writing postage transactions accounting data into the first non-volatile memory in real time during each trip cycle of the meter; providing a second non-volatile memory; writing postage transaction accounting data into the second non-volatile memory only during the power cycle of the meter; and disabling the first non-volatile memory when the meter enters a power down cycle to prevent any further writing of data into the first non-volatile memory. Advantageously, the first non-volatile memory is clamped to ground potential during the power down cycle.
    Type: Grant
    Filed: August 22, 1984
    Date of Patent: November 10, 1987
    Assignee: Pitney Bowes Inc.
    Inventors: Wallace Kirschner, Easwaran C. N. Nambudiri, Douglas H. Patterson
  • Patent number: 4692893
    Abstract: A data buffer has a storage array that is addressable for read and write operations by an address of n bits that are supplied by a read address counter and a write address counter that each have n+1 bits. The n+1th bit is in effect a counter for passes through the array by the read and write circuits. During a write operation the n+1th bit of the write counter is stored as part of a parity bit for the addressed array location. During a read operation the n+1th bit of the read address counter is entered into a parity checking function on the word read from the addressed location. An errror is signaled if the n+1th bit of the read address counter does not agree with the n+1th bit of the write counter at the time of the write operation. For example, an error is detected if the write circuits fail and the read circuits make a second pass through words that have previously been read. The same entries on a next pass through the array.
    Type: Grant
    Filed: December 24, 1984
    Date of Patent: September 8, 1987
    Assignee: International Business Machines Corp.
    Inventor: Daniel F. Casper
  • Patent number: 4691279
    Abstract: A method and a means of increasing the performance of an instruction buffer in a digital data processing system is disclosed. The improvement is accomplished by by-passing the content addressable memory operation which has heretofore been utilized to access page addresses in the instruction buffer. As each word included on the same page was accessed, the CAM was repetitiously activated even though it was accessing the same page. In the present system, word accesses made to the same page are handled in a much improved manner. In the present system, a comparator is implemented in the system which compares the presently reference page with the previously referenced word, so that when a match is noted, i.e., the same page is indicated, the CAM is bypassed and successive requests made to the same page are satisfied from the instruction buffer by a validity designator which designates that the presently referenced word is the correct one.
    Type: Grant
    Filed: March 2, 1984
    Date of Patent: September 1, 1987
    Assignee: Unisys Corporation
    Inventors: Michael Danilenko, John T. Rusterholz, Archie E. Lahti
  • Patent number: 4689765
    Abstract: Address circuitry generates groups of tag signals, and each group is associated with a data word in a data processing device. A portion of the tag signals defines an addressable location in a storage device and another portion of the tag signals defines an operational identification of its associated data word. As data words (i.e., instruction words, operands, etc.) are fetched from memory they are decoded, if necessary, or made ready, (for use by the circuitry which executes the operations intended for such instructions, operands, etc.), and are stored in a multi-plane set of buffers. Each of said buffers has a plurality of address locations, corresponding to the address locations defined by said first portions of said tag signals, and each of said planes is selectable by said other portions of said tag signals.
    Type: Grant
    Filed: January 28, 1983
    Date of Patent: August 25, 1987
    Assignee: Digital Equipment Corporation
    Inventor: Donald F. Hooper
  • Patent number: 4688166
    Abstract: A direct memory access controller (8, FIG. 1) is provided which can service a number of input/output controllers (24, 26) concurrently on a time-division multiplexed basis. The direct memory access controller 8 (DMAC) is capable of interconnecting more than one input/output device (64, 66, 69, 74, 76) with more than one system memory (2, 20). The DMAC 8 can also transfer data from one system memory (2) to a second system memory (20), or within one system memory.
    Type: Grant
    Filed: August 3, 1984
    Date of Patent: August 18, 1987
    Assignee: Motorola Computer Systems, Inc.
    Inventor: Glenn H. Schneider
  • Patent number: 4688190
    Abstract: A computer memory architecture is most advantageously used in conjunction with a digital computer, to provide an improved high speed graphics display capability. Data representative of digital images to be displayed is generated and/or manipulated by a display processor and stored within a selected portion of the display processor's main memory. Subsequent modifications to the stored image are effectuated by the display processor reading the data from its main memory, performing appropriate operations on the data, and writing the data back into the main memory. Updated images are transferred to an buffer memory which sequentially stores the images in the order in which they were updated by the display processor. Data representative of an updated image is then transferred to the display frame buffer of the particular display system for subsequent display. Data is transferred from the buffer memory to the frame buffer during periods when the frame buffer is not refreshing the display.
    Type: Grant
    Filed: October 31, 1983
    Date of Patent: August 18, 1987
    Assignee: Sun Microsystems, Inc.
    Inventor: Andreas Bechtolsheim
  • Patent number: 4683552
    Abstract: A display system operates to display characters, graphics and picture images in connection with a host computer in online mode in which character data is treated in the online display data form, and without connection of the host computer in offline mode in which character data is treated in the offline display form. Character data supplied for the online operation is converted into the offline display data form and stored for use in offline mode, or it is first stored and then converted when used in offline mode.
    Type: Grant
    Filed: April 25, 1984
    Date of Patent: July 28, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Hiroaki Kambayashi, Yasuyuki Okada
  • Patent number: 4683550
    Abstract: A modular plug-in instrumentation system for enabling a personal computer to perform instrumentation functions, including receiving analog and digital signals from an external device and transmitting analog and digital signals to an external device, includes a carrier module pluggable into a bus of the personal computer, and also includes an internal instrumentation bus into which a plurality of different interchangeable instrument modules can be plugged. The instrumentation bus includes a digital portion, and also includes a segmented analog portion that is extendable merely by plugging instrumentation modules into bus connectors which span gaps between the analog bus segments. Analog and/or digital signals are communicated between various instrument modules and external devices by means of cables connected to the instrument modules.
    Type: Grant
    Filed: July 30, 1984
    Date of Patent: July 28, 1987
    Assignee: Burr-Brown Corporation
    Inventors: James A. Jindrick, Shashikant M. Patil, Margaret S. Morrison, Littleton D. Page
  • Patent number: 4683531
    Abstract: A method for polling a plurality of remote processing units includes establishing a table of active and inactive remote processing units, sequentially polling each of the active processing units, at the conclusion of polling the active processing units, polling an inactive processing unit after which all of the active processing units are again polled. This sequence is repeated until all the active and inactive processing units have been polled. If in polling a processing unit, a response to the poll message indicates a change of status of the polled processing unit has occurred, the table is accordingly updated to reflect the current status of the processing unit.
    Type: Grant
    Filed: July 2, 1984
    Date of Patent: July 28, 1987
    Assignee: NCR Corporation
    Inventors: Russell K. Kelch, Don C. Finfrock, Donald J. Girard, Daniel B. Seevers, Barry D. Briggs, Gene R. Mathes
  • Patent number: 4680699
    Abstract: A terminal control apparatus for controlling data transfer between a terminal device and a central processor includes a terminal control unit for editing data and a communication control unit for transmission/reception of data. The terminal control unit and the communication control unit are operable independently of each other to carry out processings in parallel. In data transmission, when the terminal control unit completes the editing of a predetermined amount of data, the communication control unit transmits the edited data in parallel with edit processing of ensuing data by the terminal control unit. In data reception, when the communication control unit receives a predetermined amount of data, the terminal control unit edits the data in parallel with reception processing of ensuing data by the communication control unit.
    Type: Grant
    Filed: May 14, 1984
    Date of Patent: July 14, 1987
    Assignee: Hitachi, Ltd.
    Inventor: Megumi Uchino
  • Patent number: 4680702
    Abstract: A register unit includes means for storing pertinent data relative to a plurality of cache transactions, identifying the zones of an addressed word block which is the subject of the individual transactions. These data are selectively extracted from the register to control the merging of the identified zone or zones of the associated word with the remainder of the data in the addressed word block.
    Type: Grant
    Filed: April 27, 1984
    Date of Patent: July 14, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventor: Daniel M. McCarthy
  • Patent number: 4680728
    Abstract: A process and apparatus for entering a predetermined number of characters use an entry terminal having a display and a keyboard having a predetermined number of character entry keys presented in a first array (ten key numeric keyboard) and a predetermined number of function keys, with the predetermined number of character entry keys being fewer in number than the predetermined number of characters. The process comprises the steps of presenting on the display more than one cluster of characters to be selected, with each cluster containing fewer than the predetermined number of characters, and with each cluster of characters being presented on the display in a second array; selecting, via a function key, one of the clusters of characters which contains the character to be entered via the terminal; and actuating one of the character entry keys whose position in the first array bears a predetermined relationship with the position in the second array held by the character to be entered.
    Type: Grant
    Filed: October 17, 1984
    Date of Patent: July 14, 1987
    Assignee: NCR Corporation
    Inventors: William N. Davis, II, Ruth E. Nash
  • Patent number: 4677549
    Abstract: The invention relates to a digital data processor based upon the pipeline control system, which is particularly effective when the time required for reading a microprogram is relatively short. A microcycle is based upon the time required for reading the microprogram, and the operations on the data is executed in a pipeline system by dividing it up according to the determined microcycle. This is done by providing a destination latch register on the output side of the arithmetic unit. The invention further deals with the processors in which the destination latch register is provided on the input side of the arithmetic unit, or when the destination latch register is incorporated within the arithmetic unit, and a circuit setup for avoiding any contention for a register that may develop when executing a current instruction and the next instruction is provided in accordance with an added microprogram.
    Type: Grant
    Filed: February 23, 1983
    Date of Patent: June 30, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Koyo Katsura, Hideo Maejima
  • Patent number: 4675809
    Abstract: An execution processing device for executing variable length floating-point data of exponent part designated by two or more kinds of representation systems and fixed length floating-point data of exponent part designated by two or more kinds of representation systems, includes a converting circuit which converts the data of various representation systems into a common representation system which is capable of expressing the data in a common data form responsive to an operation mode that is provided to discriminate the various representation systems at the time of reading and operating on the data of the various representation systems stored in a storage unit according to the same load instruction. An arithmetic unit introduces the data converted by said converting circuit into the common representation system, which performs the operation designated by the same instruction, and which produces the operation result as the data of the common representation system.
    Type: Grant
    Filed: October 31, 1984
    Date of Patent: June 23, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Koichiro Omoda, Hozumi Hamada, Sakae Takahashi
  • Patent number: 4674064
    Abstract: A digital disk recorder is used to record digitized circular video images at the video frame rate. The digital pixel values for each image frame are written onto successive pages of a disk buffer memory (DBM) under video frame timing and are read from memory and written on disk under disk timing. A group of adjacent pixels are written simultaneously and in coincident locations on the several disks under clocks that are derived from disk. A programmable serial-to-parallel converter converts serially recorded pixels of any bit length back to parallel bits of the same number as before they were serialized.
    Type: Grant
    Filed: August 6, 1984
    Date of Patent: June 16, 1987
    Assignee: General Electric Company
    Inventor: Steven T. Vaughn
  • Patent number: 4665501
    Abstract: A computer workstation includes a display monitor and keyboard that can be used as a smart terminal for remote data processing in a first operating mode and that can be used as part of a microcomputer in a second operating mode. To provide maximum software compatibility separate display generators are provided, one for each operating mode. A network operating mode can also be provided.
    Type: Grant
    Filed: September 30, 1983
    Date of Patent: May 12, 1987
    Assignee: Esprit Systems, Inc.
    Inventors: Neil P. Saldin, Bruce J. Strum, Michael V. Livoti, Allan Maurer
  • Patent number: 4663728
    Abstract: A read/modify/write circuit (10) for a computer is used in conjunction with a main memory (12) in which block operations are executed using a plurality of data units. The circuit (10) includes a first register connected to receive a data block from the main memory (12), a second register connected to receive data units from a requestor, such as a processor (18) and a third register in which a resulting data block is produced which comprises the data units to be written into the main memory (12) and the remaining data units which were previously in the block read from memory (12). Multiplex circuits (70, 72, 74, 76, 78, 80, 82 and 84) are commanded by a decoder (136) in response to the processor (18) to selectively route sections of registers (26 and 28) into a register (106). The resulting data block is then transferred through the memory bus (14) for writing into the main memory (12).
    Type: Grant
    Filed: June 20, 1984
    Date of Patent: May 5, 1987
    Inventors: James R. Weatherford, Arthur T. Kimmel
  • Patent number: 4656578
    Abstract: In the processing of instructions in data processing systems it is not always possible to execute these instructions without interruption since particular situations, in the following called events can occur which necessitate a short interruption for executing the operations caused by such events before continuing the interrupted instruction processing. Such repetition however is only possible when the contents of the operation register containing the instruction is frozen during the interruption. Such a situation requires two actions: the first is the execution of a forced operation to resolve the event. The second action is a repetition of the instruction and execution phase of the interrupted instruction.
    Type: Grant
    Filed: September 4, 1984
    Date of Patent: April 7, 1987
    Assignee: International Business Machines Corporation
    Inventors: Herbert Chilinski, Klaus J. Getzlaff, Johann Hajdu, Stephan Richter
  • Patent number: 4649511
    Abstract: A controller for interfacing a single-chip microcomputer with external dynamic random-access memory, includes a subcircuit for generating a column-address strobe at a time after a row-address strobe is generated, and also includes a multiplexing subcircuit for providing the proper 8-bit portion of a 16-bit address output from the microprocessor to the 8-bit dynamic memory inputs, prior to receipt of the associated row-address or column-address strobe. The microprocessor utilizes the strobe-generation and multiplexing subcircuits to burst-refresh the dynamic memory, in one presently preferred embodiment. In another presently preferred embodiment, lines from an additional microprocessor output port are utilized with a resettable binary counter and a multiplicity of buffers, to count through the range of row addresses in cyclic fashion, with each address being incremented after the previously-addressed row of memory cells has been refreshed.
    Type: Grant
    Filed: July 25, 1983
    Date of Patent: March 10, 1987
    Assignee: General Electric Company
    Inventor: Michael Gdula