Patents Examined by Emily Yue Chan
  • Patent number: 4642759
    Abstract: A magnetic bubble memory based floppy disk emulating system is provided which is capable of emulating available industry standard floppy disk drives with a simple, microprocessor controlled system in which direct memory access techniques are used to free the microprocessor to perform the control functions necessary to emulate single/double density and floppy/minifloppy disks.
    Type: Grant
    Filed: April 2, 1984
    Date of Patent: February 10, 1987
    Assignee: Targa Electronics Systems Inc.
    Inventor: William R. Foster
  • Patent number: 4639856
    Abstract: A dual stream processor apparatus, for use in a multiprocessor computer system, is disclosed. The multiprocessor computer system includes at least a first processor and a second processor. A first apparatus and a second apparatus is included in both the first processor and the second processor for use when either the first or the second processor is inoperative. The first apparatus, disposed within the inoperative processor, suspends the functional operation of the inoperative processor. The second apparatus, disposed within the inoperative processor, transmits a miss signal to the other remaining functionally operational processor. When the other remaining processor receives the miss signal, it will not subsequently attempt to locate desired data in the cache of the inoperative processor. Rather, the other remaining processor will search for the desired data in the main memory in the event it cannot locate the data in its own cache.
    Type: Grant
    Filed: November 4, 1983
    Date of Patent: January 27, 1987
    Assignee: International Business Machines Corporation
    Inventors: John Hrustich, Wayne R. Sitler
  • Patent number: 4639862
    Abstract: A computer system has a CPU, a main memory and an additional memory storage which is difficult from the main memory and an external storage. The additional storage may transmit data with the main memory and/or the CPU.
    Type: Grant
    Filed: October 21, 1983
    Date of Patent: January 27, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Wada, Humio Goto
  • Patent number: 4631667
    Abstract: An asynchronous bus multiprocessor system where a plurality of microprogrammed processors communicate with a working memory through a common bus. Microinstructions are read out from working memory. At least one of the processors, in addition to conventional bus interface registers for latching of data, address and commands to be forwarded to the working memory through the bus, is provided with an additional interface register, devoted to the latching of a microinstruction address for a microinstruction to be read out from the working memory. The system is further provided with a multiplexer for selectively loading a microinstruction register either from a microprogram control memory or from the system common bus, via a direct path established between the system common bus and an input set of the multiplexer.
    Type: Grant
    Filed: June 27, 1983
    Date of Patent: December 23, 1986
    Assignee: Honeywell Information Systems Italia
    Inventors: Ferruccio Zulian, Vittorio Zanchi
  • Patent number: 4627016
    Abstract: A method and associated apparatus is provided for using data stored in one non-volatile memory to locate the next memory address in which to write data in another non-volatile memory of an electronic postage meter, comprising the steps of and associated apparatus for providing a first non-volatile memory for storing data therein including cumulative piece count data corresponding to the number of completed postage transactions, providing a second non-volatile memory for storing accounting data sequentially therein for each one of a predetermined number of trip cycles of the postage meter which number corresponds to the number of individually addressable trip cycle memory locations in the second non-volatile memory and defines a modulus of the second non-volatile memory, retrieving the cumulative piece count data from the first non-volatile memory during a power up cycle, dividing the cumulative piece count data by the modulus of the second non-volatile memory, and using the remainder resulting from the divisi
    Type: Grant
    Filed: August 22, 1984
    Date of Patent: December 2, 1986
    Assignee: Pitney Bowes Inc.
    Inventors: Wallace Kirschner, Easwaran C. N. Nambudiri, Douglas H. Patterson