Abstract: In an embodiment, a semiconductor device includes: a main bi-directional switch formed on a semiconductor substrate and including first and second gates, a first source electrically connected to a first voltage terminal, a second source electrically connected to a second voltage terminal, and a common drain; and a substrate control circuit. The substrate control circuit includes: a first diode and a second diode; a discharge circuit including a first transistor and a second transistor connected in a common source configuration to the semiconductor substrate; and a gate potential control circuit including a third diode and a fourth diode. The first diode has a forward voltage Vf1 and the third diode has a forward voltage Vf3, where Vf1?1.1Vf4 or Vf1?1.2Vf4 or Vf1?1.5Vf4 or Vf1?2Vf4.

Abstract: A silicon carbide semiconductor device includes a starting substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a gate insulating film, a gate electrode, an interlayer insulating film, an ohmic electrode, a barrier metal provided at the surface of the ohmic electrode and the surface of the interlayer insulating film, a surface electrode provided at the surface of the barrier metal, and a back electrode. The barrier metal has a three-layered structure including a first TiN film, a Ti film, and a second TiN film; the first TiN film contains TiN having a crystal grain size that is larger than a crystal grain size of TiN of the second TiN film.

Abstract: A capacitor comprises a stack of layers made of a semiconductor material having a band gap energy greater than 2.3 eV, the stack of layers comprising: an electrically insulating intermediate layer having a resistivity greater than 10 kohm·cm and comprising n- or p-type deep dopants producing energy levels more than 0.4 eV from the conduction band or the valence band of the semiconductor material, two contact layers having a resistivity less than or equal to 10 kohm·cm and comprising dopants of a type opposite to that of the deep dopants of the intermediate layer, the two contact layers being arranged on either side of the intermediate layer to form two pn junctions.

Abstract: Disclosed are a low-temperature processing method for improving a 4H—SiC/SiO2 interface based on a supercritical oxynitride, and use thereof. The method includes: performing standard cleaning on a silicon carbide sample to be processed; performing dry-oxygen oxidation on the cleaned silicon carbide sample to grow an oxide layer; placing the silicon carbide sample having the oxide layer on a support in a steady-state supercritical chamber; controlling a pressure and injecting nitrogen-oxygen gas into the supercritical device; increasing a temperature in the supercritical device from 23° C. to 500° C.; maintaining the above supercritical state until the processing ends; reducing a temperature of a reactor to room temperature after reaction ends, reducing the pressure to an atmospheric pressure, and taking out the reactor. The present disclosure allows for effective and quick decrease in the 4H—SiC/SiO2 interface state density, and also a significant decrease in the processing temperature.

Abstract: A self-aligning process method and a self-aligning process apparatus for reducing critical dimension variation of a SiC trench gate MOSFET structure are disclosed.

Abstract: A semiconductor structure including a fin of a vertical transistor structure, a top source drain region on a top side of the fin, a bottom source drain region on a bottom side of the fin, and a backside contact below and contacting the bottom source drain region.

Abstract: A radio frequency device includes a substrate, an epitaxial structure, a first electrode, a second electrode, a gate structure, a metal bulk, an auxiliary metal bulk, and a metal connection line. The first/second electrode includes a first/second electrode body and first/second electrode fingers. The gate structure includes a sub-gate having parallel portions and vertical portions alternately connected to one another in series to form a serpentine shape. The auxiliary metal bulk is arranged between corresponding adjacent two parallel portions and between a corresponding vertical portion and an end of a corresponding first electrode finger. The metal bulk is arranged between the auxiliary metal bulk and the vertical portion corresponding to the auxiliary metal bulk. The metal connection line connects the metal bulk to the second electrode body and is insulated from the sub-gate. A radio frequency front-end apparatus including the radio frequency device is also disclosed.

Abstract: A transistor according to the disclosure includes a semiconductor substrate, a source pad provided on an upper surface of the semiconductor substrate, a plurality of source electrodes provided on the upper surface of the semiconductor substrate and arranged in an arrangement direction, the plurality of source electrodes each including a first end connected to the source pad and a second end on a side opposite to the source pad, a plurality of drain electrodes arranged alternately with the plurality of source electrodes in the arrangement direction, a gate electrode and a first wire configured to connect the second ends of a plurality of central electrodes provided at a central part of the semiconductor substrate in the arrangement direction among the plurality of source electrodes, and not to connect the second ends of the source electrodes other than the plurality of central electrodes.

Abstract: A method includes forming a semiconductor layer over a substrate; depositing a first ferroelectric layer over a channel region of the semiconductor layer; depositing a first dielectric layer over the first ferroelectric layer; depositing a second ferroelectric layer over the first dielectric layer; depositing a gate metal layer over the second ferroelectric layer; patterning the gate metal layer, the second ferroelectric layer, the first dielectric layer, and the first ferroelectric layer to form a gate structure; and forming source/drain regions in the semiconductor layer and on opposite sides of the gate structure.

Abstract: First and second buffer regions and an n?-type drift region are sequentially formed by epitaxial growth on an n+-type starting substrate. An impurity concentration of the first buffer region is higher than that of the n?-type drift region and lower than that of the n+-type starting substrate. An impurity concentration of the second buffer region is higher than that of the first buffer region and continuously increases by a first impurity concentration gradient from a first gradient changing point toward the n?-type drift region to a second gradient changing point toward the first buffer region; continuously decreases by a second impurity concentration gradient from the first gradient changing point to a first interface; and continuously decreases by a third impurity concentration gradient from the second gradient changing point to a second interface. The second impurity concentration gradient is lower than the third impurity concentration gradient.

Abstract: A method of manufacturing a semiconductor device includes forming a trench that extends from a first surface into a silicon carbide body. A first doped region and an oppositely doped second doped region are formed in the silicon carbide body. A lower layer structure is formed on a lower sidewall portion of the trench. An upper layer stack is formed on an upper sidewall portion and/or on the first surface. The first doped region and the upper layer stack are in direct contact along the upper sidewall portion and/or on the first surface. The second doped region and the lower layer structure are in direct contact along the lower sidewall portion.

Abstract: A method for manufacturing an optoelectronic device including forming, by metal-organic chemical vapor deposition, MOCVD, wire-shaped, conical, or frustoconical semiconductor elements made of a III-V compound, doped or undoped, each semiconductor element extending along an axis and including a top, and forming by remote plasma chemical vapor deposition, RPCVD, or by molecular-beam epitaxy, MBE, or by hydride vapor phase epitaxy, HVPE, for each semiconductor element, an active area only on said top including at least a first semiconductor layer made of the III-V compound and a second semiconductor layer made of the III-V compound and an additional group-III element.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a valley inwardly positioned on a top surface of the substrate; a programmable insulating layer conformally positioned on the valley and including a V-shaped cross-sectional profile; and a top electrode positioned on the programmable insulating layer. The programmable insulating layer is configured to be blown out under a programming voltage.

Abstract: A P-type gate HEMT device includes a substrate, a buffer layer, a channel layer, and a barrier layer sequentially arranged from bottom to top. A first P-type material layer is arranged on the barrier layer. A first source and a first drain are respectively arranged on two sides of the first P-type material layer. A first conductive layer is arranged on the first P-type material layer. A second P-type material layer is connected to the first P-type material layer. A second conductive layer is connected to the second P-type material layer. A third conductive layer is connected to the second P-type material layer. The first P-type material layer, the first source, the first drain, and the first conductive layer form a normally-off N-channel transistor. The second P-type material layer, the second conductive layer, and the third conductive layer form a normally-on P-channel transistor.

Abstract: A sacrificial layer is formed over a first channel structure of an N-type transistor (NFET) and over a second channel structure of a P-type transistor (PFET). A PFET patterning process is performed at least in part by etching away the sacrificial layer in the PFET while protecting the NFET from being etched. After the PFET patterning process has been performed, a P-type work function (WF) metal layer is deposited in both the NFET and the PFET. An NFET patterning process is performed at least in part by etching away the P-type WF metal layer and the sacrificial layer in the NFET while protecting the PFET from being etched. After the NFET patterning process has been performed, an N-type WF metal layer is deposited in both the NFET and the PFET.

Abstract: The present disclosure generally relates to a bird's beak profile of a field oxide region. In an example, a semiconductor device structure includes a semiconductor substrate, a dielectric oxide layer, and a field oxide region. The semiconductor substrate has a top surface. The dielectric oxide layer is over the top surface of the semiconductor substrate. The field oxide region is over the semiconductor substrate. The field oxide region is connected to the dielectric oxide layer through a bird's beak region. A lower surface of the bird's beak region interfaces with the semiconductor substrate. In a cross-section along a direction from the field oxide region to the dielectric oxide layer, the lower surface of the bird's beak region does not have a slope with a magnitude that exceeds 0.57735, where rise of the slope is in a direction normal to the top surface of the semiconductor substrate.

Abstract: A semiconductor device includes: a first trench provided from the upper surface of a first impurity layer to the inside of a first semiconductor layer, a second trench provided from the upper surface of a second impurity layer to a position lower than the lower surface of the first semiconductor layer; a second semiconductor layer of a first conductivity type provided on the surface layer of the first impurity layer and disposed to be interposed between the first trench and a third impurity layer in a plan view; and a third semiconductor layer of the first conductivity type provided in the surface layer of the second impurity layer and disposed to be interposed between the second trench and the third impurity layer in the plan view.

Abstract: A display device includes a thin film layer test part capable of measuring a film quality of a deposited thin film layer, and the thin film layer test part includes a first wiring part formed at an upper surface of a thin film layer to be tested, pad parts connected to opposite ends of the first wiring part, a second wiring part formed at a lower surface of the thin film layer, and a pad part connected to the second wiring part, thus the display device can check a film quality of the thin film layer, for example, through detection of a resistance difference between the first wiring part and the second wiring part by the thin film layer test part.

Abstract: A trench junction field effect transistor (trench JFET) includes a mesa region confined by first and second trenches along a first lateral direction. The first and second trenches extend into a semiconductor body from a first surface of the semiconductor body. A mesa channel region of a first conductivity type is confined, along the first lateral direction, by first and second gate regions of a second conductivity type. A first pn junction is defined by the mesa channel region and the first gate region. A second pn junction is defined by the mesa channel region and the second gate region. The mesa channel region includes, along the first lateral direction, first, second and third mesa channel sub-regions having a same extent along the first lateral direction.

Abstract: An HEMT device includes a substrate, a buffer layer, a channel layer, and a barrier layer sequentially disposed in such order; a source electrode and a drain electrode disposed oppositely on an active region, and a gate electrode including a comb structure disposed in a gate region between the source electrode and the drain electrode. The comb structure includes a comb stem portion and a plurality of comb tooth portions. The comb tooth portions are spaced apart from each other in a gate width direction. The comb stem portion is disposed on the barrier layer. Distances between the comb tooth portions in the gate width direction are unequal and irregular. The comb tooth portions penetrate into the barrier layer to equal depths, and the depths are no smaller than half of a thickness of the barrier layer. A method for making the HEMT device is also provided.