Abstract: A high electron mobility transistor includes a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate in sequence. A source electrode and a drain electrode are disposed on the semiconductor channel layer. A semiconductor cap layer is disposed on the semiconductor barrier layer. A first dielectric layer is disposed over the source electrode, the semiconductor cap layer and the drain electrode. A first via passes through the first dielectric layer and is extended downward onto the semiconductor cap layer. A gate electrode is disposed on the first dielectric layer and in contact with the first via. A first field plate is disposed in the first dielectric layer. A second field plate is disposed on the first dielectric layer and in contact with the first field plate.

Abstract: A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is first subjected to the nitride treatment and is then subjected to the oxidation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a nitride-based multiple semiconductor layer, a gate electrode, a gate insulator layer, and a source electrode. The first nitride-based semiconductor layer includes a drift region and at least two doped barrier regions defining an aperture in the drift region. The nitride-based multiple semiconductor layer structure is disposed over the first nitride-based semiconductor layer and has a first heterojunction and a second heterojunction which are separated from each other. The gate electrode is received by the nitride-based multiple semiconductor layer structure and vertically aligns with the aperture in the drift region. The gate insulator layer is disposed between the nitride-based multiple semiconductor layer structure and the gate electrode.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, the tiers including conductive materials that form part of respective control gates for memory cells of the apparatus; a staircase structure formed in the tiers, the conductive materials including respective portions that collectively form a part of the staircase structure, the staircase structure including a sidewall on a side of the staircase structure; a dielectric liner formed on the sidewall; recesses formed in respective tiers and adjacent the sidewall such that respective portions of the dielectric liner are located in the recesses; and a contact structure extending through a portion of the dielectric liner, wherein the portions of the dielectric liner are between the contract structure and the conductive materials.

Abstract: A display device may include a wiring pad and a dummy pad disposed on a substrate and spaced apart from each other, a planarization layer disposed over the wiring pad and the dummy pad, a first insulating layer disposed on the planarization layer, the first insulating layer exposing a portion of the planarization layer, a first pad electrode and a second pad electrode disposed on the planarization layer and the first insulating layer, the first pad electrode electrically connected to the wiring pad and the second pad electrode electrically connected to the dummy pad, a second insulating layer disposed on the first pad electrode and the second pad electrode, conductive particles disposed on the first pad electrode and the second pad electrode, the conductive particles having a cylindrical shape, and an external device disposed on the conductive particles.

Abstract: Metal oxide semiconductor field effect transistors (MOSFET) including deep P-wells are disclosed. MOSFETs may include a drift layer disposed over a substrate, and a P-well disposed within the drift layer. The P-well may include a first portion disposed directly over the drift layer, where the first portion includes a first doping concentration. The P-well may also include a second portion separated from the drift layer by the first portion. The second portion may include a second doping concentration distinct from the first doping concentration of the first portion. Additionally, the MOSFET may include an N-source disposed at least partially over the second portion of the P-well, an oxide layer disposed over the N-source and the drift layer, and a gate layer disposed over the oxide layer.

Abstract: A semiconductor layer in a semiconductor device includes a drift region of a first conductivity type, a body region of a second conductivity type disposed above the drift region, a source region of the first conductivity type disposed above the body region, and a first contact region and a second contact region each having a higher concentration of second conductivity-type impurities than the body region. The first contact region is located in an active region, and reaches the body region beyond the source region. The second contact region is located in an intermediate region, reaches the body region beyond the source region, and extends around the source region along a peripheral edge of the source region. Concentration distributions of the second conductivity-type impurities in a depth direction of the first contact region and the second contact region match with each other.

Abstract: Provided is a method of producing a micro-LED panel that can produce a micro-LED panel with excellent display quality by reducing misalignment of micro-LED chips and can achieve an increased yield. The method of producing a micro-LED panel includes: producing a micro-LED chip including a micro-LED, a first contact electrode, and a light blocking component; producing an array substrate including a switching element, a second contact electrode, and an insulating film; and placing the micro-LED chip on the array substrate. The light blocking component includes a bump with an inclined surface. The insulating film includes a dent with an inclined surface. The placing of the micro-LED chip includes electrically connecting the first contact electrode to the second contact electrode by making the bump of the light blocking component opposite to the dent of the insulating film.

Abstract: A transistor device and a method for forming a transistor device are disclosed. The transistor device includes: a SiC semiconductor body that includes a first semiconductor layer and a second semiconductor layer formed on top of the first semiconductor; a trench structure extending from a first surface of the semiconductor body through the second semiconductor layer into the first semiconductor layer; a drain region arranged in the first semiconductor layer; and a plurality of transistor cells each coupled between the drain region and a source node. The trench structure subdivides the second semiconductor layer into a plurality of mesa regions and includes at least one cavity. At least one of the plurality of transistor cells is at least partially integrated in each of the mesa regions.

Abstract: A semiconductor device manufacturing method of embodiments includes: performing first ion implantation for implanting aluminum into a silicon carbide layer with a first dose amount; performing first heat treatment at a temperature equal to or more than 1600° C.; performing first etching process for etching a surface of the silicon carbide layer in an atmosphere containing plasma generated from a gas containing halogen and oxygen; performing second etching process for etching the surface in an atmosphere containing hydrogen plasma or atomic hydrogen; forming a silicon oxide film on the surface; and forming a gate electrode on the silicon oxide film.

Abstract: A semiconductor device includes an n-type semiconductor substrate, a trench, a gate electrode formed in the trench via the gate insulating film, a p-type base region formed in the semiconductor substrate, and an n-type emitter region formed in the base region. The trench extends in a Y direction, in a plan view. Adjacent ones of a plurality of emitter regions are formed to be spaced apart from each other by a distance, along the Y direction. The distance is wider than ? of a width of each of the emitter regions in the Y direction and narrower than the width.

Abstract: Transistor devices are provided. In one example, the transistor device includes a channel layer. The transistor device includes a multilayer barrier structure on the channel layer. The multilayer barrier structure includes a first Group III-nitride layer and a second Group III-nitride layer on the first Group III-nitride layer and opposite to the channel layer. The first Group III-nitride layer has a thickness greater than a thickness of the second Group III-nitride layer. An aluminum concentration of the first Group III-nitride layer is at least two times greater than an aluminum concentration of the second Group III-nitride layer.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a valley inwardly positioned on a top surface of the substrate; a programmable insulating layer conformally positioned on the valley and including a V-shaped cross-sectional profile; and a top electrode positioned on the programmable insulating layer. The programmable insulating layer is configured to be blown out under a programming voltage.

Abstract: In an embodiment, a semiconductor device includes: a main bi-directional switch formed on a semiconductor substrate and including first and second gates, a first source electrically connected to a first voltage terminal, a second source electrically connected to a second voltage terminal, and a common drain; and a substrate control circuit. The substrate control circuit includes: a first diode and a second diode; a discharge circuit including a first transistor and a second transistor connected in a common source configuration to the semiconductor substrate; and a gate potential control circuit including a third diode and a fourth diode. The first diode has a forward voltage Vf1 and the third diode has a forward voltage Vf3, where Vf1?1.1Vf4 or Vf1?1.2Vf4 or Vf1?1.5Vf4 or Vf1?2Vf4.

Abstract: A silicon carbide semiconductor device includes a starting substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a gate insulating film, a gate electrode, an interlayer insulating film, an ohmic electrode, a barrier metal provided at the surface of the ohmic electrode and the surface of the interlayer insulating film, a surface electrode provided at the surface of the barrier metal, and a back electrode. The barrier metal has a three-layered structure including a first TiN film, a Ti film, and a second TiN film; the first TiN film contains TiN having a crystal grain size that is larger than a crystal grain size of TiN of the second TiN film.

Abstract: A capacitor comprises a stack of layers made of a semiconductor material having a band gap energy greater than 2.3 eV, the stack of layers comprising: an electrically insulating intermediate layer having a resistivity greater than 10 kohm·cm and comprising n- or p-type deep dopants producing energy levels more than 0.4 eV from the conduction band or the valence band of the semiconductor material, two contact layers having a resistivity less than or equal to 10 kohm·cm and comprising dopants of a type opposite to that of the deep dopants of the intermediate layer, the two contact layers being arranged on either side of the intermediate layer to form two pn junctions.

Abstract: Disclosed are a low-temperature processing method for improving a 4H—SiC/SiO2 interface based on a supercritical oxynitride, and use thereof. The method includes: performing standard cleaning on a silicon carbide sample to be processed; performing dry-oxygen oxidation on the cleaned silicon carbide sample to grow an oxide layer; placing the silicon carbide sample having the oxide layer on a support in a steady-state supercritical chamber; controlling a pressure and injecting nitrogen-oxygen gas into the supercritical device; increasing a temperature in the supercritical device from 23° C. to 500° C.; maintaining the above supercritical state until the processing ends; reducing a temperature of a reactor to room temperature after reaction ends, reducing the pressure to an atmospheric pressure, and taking out the reactor. The present disclosure allows for effective and quick decrease in the 4H—SiC/SiO2 interface state density, and also a significant decrease in the processing temperature.

Abstract: A self-aligning process method and a self-aligning process apparatus for reducing critical dimension variation of a SiC trench gate MOSFET structure are disclosed.

Abstract: A semiconductor structure including a fin of a vertical transistor structure, a top source drain region on a top side of the fin, a bottom source drain region on a bottom side of the fin, and a backside contact below and contacting the bottom source drain region.

Abstract: A radio frequency device includes a substrate, an epitaxial structure, a first electrode, a second electrode, a gate structure, a metal bulk, an auxiliary metal bulk, and a metal connection line. The first/second electrode includes a first/second electrode body and first/second electrode fingers. The gate structure includes a sub-gate having parallel portions and vertical portions alternately connected to one another in series to form a serpentine shape. The auxiliary metal bulk is arranged between corresponding adjacent two parallel portions and between a corresponding vertical portion and an end of a corresponding first electrode finger. The metal bulk is arranged between the auxiliary metal bulk and the vertical portion corresponding to the auxiliary metal bulk. The metal connection line connects the metal bulk to the second electrode body and is insulated from the sub-gate. A radio frequency front-end apparatus including the radio frequency device is also disclosed.