Abstract: A semiconductor device includes a source region and a drain region disposed in a substrate, a gate stack including a floating gate and a control gate disposed between the source region and the drain region, a select gate insulating layer disposed on a sidewall of the gate stack, and a select gate disposed on the select gate insulating layer, the select gate having a height higher than a height of the gate stack or a height of the control gate.

Abstract: A display substrate and a display apparatus are provided. The display substrate includes sub-pixels, a pixel defining pattern, and a defining structure. The sub-pixel includes a light-emitting functional layer. The pixel defining pattern includes first openings and second openings, a portion in the defining structure exposed by the second opening is configured to isolate the light-emitting functional layer. The sub-pixels include a first sub-pixel and a second sub-pixel, a turn-on voltage of the first sub-pixel is higher than that of the second sub-pixel; the defining structure includes a first defining structure surrounding the second sub-pixel and a second defining structure surrounding the second sub-pixel; the first defining structure is not exposed by the second opening; or a proportion of the first defining structure exposed by the second opening is less than a proportion of the second defining structure exposed by the second opening.

Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.

Abstract: In an example, a semiconductor device includes an active trench region and an intersecting trench. The active region includes an active shield electrode and the intersecting trench includes an intersecting shield electrode. A coupling trench region connects the active trench region to the intersecting trench region. The coupling trench region includes a coupling shield electrode. The coupling shield electrode and the intersecting shield electrode are provided proximate to a termination mesa region. One or more of the coupling shield electrode or the intersecting shield electrode is thinner than the active shield electrode. The thinner shield electrode reduces depletion in the termination mesa region to improve, among other things, breakdown voltage performance.

Abstract: A magnetoresistive random access memory (MRAM) includes a pillar structure having a bottom electrode and a magnetic tunnel junction (MTJ) having a reference layer, a free layer and a tunnel barrier disposed between the reference layer and the free layer. The MTJ is disposed on the bottom electrode. A top electrode is disposed on the MTJ. The top electrode includes two or more tiers wherein each tier successively includes a smaller footprint.

Abstract: A method of manufacturing an integrated circuit device includes forming, on a substrate, a fin-type active region and a stack structure in which sacrificial semiconductor layers and nanosheet semiconductor layers are alternately stacked one-by-one, forming a first local liner on a sidewall of the stack structure to cover a sidewall of a bottom sacrificial semiconductor layer, which is closest to the fin-type active region and expose sidewalls of other sacrificial semiconductor layers, forming a second local liner on the sidewall of the stack structure to cover the sidewalls of the other sacrificial semiconductor layers except for the bottom sacrificial semiconductor layer, exposing the bottom sacrificial semiconductor layer by removing the first local liner, forming a bottom insulating space exposing a fin top surface of the fin-type active region by removing the bottom sacrificial semiconductor layer, and forming a bottom insulating structure in the bottom insulating space.

Abstract: A SiC semiconductor device includes a SiC chip having a main surface, a trench gate structure formed at the main surface, a trench source structure formed at the main surface away from the trench gate structure in one direction, an insulating film covering the trench gate structure and the trench source structure above the main surface, a gate main surface electrode formed on the insulating film and a gate wiring that is led out from the gate main surface electrode onto the insulating film such as to cross the trench gate structure and the trench source structure in the one direction, and that is electrically connected to the trench gate structure through the insulating film, and that faces the trench source structure with the insulating film between the trench source structure and the gate wiring.

Abstract: A quantum dot device and an electronic device. The quantum dot device includes a first electrode and a second electrode, a light emitting layer disposed between the first electrode and the second electrode and including quantum dots, a first charge auxiliary layer disposed between the second electrode and the light emitting layer and enhancing transport of first charge carriers from the second electrode to the light emitting layer, and a buffer layer disposed between the light emitting layer and the first charge auxiliary layer and enhancing extraction of second charge carriers from the light emitting layer.

Abstract: An electronic component comprises a first layer and a second layer, wherein a main surface of the first layer is arranged opposite a main surface of the second layer. The first layer comprises a polarized first material. A polarization of the first material faces in a first direction. The second layer comprises a polarized second material having at least one polarization state, wherein a direction of a polarization of the second material at least in the one polarization state of the second material is at least in part opposite to the first direction such that a charge zone forms along the main surface of the first and/or the second layer, said charge zone being electrically conductive at least when the second material is in the one polarization state.

Abstract: A semiconductor device includes a transistor having macro cells. A plurality of the macro cells include a first macro cell and a second macro cell. Each first and second macro cell includes trenches formed in a first main surface of a semiconductor substrate. The trenches pattern the semiconductor substrate into mesas and include a conductive trench, with a conductive material in the conductive trench being electrically connected to a terminal. A majority of all trenches of the first macro cell exclusively run in a first direction. A majority of all trenches of the second macro cell exclusively run in a second direction different from the first direction. At least one first macro cell is arranged adjacent to at least one second macro cell.

Abstract: A high electron mobility transistor includes a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate in sequence. A source electrode and a drain electrode are disposed on the semiconductor channel layer. A semiconductor cap layer is disposed on the semiconductor barrier layer. A first dielectric layer is disposed over the source electrode, the semiconductor cap layer and the drain electrode. A first via passes through the first dielectric layer and is extended downward onto the semiconductor cap layer. A gate electrode is disposed on the first dielectric layer and in contact with the first via. A first field plate is disposed in the first dielectric layer. A second field plate is disposed on the first dielectric layer and in contact with the first field plate.

Abstract: A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is first subjected to the nitride treatment and is then subjected to the oxidation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a nitride-based multiple semiconductor layer, a gate electrode, a gate insulator layer, and a source electrode. The first nitride-based semiconductor layer includes a drift region and at least two doped barrier regions defining an aperture in the drift region. The nitride-based multiple semiconductor layer structure is disposed over the first nitride-based semiconductor layer and has a first heterojunction and a second heterojunction which are separated from each other. The gate electrode is received by the nitride-based multiple semiconductor layer structure and vertically aligns with the aperture in the drift region. The gate insulator layer is disposed between the nitride-based multiple semiconductor layer structure and the gate electrode.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, the tiers including conductive materials that form part of respective control gates for memory cells of the apparatus; a staircase structure formed in the tiers, the conductive materials including respective portions that collectively form a part of the staircase structure, the staircase structure including a sidewall on a side of the staircase structure; a dielectric liner formed on the sidewall; recesses formed in respective tiers and adjacent the sidewall such that respective portions of the dielectric liner are located in the recesses; and a contact structure extending through a portion of the dielectric liner, wherein the portions of the dielectric liner are between the contract structure and the conductive materials.

Abstract: A display device may include a wiring pad and a dummy pad disposed on a substrate and spaced apart from each other, a planarization layer disposed over the wiring pad and the dummy pad, a first insulating layer disposed on the planarization layer, the first insulating layer exposing a portion of the planarization layer, a first pad electrode and a second pad electrode disposed on the planarization layer and the first insulating layer, the first pad electrode electrically connected to the wiring pad and the second pad electrode electrically connected to the dummy pad, a second insulating layer disposed on the first pad electrode and the second pad electrode, conductive particles disposed on the first pad electrode and the second pad electrode, the conductive particles having a cylindrical shape, and an external device disposed on the conductive particles.

Abstract: Metal oxide semiconductor field effect transistors (MOSFET) including deep P-wells are disclosed. MOSFETs may include a drift layer disposed over a substrate, and a P-well disposed within the drift layer. The P-well may include a first portion disposed directly over the drift layer, where the first portion includes a first doping concentration. The P-well may also include a second portion separated from the drift layer by the first portion. The second portion may include a second doping concentration distinct from the first doping concentration of the first portion. Additionally, the MOSFET may include an N-source disposed at least partially over the second portion of the P-well, an oxide layer disposed over the N-source and the drift layer, and a gate layer disposed over the oxide layer.

Abstract: A semiconductor layer in a semiconductor device includes a drift region of a first conductivity type, a body region of a second conductivity type disposed above the drift region, a source region of the first conductivity type disposed above the body region, and a first contact region and a second contact region each having a higher concentration of second conductivity-type impurities than the body region. The first contact region is located in an active region, and reaches the body region beyond the source region. The second contact region is located in an intermediate region, reaches the body region beyond the source region, and extends around the source region along a peripheral edge of the source region. Concentration distributions of the second conductivity-type impurities in a depth direction of the first contact region and the second contact region match with each other.

Abstract: Provided is a method of producing a micro-LED panel that can produce a micro-LED panel with excellent display quality by reducing misalignment of micro-LED chips and can achieve an increased yield. The method of producing a micro-LED panel includes: producing a micro-LED chip including a micro-LED, a first contact electrode, and a light blocking component; producing an array substrate including a switching element, a second contact electrode, and an insulating film; and placing the micro-LED chip on the array substrate. The light blocking component includes a bump with an inclined surface. The insulating film includes a dent with an inclined surface. The placing of the micro-LED chip includes electrically connecting the first contact electrode to the second contact electrode by making the bump of the light blocking component opposite to the dent of the insulating film.

Abstract: A transistor device and a method for forming a transistor device are disclosed. The transistor device includes: a SiC semiconductor body that includes a first semiconductor layer and a second semiconductor layer formed on top of the first semiconductor; a trench structure extending from a first surface of the semiconductor body through the second semiconductor layer into the first semiconductor layer; a drain region arranged in the first semiconductor layer; and a plurality of transistor cells each coupled between the drain region and a source node. The trench structure subdivides the second semiconductor layer into a plurality of mesa regions and includes at least one cavity. At least one of the plurality of transistor cells is at least partially integrated in each of the mesa regions.

Abstract: A semiconductor device manufacturing method of embodiments includes: performing first ion implantation for implanting aluminum into a silicon carbide layer with a first dose amount; performing first heat treatment at a temperature equal to or more than 1600° C.; performing first etching process for etching a surface of the silicon carbide layer in an atmosphere containing plasma generated from a gas containing halogen and oxygen; performing second etching process for etching the surface in an atmosphere containing hydrogen plasma or atomic hydrogen; forming a silicon oxide film on the surface; and forming a gate electrode on the silicon oxide film.