Patents Examined by Eric A. Ward
  • Patent number: 11990413
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers. The electrically conductive layers include an intermetallic alloy of aluminum and at least one metal other than aluminum. Memory openings vertically extend through the alternating stack. Memory opening fill structures are located in a respective one of the memory openings and include a respective vertical semiconductor channel and a respective vertical stack of memory elements.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: May 21, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Linghan Chen, Raghuveer S. Makala, Fumitaka Amano
  • Patent number: 11990539
    Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate capping layer, a dielectric layer, and a gate electrode. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate capping layer is disposed on the semiconductor barrier layer, and the dielectric layer conformally covers the gate capping layer and surrounds the periphery of the gate capping layer. The gate electrode is disposed on the dielectric layer and covers at least one sidewall of the gate capping layer.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: May 21, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Po-Yu Yang
  • Patent number: 11990409
    Abstract: Provided is a semiconductor device including a front-end-of-line (FEOL) structure and a back-end-of-line (BEOL) structure connected to the FEOL structure, wherein the FEOL structure includes at least one source/drain region and at least one gate structure, and the BEOL structure includes: a plurality of 1st fine metal lines arranged in a row with a same pitch, each of the plurality of 1st fine metal lines having a same width; and at least one 1st wide metal line formed at a side of the plurality of 1st fine metal lines, the 1st wide metal line having a width greater than the width of the 1st fine metal line, and wherein each of the plurality of 1st fine metal lines includes a material different from a material included in the 1st wide metal line.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: May 21, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taeyong Bae, Hoonseok Seo
  • Patent number: 11984444
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a first active region extending along a first direction. The semiconductor device also includes a second active region extending along the first direction. The semiconductor device further includes a first gate extending along a second direction perpendicular to the first direction. The first gate has a first segment disposed between the first active region and the second active region. In addition, the semiconductor device includes a first electrical conductor extending along the second direction and across the first active region and the second active region, wherein the first segment of the first gate and the first electrical conductor are partially overlapped to form a first capacitor.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Hui Chen, Wan-Te Chen, Tzu Ching Chang, Tsung-Hsin Yu
  • Patent number: 11984479
    Abstract: The present disclosure relates to a field effect transistor (FET) structure. The FET structure has a substrate, an active region, a dielectric layer provided over a channel of the active region and a gate provided over the dielectric layer. The active region comprises a source, a drain and the channel provided between the source and the drain. The active region is surrounded by an isolation trench, such that width edges of the channel are directly adjacent to the isolation trench. Current paths run between the source and the drain, through the channel. The FET is configured such that current paths running proximal to the channel edges are reduced or weaker in comparison to a dominant current path running through a center of the channel. One or more of the channel, the dielectric layer or the substrate can be modified or adapted to provide the reduced and dominant current paths.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: May 14, 2024
    Assignee: Analog Devices International Unlimited Company
    Inventors: Dennis A. Dempsey, Andrew Christopher Linehan, Seamus P. Whiston, David J. Rohan
  • Patent number: 11984501
    Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: May 14, 2024
    Assignee: ROHM CO., LTD.
    Inventors: So Nagakura, Satoshi Iwahashi
  • Patent number: 11980085
    Abstract: A display device includes a sensing line and a data driver. The sensing line is in a display panel. The data driver includes a plurality of integrated circuits. Each of the integrated circuits includes an interface, which includes a mobile industry processor interface (MIPI) and a crack detector. The crack detector detects cracks of the panel based on the sensing line and transmits and receives information corresponding to the crack to and from adjacent ones of the integrated circuits using a transmission terminal and a reception terminal in the MIPI.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: May 7, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventor: Ho Seok Han
  • Patent number: 11973024
    Abstract: A semiconductor memory device according to an embodiment includes a substrate, conductive layers, pillars, and contacts. The substrate includes first and second areas, and block areas. The conductive layers are divided for each of the block areas. The conductive layers includes terraced portions. The contacts are respectively provided on the terraced portions for each of the block areas. The second area includes a first sub area and a second sub area. The first sub area includes a first stepped structure. The second sub area includes a second stepped structure and a first pattern. The first pattern is continuous with any one of the conductive layers. The first pattern is arranged between the first stepped structure and the second stepped structure.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: April 30, 2024
    Assignee: Kioxia Corporation
    Inventor: Hisashi Kato
  • Patent number: 11967619
    Abstract: Laterally-gated transistors and lateral Schottky diodes are disclosed. The FET includes a substrate, source and drain electrodes, channel, a gate electrode structure, and a dielectric layer. The gate electrode structure includes an electrode in contact with the channel and a lateral field plate adjacent to the electrode. The dielectric layer is disposed between the lateral field plate and the channel. The lateral field plate contacts the dielectric layer and to modulate an electric field proximal to the gate electrode proximal to the drain or source electrodes. Also disclosed is a gate electrode structure with lateral field plates symmetrically disposed relative to the gate electrode. Also disclosed in a substrate with dielectric structures buried in the substrate remote from the gate electrode structure. A lateral Schottky diode having an anode structure includes an anode (A), cathodes (C) and lateral field plates located between the anode and the cathodes.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: April 23, 2024
    Assignee: TELEDYNE SCIENTIFIC & IMAGING, LLC
    Inventors: Keisuke Shinohara, Casey King, Eric Regan, Miguel Urteaga
  • Patent number: 11967589
    Abstract: A micro multi-color LED device includes two or more LED structures for emitting a range of colors. The two or more LED structures are vertically stacked to combine light from the two more LED structures. Light from the micro multi-color LED device is emitted horizontally from each of the LED structures and reflected upward via some reflective structures. In some embodiments, each LED structure is connected to a pixel driver and/or a common electrode. The LED structures are bonded together through bonding layers. In some embodiments, planarization layers enclose each of the LED structures or the micro multi-color LED device. In some embodiments, one or more of reflective layers, refractive layers, micro-lenses, spacers, and reflective cup structures are implemented in the device to improve the LED emission efficiency. A display panel comprising an array of the micro tri-color LED devices has a high resolution and a high illumination brightness.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: April 23, 2024
    Assignee: Jade Bird Display (Shanghai) Limited
    Inventors: Qunchao Xu, Huiwen Xu, Qiming Li
  • Patent number: 11961896
    Abstract: Systems and methods for building passive and active electronics with diamond-like carbon (DLC) coatings are provided herein. DLC may be layered upon substrates to form various components of electronic devices. Passive components such as resistors, capacitors, and inductors may be built using DLC as a dielectric or as an insulating layer. Active components such as diodes and transistors may be built with the DLC acting substantially like a semiconductor. The amount of sp2 and sp3 bonded carbon atoms may be varied to modify the properties of the DLC for various electronic components.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: April 16, 2024
    Assignee: Honeywell Federal Manufacturing & Technologies, LLC
    Inventors: Erik Joseph Timpson, Justin M. Schlitzer, Thomas Matthew Selter, Michael Walsh
  • Patent number: 11961921
    Abstract: A semiconductor device has a semiconductor substrate and a semiconductor film doped with impurities that is formed so as to cover an inner wall surface of a trench formed so as to extend from a first surface of the semiconductor substrate towards an interior thereof. The semiconductor film is formed so as to extend continuously from the inner wall surface to the first surface of the semiconductor substrate. The semiconductor device further has an opposite electrode having a first portion that is provided at a position opposing the semiconductor substrate while sandwiching the semiconductor film therebetween, and that extends on the first surface of the semiconductor substrate, and a second portion that is continuous with the first portion and extends so as to fill the trench. The semiconductor device further has an insulating film that insulates the semiconductor film from the opposite electrode.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: April 16, 2024
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hiroshi Shibata
  • Patent number: 11956957
    Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: April 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Young Kim, Woo Sung Yang, Sung-Min Hwang, Suk Kang Sung, Joon-Sung Lim
  • Patent number: 11957036
    Abstract: A perovskite light-emitting diode and a method of manufacturing the same are provided. The method includes steps of providing a substrate, disposing a first electrode layer, a hole transport layer, and a perovskite precursor liquid layer on the substrate, coating the perovskite precursor liquid layer with a first solvent, performing a first thermal process to form a perovskite prefabricated layer, coating the perovskite prefabricated layer with a second solvent, and performing a second thermal process to form a perovskite light-emitting layer.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: April 9, 2024
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Yongwei Wu
  • Patent number: 11957024
    Abstract: An OLED panel includes a display area and a non-display area around the display area; a substrate, a driving device layer and a light emitting device layer arranged in the display area, an encapsulation layer covering the light emitting device layer; and a touch layer located on a side of the encapsulation layer facing away from the substrate, the touch layer comprising a touch electrode and a touch wire. The non-display area includes an electrostatic discharge portion, the electrostatic discharge portion is made of a conductive material and is located on a side of the encapsulation layer facing away from the substrate. The non-display area includes a blocking portion, the blocking portion is arranged around the display area, and is located between the substrate and the encapsulation layer. The electrostatic discharge portion is located on a side of the touch wire facing away from the display area.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: April 9, 2024
    Assignee: WUHAN TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Chujie Yu, Jiazhu Zhu, Shanfu Yuan, Tao Peng, Ruiyuan Zhou
  • Patent number: 11942556
    Abstract: A device includes a first channel layer, a second channel layer, a gate structure, a source/drain epitaxial structure, and a source/drain contact. The first channel layer and the second channel layer are arranged above the first channel layer in a spaced apart manner over a substrate. The gate structure surrounds the first and second channel layers. The source/drain epitaxial structure is connected to the first and second channel layers. The source/drain contact is connected to the source/drain epitaxial structure. The second channel layer is closer to the source/drain contact than the first channel layer is to the source/drain contact, and the first channel layer is thicker than the second channel layer.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Ru Lin, Shu-Han Chen, Yi-Shao Li, Chun-Heng Chen, Chi On Chui
  • Patent number: 11942499
    Abstract: An image sensor includes a pixel array and a logic circuit. The pixel array includes a pixel isolation layer between a plurality of pixels. Each of the plurality of pixels include a pixel circuit below at least one photodiode. The logic circuit acquires a pixel signal from the plurality of pixels. The pixel array includes at least one autofocusing pixel, which includes a first photodiode, a second photodiode, a pixel internal isolation layer between the first and second photodiodes, and a microlens on the first and second photodiodes. The pixel internal isolation layer includes a first pixel internal isolation layer and a second pixel internal isolation layer, separated from each other in a first direction, perpendicular to the upper surface of the substrate, and the first pixel internal isolation layer and the second pixel internal isolation layer include different materials.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: March 26, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Masato Fujita, Doosik Seol, Kyungduck Lee, Kyungho Lee, Taesub Jung
  • Patent number: 11935938
    Abstract: Devices, such as transistors, that use bismuth to create ohmic contacts are provided, as are methods of manufacturing the same. The transistors, such as field-effect transistors, can include one or more two-dimensional materials, and electrical contact areas can be created on the two-dimensional material(s) using bismuth. The bismuth can help to provide energy-barrier free, ohmic contacts, and the resulting devices can have performance levels that rival or exceed state-of-the-art devices that utilize three-dimensional materials, like silicon. The two-dimensional materials can include transition metal dichalcogenides, such as molybdenum disulfide.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: March 19, 2024
    Assignee: Massachusetts Institute of Technology
    Inventors: Pin-Chun Shen, Jing Kong
  • Patent number: 11935948
    Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A third III-V compound layer is disposed on the second III-V compound layer. The first III-V compound layer and the third III-V compound layer are composed of the same group III-V elements. The third III-V compound layer includes a body and numerous finger parts. Each of the finger parts is connected to the body. All finger parts are parallel to each other and do not contact each other. A source electrode, a drain electrode and a gate electrode are disposed on the first III-V compound layer.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: March 19, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Po-Yu Yang
  • Patent number: 11929408
    Abstract: Various embodiments are disclosed for improved and structurally optimized transistors, such as RF power amplifier transistors. A transistor may include a drain metal portion raised from a surface of a substrate, a drain metal having a notched region, a gate manifold body with angled gate tabs extending from the gate manifold, and/or a source-connected shielding. The transistor may include a high-electron-mobility transistor (HEMT), a gallium nitride (GaN)-on-silicon transistor, a GaN-on-silicon-carbide transistor, or other type of transistor.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: March 12, 2024
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Shamit Som, Wayne Mack Struble, Jason Matthew Barrett, Nishant R Yamujala, John Stephen Atherton