Patents Examined by Eric A. Ward
  • Patent number: 10804278
    Abstract: A method for integrating vertical transistors and electric fuses includes forming fins through a dielectric layer and a dummy gate stack on a substrate; thinning top portions of the fins by an etch process; epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region; and removing the dummy gate layer and exposing sidewalls of the fins. The fuse region is blocked to form a gate structure in the transistor region. The transistor region is blocked and the fuse region is exposed to conformally deposit a metal on exposed sidewalls of the fins. The metal is annealed to form silicided fins. Portions of the substrate are separated to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: October 13, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Karthik Balakrishnan, Michael A. Guillorn, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10804437
    Abstract: A light emitting diode chip including a light emitting structure having an active layer, and a distributed Bragg reflector (DBR) disposed to reflect light emitted therefrom. The DBR has first and second regions, and a third region therebetween. The first region is closer to the light emitting structure than the second and third regions. The DBR includes first material layers having a high index of refraction and second material layers having a low index of refraction alternately disposed one over another. The first material layers include first, second, and third groups having an optical thickness greater than 0.25?+10%, in a range of 0.25??10% to 0.25?+10%, and less than 0.25??10%, respectively. With respect to a central wavelength (?: 554 nm) of the visible range, the first region has the first and second groups, the second region has the third group, and the third region has the second and third groups.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: October 13, 2020
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Ye Seul Kim, Sang Won Woo, Kyoung Wan Kim
  • Patent number: 10804137
    Abstract: An SOI substrate manufacturing method and an SOI substrate are provided, where the method includes: forming a patterned etch-stop layer in an oxide layer of a first silicon substrate, bonding a surface, having the patterned etch-stop layer (130), of the first silicon substrate with a surface of a second silicon substrate, and peeling off a part of the first silicon substrate to form a patterned SOI substrate.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: October 13, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Yourui HuangFu
  • Patent number: 10804157
    Abstract: A semiconductor apparatus and its manufacturing method are presented. The method entails providing a substrate structure comprising a substrate, one or more fins positioned along a first direction on the substrate, and a separation region surrounding the fins. The separation region comprises a first separation region neighboring a first side of the fins and a second separation region neighboring a second side of the fins; forming a first and a second insulation layers on the substrate structure; forming a barrier layer; performing a first etching process using the barrier layer as a mask; removing the barrier layer; performing a second etching process using the remaining second insulation layer as a mask; forming a third insulation layer on side surfaces of the remaining first and second insulation layers; and performing a third etching process using the remaining second insulation layer and the third insulation layer as a mask.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: October 13, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Hai Zhao
  • Patent number: 10796991
    Abstract: A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: October 6, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jang-Gn Yun, Jaesun Yun, Joon-Sung Lim
  • Patent number: 10797137
    Abstract: A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 6, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Hung-Hsiang Cheng, Samuel C. Pan
  • Patent number: 10797199
    Abstract: An apparatus and method capable of efficiently manufacturing a LED module. The method of manufacturing an Light Emitting Diode (LED) module includes preparing a substrate and a carrier on which an LED chip is disposed, disposing a mask on the substrate, the mask including an opening and a wall defining or forming the opening, picking up the LED chip from the carrier with a stamp, moving the LED chip picked up by the stamp to face the opening, moving the LED chip so that at least a part of the LED chip is inserted into the opening, and positioning the LED chip on the substrate by moving the LED chip so that the at least a part of the LED chip contacts the wall.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: October 6, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Hoon Yoon, Kyung Hoon Cha
  • Patent number: 10784180
    Abstract: An electronics device with at least one component to be cooled, a cooling element for cooling the component to be cooled, at least one power supply line, and a respective current sensor for recording a current strength of a current flowing through the respective power supply line, wherein the cooling element has a recess, in which the current sensor engages or in which the current sensor is arranged.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 22, 2020
    Assignee: AUDI AG
    Inventors: Andreas Apelsmeier, Benjamin Söhnle, Stephan Brüske
  • Patent number: 10777651
    Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yushi Hu, John Mark Meldrim, Eric Blomiley, Everett Allen McTeer, Matthew J. King
  • Patent number: 10777668
    Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer is arranged over the active region, and a semiconductor layer is arranged on the base layer. The semiconductor layer includes a stepped profile with a first section having a first width adjacent to the base layer and a second section having a second width that is less than the first width. An emitter is arranged on the second section of the semiconductor layer.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Vibhor Jain, John J. Pekarik, Qizhi Liu, Pernell Dongmo
  • Patent number: 10770667
    Abstract: A flexible display device is provided, including: a display area, a bending area, and a driving printed circuit board. The bending area is located between the display area and the driving printed circuit board, and the driving printed circuit board is located on a rear side of the display area by bending of the bending area. The bending area includes: a substrate; an inorganic layer disposed on the substrate, where the inorganic layer is disposed on the substrate and distributed in a form of islands, and the inorganic layer includes a plurality of island-shaped blocks, and two adjacent island-shaped blocks are spaced apart from each other; and a first metal layer disposed on a whole surface of the inorganic layer and the substrate, where the first metal layer forms a plurality of first recesses corresponding to shapes of the plurality of island-shaped blocks.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: September 8, 2020
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Shasha Li, Shoucheng Wang
  • Patent number: 10770578
    Abstract: A semiconductor device includes an electrical device and has an output capacitance characteristic with at least one output capacitance maximum located at a voltage larger than 5% of a breakdown voltage of the semiconductor device. The output capacitance maximum is larger than 1.2 times an output capacitance at an output capacitance minimum located at a voltage between the voltage at the output capacitance maximum and 5% of a breakdown voltage of the semiconductor device.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: September 8, 2020
    Assignee: Infineon Technologies Austria AG
    Inventor: Franz Hirler
  • Patent number: 10763270
    Abstract: A method for forming an integrated circuit (IC) and an IC are disclosed. The method for forming the IC includes: forming an isolation structure separating a memory semiconductor region from a logic semiconductor region; forming a memory cell structure on the memory semiconductor region; forming a memory capping layer covering the memory cell structure and the logic semiconductor region; performing a first etch into the memory capping layer to remove the memory capping layer from the logic semiconductor region, and to define a slanted, logic-facing sidewall on the isolation structure; forming a logic device structure on the logic semiconductor region; and performing a second etch into the memory capping layer to remove the memory capping layer from the memory semiconductor, while leaving a dummy segment of the memory capping layer that defines the logic-facing sidewall.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Yu Chen, Kuo-Chi Tu, Wen-Ting Chu, Yong-Shiuan Tsair
  • Patent number: 10763178
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack has a first upper portion and a first lower portion, and the first upper portion is wider than the first lower portion. The semiconductor device structure includes a spacer layer surrounding the gate stack. The spacer layer has a second upper portion and a second lower portion. The second upper portion is thinner than the second lower portion.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Heng Tsai, Chun-Sheng Liang, Pei-Lin Wu, Yi-Ren Chen, Shih-Hsun Chang
  • Patent number: 10763272
    Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Wataru Sakamoto, Ryota Suzuki, Tatsuya Okamoto, Tatsuya Kato, Fumitaka Arai
  • Patent number: 10756297
    Abstract: A flexible panel is provided. The flexible panel includes a substrate, an organic light-emitting diode device, a thin-film encapsulation layer and a retaining wall. Wherein the organic light-emitting diode device is formed on the substrate, the thin-film encapsulation layer is formed on the substrate and covers the organic light-emitting diode device, the retaining wall is disposed on the substrate and is around an outside of the organic light-emitting diode device. Wherein the first portion is closer to a light-emitting region of the flexible panel than the second portion. A manufacturing method for the flexible panel and a display device using the flexible panel are also disclosed.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: August 25, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Jing Huang, Hsiang Lun Hsu
  • Patent number: 10756222
    Abstract: A photo-sensitive device includes a uniform layer, a gradated buffer layer over the uniform layer, a silicon layer over the gradated buffer layer, a photo-sensitive light-sensing region in the uniform layer and the silicon layer, a device layer on the silicon layer, and a carrier wafer bonded to the device layer.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Hung Cheng, Chia-Shiung Tsai, Cheng-Ta Wu, Xiaomeng Chen, Yen-Chang Chu, Yeur-Luen Tu
  • Patent number: 10748911
    Abstract: An integrated circuit structure includes a semiconductor substrate, an active area, a gate electrode, and a butted contact. The active area is oriented in a first direction and has at least one tooth portion extending in a second direction in the semiconductor substrate. The gate electrode overlies the active area and extends in the second direction. The butted contact has a first portion above the gate electrode and a second portion above the active area. A portion of the second portion of the butted contact lands on the tooth portion.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gulbagh Singh, Shun-Chi Tsai, Chih-Ming Lee, Chi-Yen Lin, Kuo-Hung Lo
  • Patent number: 10741643
    Abstract: A semiconductor device includes: a substrate; a first source/drain region and a second source/drain region spaced apart from each other by a trench in the substrate; and a gate structure in the trench, wherein the gate structure includes: a gate dielectric layer formed on a bottom and sidewalls of the trench; a first gate electrode positioned in a bottom portion of the trench over the gate dielectric layer; a second gate electrode positioned over the first gate electrode; and a dipole inducing layer formed between the first gate electrode and the second gate electrode and between sidewalls of the second gate electrode and the gate dielectric layer.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: August 11, 2020
    Assignee: SK hynix Inc.
    Inventor: Seong-Wan Ryu
  • Patent number: 10741392
    Abstract: A method includes forming a metal layer over a substrate; forming a dielectric layer over the metal layer; removing a first portion of the dielectric layer to expose a first portion of the metal layer, while a second portion of the dielectric layer remains on the metal layer; selectively forming a first inhibitor on the second portion of the dielectric layer, while the metal layer is free of coverage by the first inhibitor; and selectively depositing a first hard mask on the exposed first portion of the metal layer, while the first inhibitor is free of coverage by the first hard mask.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wei Su, Fu-Ting Yen, Teng-Chun Tsai