Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

Abstract: An SRAM structure includes first and second gate strips extending along a first direction. A first active region extends across the first gate strip from a top view, and forms a first pull-up transistor with the first gate strip. A second active region extends across the second gate strip from the top view, and forms a second pull-up transistor with the second gate strip. From the top view the first active region has a first stepped sidewall facing away from the second active region. The first stepped sidewall has a first side surface farthest from the second active region, a second side surface set back from the first side surface along the first direction, and a third side surface set back from the second side surface along the first direction.

Abstract: A field effect transistor for a high voltage operation can include vertical current paths, which may include vertical surface regions of a pedestal semiconductor portion that protrudes above a base semiconductor portion. The pedestal semiconductor portion can be formed by etching a semiconductor material layer employing a gate structure as an etch mask. A dielectric gate spacer can be formed on sidewalls of the pedestal semiconductor portion. A source region and a drain region may be formed underneath top surfaces of the base semiconductor portion. Alternatively, epitaxial semiconductor material portions can be grown on the top surfaces of the base semiconductor portions, and a source region and a drain region can be formed therein. Alternatively, a source region and a drain region can be formed within via cavities in a planarization dielectric layer.

Abstract: A 3D integrated circuit (3D IC) chip is described. The 3D IC chip includes a die having a compound semiconductor high electron mobility transistor (HEMT) active device. The compound semiconductor HEMT active device is composed of compound semiconductor layers on a single crystal, compound semiconductor layer. The 3D IC chip also includes an acoustic device integrated in the single crystal, compound semiconductor layer. The 3D IC chip further includes a passive device integrated in back-end-of-line layers of the die on the single crystal, compound semiconductor layer.

Abstract: According to one configuration, a fabricator produces an electronic device to include: a substrate; a transistor circuit disposed on the substrate; silicide material disposed on first regions of the transistor circuit; and the silicide material absent from second regions of the transistor circuit. Absence of the silicide material over the second regions of the respective of the transistor circuit increases a resistance of one or more parasitic paths (such as one or more parasitic transistors) in the transistor circuit. The increased resistance in the one or more parasitic paths provides better protection of the transistor circuit against electro-static discharge conditions.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric layer; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric layer, and the second gate dielectric layer extends over the first gate.

Abstract: Integrated circuit (IC) structures including buried insulator layer and methods for forming are provided. In a non-limiting example, a IC structure includes: a substrate; a first fin over the substrate; a source region and a drain region in the first fin; a first gate structure and a second gate structure over the first fin, the first and the second gate structures positioned between the source region and the drain region; and a buried insulator layer including a portion disposed under the first fin.

Abstract: A semiconductor device of an embodiment includes a first trench extending in a first direction in a silicon carbide layer; a second trench and a third trench adjacent to each other in the first direction; a first silicon carbide region of n type; a second silicon carbide region of p type on the first silicon carbide region; a third silicon carbide region of n type on the second silicon carbide region; a fourth silicon carbide region of p type between the first silicon carbide region and the second trench; a fifth silicon carbide region of p type between the first silicon carbide region and the third trench; a gate electrode in the first trench; a first electrode, part of which is in the second trench, the first electrode contacting the first silicon carbide region between the fourth silicon carbide region and the fifth silicon carbide region; and a second electrode.

Abstract: A semiconductor device of an embodiment includes: a first trench located in a silicon carbide layer extending in a first direction; a second trench and a third trench adjacent to each other in the first direction; n type first silicon carbide region; p type second silicon carbide region on the first silicon carbide region; n type third silicon carbide region on the second silicon carbide region; p type fourth silicon carbide region between the first silicon carbide region and the second trench; p type fifth silicon carbide region between the first silicon carbide region and the third trench; p type sixth silicon carbide region shallower than the second trench between the second trench and the third trench and having a p type impurity concentration higher than that of the second silicon carbide region; a gate electrode in the first trench; a first electrode, and a second electrode.

Abstract: A method includes forming a metal layer over a substrate; forming a dielectric layer over the metal layer; removing a first portion of the dielectric layer to expose a first portion of the metal layer, while a second portion of the dielectric layer remains on the metal layer; selectively forming a first inhibitor on the second portion of the dielectric layer, while the metal layer is free of coverage by the first inhibitor; and selectively depositing a first hard mask on the exposed first portion of the metal layer, while the first inhibitor is free of coverage by the first hard mask.

Abstract: A memory device includes a substrate, first, second, and third conductive layers, a stack of fourth conductive layers, a memory pillar, and an insulator. The first, second, and third conductive layer are provided above the substrate. The stack of fourth conductive layers is provided above the third conductive layer. The memory pillar extends in the thickness direction through the stack and the third conductive layer and into the second conductive layer in a first region of the memory device. The insulator extends in a thickness direction through the stack, the third conductive layer, and the second conductive layer in a second region of the memory device. The insulator also extends in a second surface direction of the substrate. A thickness of the third conductive layer in a region through which the insulator extends is greater than a thickness of the third conductive layer in the first region.

Abstract: A semiconductor structure includes a seed layer on a substrate and an epitaxial stack on the seed layer. The epitaxial stack includes a first superlattice part and a second superlattice part on the first superlattice part. The first superlattice part includes first units repetitively stacked M1 times on the seed layer. Each first unit includes a first sub-layer that is an Aly1Ga1-y1N layer, and a second sub-layer that is an Alx1Ga1-x1N layer, wherein y1<x1. The second superlattice part includes second units repetitively stacked M2 times on the first superlattice part. Each second unit includes a third sub-layer that is an Aly2Ga1-y2N layer, and a fourth sub-layer that is an Alx2Ga1-x2N layer, wherein y2<x2. M1 and M2 are positive integers, 0?x1, y1 and y2<1, 0<x2?1, and x1<x2, or x1=x2 and y1<y2.

Abstract: A semiconductor device includes a substrate, a first well, a second well, a metal gate, a poly gate, a source region, and a drain region. The first well and the second well are within the substrate. The metal gate is partially over the first well. The poly gate is over the second well. The poly gate is separated from the metal gate, and a width ratio of the poly gate to the metal gate is in a range from about 0.1 to about 0.2. The source region and the drain region are respectively within the first well and the second well.

Abstract: An object of the present disclosure is to suppress a shrinkage cavity without affecting the layout or the insulation performance of the semiconductor element in a power semiconductor device. A power semiconductor device includes a heat radiation plate; an insulating substrate bonded in a bonding region on an upper surface of the heat radiation plate with a bonding material containing a plurality of elements having different solidification points; a semiconductor element mounted on an upper surface of the insulating substrate; and a bonding wire bonded in the bonding region on the upper surface of the heat radiation plate such that the bonding wire surrounds the semiconductor element in plan view.

Abstract: Group-III nitride (III-N) tunnel devices with a device structure including multiple quantum wells. A bias voltage applied across first device terminals may align the band structure to permit carrier tunneling between a first carrier gas residing in a first of the wells to a second carrier gas residing in a second of the wells. A III-N tunnel device may be operable as a diode, or further include a gate electrode. The III-N tunnel device may display a non-linear current-voltage response with negative differential resistance, and be employed as a frequency mixer operable in the GHz and THz bands. In some examples, a GHz-THz input RF signal and local oscillator signal are coupled into a gate electrode of a III-N tunnel device biased within a non-linear regime to generate an output RF signal indicative of a frequency difference between the RF signal and a local oscillator signal.

Abstract: A semiconductor device structure includes a region of semiconductor material having an active region and a termination region. An active structure is disposed in the active region and a termination structure is disposed in the termination region. In one embodiment, the termination structure includes a termination trench and a conductive structure within the termination trench and electrically isolated from the region of semiconductor material by a dielectric structure. A dielectric layer is disposed to overlap the termination trench to provide the termination structure as a floating structure. A Schottky contact region is disposed within the active region. A conductive layer is electrically connected to the Schottky contact region and the first conductive layer extends onto a surface of the dielectric layer and laterally overlaps at least a portion of the termination trench.

Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.

Abstract: In a step of calculating formation conditions for the second silicon carbide layer, a formation time of the second silicon carbide layer is calculated as a value obtained by multiplying a value obtained by dividing the second thickness by the first thickness, by the first formation time, and a flow rate of a second ammonia gas in a step of forming the second silicon carbide layer by epitaxial growth is calculated as a value obtained by multiplying a value obtained by dividing the second concentration by the first concentration, by the first flow rate.

Abstract: A phase-change memory cell includes, in at least a first portion, a stack of at least one germanium layer covered by at least one layer made of a first alloy of germanium, antimony, and tellurium In a programmed state, resulting from heating a portion of the stack to a sufficient temperature, portions of layers of germanium and of the first alloy form a second alloy made up of germanium, antimony, and tellurium, where the second alloy has a higher germanium concentration than the first alloy.

Abstract: A semiconductor wafer includes a silicon carbide wafer and an epitaxial layer, which is disposed at a surface of the silicon carbide wafer and made of silicon carbide. The semiconductor wafer satisfies a condition that a waviness value is equal to or smaller than 1 micrometer. The waviness value is a sum of an absolute value of a value ? and an absolute value of a value ?. A highest height among respective heights of a plurality of points with reference to a surface reference plane within a light exposure area is denoted as the value ?. A lowest height among the respective heights of the points at the epitaxial layer with reference to the surface reference plane within the light exposure area is denoted as the value ?.