Patents Examined by Eric Ashbahian
  • Patent number: 10199481
    Abstract: A method for manufacturing a semiconductor device includes carrying out a first heat treatment accompanied by nitration on a first insulating film and a silicon carbide substrate in a first gas atmosphere, after the carrying out of the first heat treatment and after a temperature of the silicon carbide substrate has become 700° C. or less, removing the silicon carbide substrate from a processing apparatus and exposing the silicon carbide substrate to air in an atmosphere outside of the processing apparatus, and after the exposing of the silicon carbide substrate to air in the atmosphere, carrying out a second heat treatment on the first insulating film and the silicon carbide substrate in a second gas atmosphere which is an inert gas.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: February 5, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masaki Hama, Yasuaki Kagotoshi
  • Patent number: 10199458
    Abstract: Provided is a semiconductor device having a superjunction structure formed by a first conduction type column and a second conduction type column, including a first region of the superjunction structure in which a PN ratio increases in a direction from a first surface side to a second surface side of the superjunction structure; and a second region of the superjunction structure that contacts the first region and is adjacent to a channel region of the semiconductor device, wherein a PN ratio of the second region is less than the PN ratio at an end of the first region on the second surface side and thickness of the second region is less than thickness of the first region.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: February 5, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Toshiaki Sakata, Mutsumi Kitamura
  • Patent number: 10199523
    Abstract: A surface region of a semiconductor material on a surface of a semiconductor device is doped during its manufacture, by coating the surface region of the semiconductor material with a dielectric material surface layer and locally heating the surface of the semiconductor material in an area to be doped to locally melt the semiconductor material with the melting being performed in the presence of a dopant source. The heating is performed in a controlled manner such that a region of the surface of the semiconductor material in the area to be doped is maintained in a molten state without refreezing for a period of time greater than one microsecond and the dopant from the dopant source is absorbed into the molten semiconductor. The semiconductor device includes a semiconductor material structure in which a junction is formed and may incorporate a multi-layer anti-reflection coating.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: February 5, 2019
    Assignees: NEWSOUTH INNOVATIONS PTY LIMITED, SUNTECH POWER INTERNATIONAL LTD.
    Inventors: Alison Maree Wenham, Ziv Hameiri, Jing Jia Ji, Ly Mai, Zhengrong Shi, Budi Tjahjono, Stuart Ross Wenham
  • Patent number: 10177223
    Abstract: A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Darsen D. Lu, Xin Miao, Tenko Yamashita
  • Patent number: 10163784
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. In the semiconductor device, an upper part of a storage node contact plug is increased in size, and an area of overlap between a storage node formed in a subsequent process and a storage node contact plug is increased, such that resistance of the storage node contact plug is increased and device characteristics are improved. The semiconductor device includes at least one bit line formed over a semiconductor substrate, a first storage node contact plug formed between the bit lines and coupled to an upper part of the semiconductor substrate, and a second storage node contact plug formed over the first storage node contact plug, wherein a width of a lower part of the second storage node contact plug is larger than a width of an upper part thereof.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: December 25, 2018
    Assignee: SK HYNIX INC.
    Inventor: Dae Sik Park
  • Patent number: 10134658
    Abstract: High power transistors, such as high power gallium nitride (GaN) transistors, are described. These high power transistors have larger total gate widths than conventional high power transistors by arranging multiple linear arrays of gate, drain, and source contacts in parallel. Thereby, the total gate width and the power rating of the high power transistor may be increased without elongating the die of the high power transistor. Accordingly, the die of the high power transistor may be mounted in a smaller circuit package relative to conventional dies with the same power rating.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: November 20, 2018
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Aram Mkhitarian, Vincent Ngo
  • Patent number: 10134845
    Abstract: A power semiconductor device includes a semiconductor body having first and second opposing sides and an edge termination region arranged between an active region and an outer rim. The semiconductor body further includes a first doping region in the active region and connected to a first electrode arranged on the first side of the semiconductor body, a second doping region in the active region and the edge termination region and connected to a second electrode arranged on the second side of the semiconductor body, a drift region between the first doping region and the second doping region, the drift region comprising a first portion adjacent to the first side of the semiconductor body and a second portion arranged between the first portion and the second doping region, and an insulating region arranged in the edge termination region between the second doping region and the first portion of the drift region.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: November 20, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Franz Hirler, Anton Mauder
  • Patent number: 10126145
    Abstract: An analog signal is supplied to a first conversion section of a physical quantity sensor device, converted to digital, and set to be an initial output value of the first conversion section. Adjustment information for the first conversion section is calculated based on the error between the initial output value and a target output value of the first conversion section. Before an initial output value of a physical quantity sensor is measured for calculating initial setting information of a physical quantity sensor device, the first conversion section is adjusted based on the adjustment information. Also, a digital signal is supplied to a second conversion section of the physical quantity sensor device, converted to analog, and set to be an initial output value of the second conversion section. The second conversion section is adjusted based on adjustment information for the second conversion section.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: November 13, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Mutsuo Nishikawa, Katsuyuki Uematsu, Kazuhiro Matsunami
  • Patent number: 10126203
    Abstract: Method for detecting an air filter condition, in particular for combustion engines, comprising the following steps: calculation of a linear regression over data-couples values, each comprising pressure drop value at the air filter and square of air flow value crossing the air filter, corresponding to said pressure drop value, in order to obtain an angular coefficient of the linear regression, comparison of the angular coefficient or of the function construed on the angular coefficient with at least one threshold in order to detect an operative condition of the air filter (FIG. 1).
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: November 13, 2018
    Assignee: FPT MOTORENFORSCHUNG AG
    Inventor: Thomas Eckhardt
  • Patent number: 10121951
    Abstract: In a light-emitting device substrate (2), a light reflecting surface covered with an anodized aluminum layer (12) is formed on one side of a base (14), and a glass-based insulator layer (11) and electrode patterns (5?6) disposed on the first insulating layer (11) are formed on the one side of the base (14) in a region not covered with the anodized aluminum layer (12). A glass-based insulator layer (13) is formed at least on the other side of the base (14) that is opposite the one side of the base (14). Therefore, a light-emitting device substrate having high reflectivity, high heat dissipation capability, dielectric withstand capability, and long-term reliability and excellent in mass productivity can be realized.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: November 6, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shin Itoh, Masahiro Konishi
  • Patent number: 10115638
    Abstract: An integrated circuit containing MOS transistors with replacement gates may be formed with elevated LDD regions and/or recessed replacement gates on a portion of the transistors. Elevating the LDD regions is accomplished by a selective epitaxial process prior to LDD implant. Recessing the replacement gates is accomplished by etching substrate material after removal of sacrificial gate material and before formation of a replacement gate dielectric layer. Elevating the LDD regions and recessing the replacement gates may increase a channel length of the MOS transistors and thereby desirably increase threshold uniformity of the transistors.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: October 30, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Mahalingam Nandakumar
  • Patent number: 10107737
    Abstract: An apparatus and a method for evaluating film adhesion are disclosed. The film is disposed on a first substrate, a side of the first substrate provided with the film is attached to a second substrate, and the film is divided into units. The apparatus includes an evaluation machine, which includes an upper fixing mechanism and a lower fixing mechanism disposed opposite to each other, the second substrate is detachably fixed on the upper fixing mechanism, and a side of the first substrate not provided with the film is detachably fixed on the lower fixing mechanism. The evaluation machine further includes a force application device, which is configured to apply an external force to the upper fixing mechanism and/or the lower fixing mechanism, so that the upper fixing mechanism and the lower fixing mechanism generate relative movement away from each other.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 23, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Min Yuan, Hongwei Xing, Guilin Liu
  • Patent number: 10109756
    Abstract: A photo-sensitive device includes a uniform layer, a gradated buffer layer over the uniform layer, a silicon layer over the gradated buffer layer, a photo-sensitive light-sensing region in the uniform layer and the silicon layer, a device layer on the silicon layer, and a carrier wafer bonded to the device layer.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: October 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Hung Cheng, Chia-Shiung Tsai, Cheng-Ta Wu, Xiaomeng Chen, Yen-Chang Chu, Yeur-Luen Tu
  • Patent number: 10096788
    Abstract: A transistor device comprising: source and drain conductors connected by a semiconductor channel; and a gate conductor capacitively coupled to the semiconductor channel via a gate dielectric; wherein the gate conductor comprises at least one portion overlapping at least part of at least one of said source and drain conductors; and further comprising a patterned insulator interposed between at least part of said at least one of the source and drain conductors and said at least one overlapping portion of said gate conductor so as to reduce capacitive coupling between the said at least one of the source and drain conductors and the gate conductor by more than any reduction in capacitive coupling between the semiconductor channel and the gate conductor.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: October 9, 2018
    Assignee: FLEXENABLE LIMITED
    Inventor: Jan Jongman
  • Patent number: 10096767
    Abstract: A Magnetoresistive Tunnel Junction (MTJ) device includes an elongated MTJ structure formed onto a substrate, the MTJ structure including a magnetic reference layer and a tunnel barrier layer. The MTJ device also includes a number of discrete free magnetic regions disposed onto the tunnel barrier layer. The ratio of length to width of the elongated MTJ structure is such that the magnetic field of the magnetic reference layer is pinned in a single direction.
    Type: Grant
    Filed: March 9, 2013
    Date of Patent: October 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chwen Yu, Kai-Wen Cheng, Tien-Wei Chiang, Dong Cheng Chen
  • Patent number: 10062749
    Abstract: Metal-oxide-semiconductor field-effect transistor (MOSFET) devices are described which have a p-type region between the p-type well regions of the device. The p-type region can be either floating or connected to the p-type well regions by additional p-type regions. MOSFET devices are also described which have one or more p-type regions connecting the p-type well regions of the device. The p-type well regions can be arranged in a various geometric arrangements including square, diamond and hexagonal. Methods of making the devices are also described.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: August 28, 2018
    Assignee: Monolith Semiconductor Inc.
    Inventors: Kiran Chatty, Kevin Matocha, Sujit Banerjee, Larry Burton Rowland
  • Patent number: 10062706
    Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: August 28, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yosuke Takeuchi, Eiji Tsukuda, Kenichiro Sonoda, Shibun Tsuda
  • Patent number: 10008630
    Abstract: An inorganic insulating film containing nitrogen, which has high adhesion to a sealant and an excellent effect of blocking hydrogen, water, and the like, is used as a layer in contact with the sealant. Further, the sealant is provided on the outer side than a side surface of an end portion of the organic insulating film provided over the transistor or the inorganic insulating film containing nitrogen is provided to cover an area from a region which is on the outer side than the edge of the organic insulating film to the side surface and the top surface of the end portion of the organic insulating film. Accordingly, the entry of hydrogen, water, and the like existing outside the display device into the oxide semiconductor included in the transistor can be suppressed, so that the display device can have high reliability.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: June 26, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshiharu Hirakata
  • Patent number: 9997623
    Abstract: A switch includes three components. Each component includes a stack of three semiconductor regions of alternating conductivity types and a control region in a first of the three semiconductor regions having a type opposite to that of the first semiconductor region. The first semiconductor regions of the first and second components are of a same conductivity type and the first semiconductor regions of the first and third components are of opposite conductivity types. The first semiconductor region of the first component is connected to the control regions of the second and third components. The first semiconductor regions of the second and third components are connected to a first switch terminal, the third semiconductor regions of the first, second, and third components are connected to a second switch terminal, and the control region of the first component is connected to a third switch terminal.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: June 12, 2018
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Yannick Hague
  • Patent number: 9991225
    Abstract: A high-voltage transistor (HVT) structure adapts a low-voltage transistor (LVT) to high-voltage environments. The HVT structure includes a drain node, a source node, a control gate, and a field electrode. The drain node and the source node define a conductive channel, in which mobilized charges are regulated by the control gate. While being isolated from the control gate, the field electrode is configured to spread the mobilized charges in response to a field voltage. The field electrode is structured and routed to prevent charge sharing with any one of the drain node, source node, or control gate. Advantageously, the isolated field electrode minimizes the capacitance of the control gate as well as the drain and source nodes, such that the HVT can switch with less power loss and a more robust performance in a high-voltage environment.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: June 5, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sandeep R. Bahl, Michael D. Seeman