Abstract: A method for data transmission is provided. The method includes, at an initiator computing device, receiving a data payload to be transmitted to a target computing device for storage using the nonvolatile memory express over fabric (NVMe-oF) protocol, wherein the data payload is represented as a plurality of logical blocks. Using a compression engine, the data payload is compressed into a plurality of physical blocks having a smaller total data size than the plurality of logical blocks. A write request is transmitted to the target computing device, the write request including the plurality of physical blocks, and metadata specifying a correspondence between each logical block of the plurality of logical blocks and one or more corresponding physical blocks of the plurality of physical blocks.

Abstract: A method includes writing, to a first data structure, indices corresponding to address locations of a logical-to-physical (L2P) data structure that maps a plurality of logical block addresses (LBAs) associated with the L2P data structure, initiating performance of a media management operation involving one or more memory blocks in which data associated with the LBAs is written, and refraining from rewriting particular entries in the L2P table that correspond to LBAs whose index in the first data structure is a particular value during performance of the media management operation.

Abstract: Methods, systems, and devices for an interface layout for stacked memory architectures are described. A memory interface block may interface a plurality of memory dies to a host controller. The memory interface block may include an interface block coupled with multiple memory dies, which may be stacked on the memory interface block using through-silicon-vias. The memory interface block may include controllers, datapath blocks, and interface blocks associated with each memory die. As such, the memory interface block may perform functions such as queueing, ECC, and performing row repair and column repair procedures. In some examples, a layout for the memory interface block may include pairing controllers for at least two memory devices, such that a pair of controllers may share a command port to a pair of memory dies. Further, the memory interface block may include interfaces to the host controller that are different from the interface to each memory die.

Abstract: A processing device, operatively coupled with a memory device, performs a first programming operation on a first set of cells associated with a first sub-block of a first die of the memory device, wherein each die of the memory device comprises a plurality of sub-blocks. The processing device identifies, based on a first predefined value, a second sub-block of a second die of the memory device on which to perform a second programming operation, wherein the first predefined value is a shift in an index value of the first sub-block of the first die of the memory device. The processing device further performs the second programming operation on a second set of cells associated with the second sub-block of the second die, wherein the second sub-block of the second die is associated with a different index value than the first sub-block of the first die.

Abstract: A technique manages solid state device (SSD) wear-level. The technique involves storing data on a plurality of SSDs. The technique further involves, based on storing the data on the plurality of SSDs, identifying a particular SSD of the plurality of SSDs as a target SSD. The technique further involves moving write-hot data to the particular SSD identified as the target SSD to increase writing workload on the particular SSD compared to respective writing workloads on other SSDs of the plurality of SSDs. Accordingly, the particular SSD wears out ahead of the other SSDs and avoids multiple SSD failures at the same time which otherwise could result in data unavailability (DU) and/or data loss (DL).

Abstract: Examples of the present disclosure disclose host and an operation method thereof, a memory system and an operation method thereof, and an electronic apparatus. The host is coupled with a memory system supporting a zone namespace function; the memory system includes a memory device, and the memory device includes K dies; the K dies are divided into N disturbance areas, each disturbance area includes at least one die, and one block in each die in the disturbance area constitutes a zone jointly; K and N are positive integers greater than or equal to 2; the host is configured to: send a command to the memory system to perform a respective operation on zones corresponding to the command at the same time, wherein the zones corresponding to the command belong to different disturbance areas.

Abstract: Provided are a computer program product, system, and method for coordinating establishment of source and target copy relationships on primary and secondary servers. A command is received to establish a primary copy relationship of primary source data in the primary storage to copy to primary target data in the primary storage and a secondary copy relationship of secondary source data in the secondary storage to copy to secondary target data in the secondary storage. A determination is made as to whether a part of the secondary target data in a secondary pre-existing copy relationship at the secondary storage can be withdrawn from the secondary pre-existing copy relationship. In response to determining that the part of the secondary target data in the secondary pre-existing copy relationship can be withdrawn, establishing the primary copy relationship for the primary storage and establishing the secondary copy relationship for the secondary storage.

Abstract: Methods, systems, and devices for folding operations for improved sequential read performance are described. A memory system may perform a single-die access operation to program data to source data blocks of the memory system. The memory system may reorder the data during folding to destination data blocks of the memory system such that a multi-die access operation may be performed to sequentially read the data from the destination data blocks. For example, data may be programmed to the source data blocks in a first order as part of a single-die access operation, and the data may be folded to the destination data blocks in a second order as part of a single-die access operation, where the supports sequentially reading the data from the destination data blocks as part of a multi-die access operation.

Abstract: A memory module may include a first storage device, and a second storage device configured to receive information about a first temperature indicating an internal temperature of the first storage device and to change a threshold temperature from a first threshold temperature to a second threshold temperature different from the first threshold temperature based on the information, to enter a mode in which an internal temperature of the second storage device is controlled when the temperature of the second storage device is higher than the threshold temperature.

Abstract: The present disclosure provides a storage management system, method, device, and machine-readable storage medium, the system including: a controller pool, to interact to-be-stored data and/or to-be-read data with an external device via network communication; a memory pool, to read and write high-speed temporary data and/or high-speed persistent data; an accelerator pool, to call a corresponding accelerator to process and distribute data according to a storage service type associated with data; a storage pool, to store to-be-stored data processed by the accelerator pool and/or read the to-be-read data; and a transmission module, to establish a system transmission network among the controller pool, the memory pool, the accelerator pool and the storage pool.

Abstract: The invention introduces a method for controlling executions of input-output (I/O) commands, performed by a processing unit, which includes: obtaining a current temperature of a device side; fetching I/O commands from a command queue during a fetching time period, and executing the I/O commands to read user data from the flash module, and/or program user data into the flash module in response to the current temperature of the device side exceeding a threshold; calculating a length of an actual execution time period for the I/O commands, and calculating a length of a pause time period according to the length of the actual execution time period after the I/O commands are executed completely; and not fetching and executing any I/O command in the command queue during the pause time period.

Abstract: An example method for provisioning data volume for a virtual compute instance may include receiving a request to provision a data volume for a virtual compute instance. The request may specify a size of the data volume, a type of the data volume, and a first input/output operations per second (IOPS) value for the data volume. Further, the method may include determining a recommended IOPS value for the data volume by applying a logic to the specified size, the specified type, and the first IOPS value. Furthermore, the method may include provisioning the data volume for the virtual compute instance with the specified size, the specified type, and the recommended IOPS value.

Abstract: In a vehicle-mounted computer that includes a physical resource including a processor with a plurality of cores and a physical device with a register and generates a plurality of virtual devices by allocating the physical resource through time-division, the processor causes at least one virtual device of the plurality of virtual devices to operate on each of the plurality of cores periodically at a predetermined period and causes another virtual device of the plurality of virtual devices to operate non-periodically, stores the core on which the other virtual device operated, and determines the core on which the other virtual device is to operate, based on whether or not the core on which the other virtual device is to operate will be changed and a change amount of a register value of the physical device.

Abstract: A host command to deallocate a memory device is received. A logical-to-physical (L2P) status data structure associated with a logical-to-physical (L2P) data structure is invalidated. The L2P mapping data structure includes a plurality of regions. Each region comprises a set of L2P address mappings and a region identifier identifying a respective region. The L2P status data structure includes a plurality of L2P status entries. An L2P status entry comprises a region identifier identifying a region of the plurality of regions of the L2P mapping data structure and a physical address identifying a location of the region of the L2P mapping data structure stored on the memory device. A host is notified that deallocation of the memory device is completed. Invalidation of the L2P mapping data structure is initiated.

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The memory management method includes: writing first data into N super physical programming units of a first super physical erasing unit in a plurality of super physical erasing units; generating N first temporary parity codes according to the first data and storing the N first temporary parity codes in a buffer memory; writing second data into M super physical programming units of a second super physical erasing unit in the plurality of super physical erasing units; performing an encoding operation on the second data and the N first temporary parity codes to generate N first parity codes; and writing the N first parity codes into the second super physical erasing unit.

Abstract: The present disclosure relates to method for checking the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprises: storing in a dummy row associated to said memory block at least internal block variables and a known pattern; performing a reading of said dummy row; comparing a result of the reading with the known pattern; trimming the parameters of the reading and/or swapping the used memory block based on the result of the comparing.

Abstract: The memory device is configured to program and erase data in a memory block according to both an SLC storage scheme and a multiple bits per memory cell (e.g., TLC) storage scheme. In operation, control circuitry receives a command to write data to the memory cells of the memory block in the TLC storage scheme and determine if already data stored in the memory block is in the SLC storage scheme or is in the TLC cell storage scheme. In response to a determination that the data contained in the memory block is in the SLC storage scheme, the control circuitry pre-programs the memory cells of the memory block and then erases the memory cells. In response to a determination that the data contained in the memory block is in the TLC storage scheme, then the control circuitry erases the memory cells without pre-programming.

Abstract: Gap processing is utilized to reorder out-of-order submissions on the normal submission queue. The controller is able to process logical block addresses (LBAs) that are received through the use of a normal NVMe submission queue (SQ) and a private SQ. The normal NVMe SQ will store the LBAs of commands that may arrive out of sequential order for processing. The private SQ is used to store an LBA that is received after a gap is detected. The private SQ is only read after a command is received on the normal SQ that contains the current First Gap LBA. If no entry in the private SQ is sequentially after the first gap LBA, no processing of the private SQ occurs. If the pulled LBA is next, then the LBA will be processed by the data storage device. If the pulled LBA is not next, then the zone gap processing will send the LBA back to the private SQ.

Abstract: Systems and methods for collecting trace data via a memory device are disclosed. One method may include receiving, by the memory device, a command from a computing device; identifying, by the memory device, first data associated with the command; storing, by the memory device, the first data in a first portion of volatile memory of the memory device for reading by the computing device; and accessing, by the memory device, a second portion of the volatile memory, wherein the second portion of the volatile memory is configured to store a copy of second data stored in a non-volatile memory of the memory device.

Abstract: The subject application relates to in-situ compression of data in a main memory and storing of the compressed data in the same main memory to improve memory optimization. A hardware logic of a memory device may receive modified pages from a first portion of memory array, cause a page compression accelerator in the hardware logic to compress the received modified pages to generate compressed data, and facilitate storing of the compressed data to a second portion of memory array of the same memory device. By using in-situ data compression, memory optimization in a computing device is improved.