Patents Examined by Eric Cardwell
  • Patent number: 12650773
    Abstract: An example method for provisioning data volume for a virtual compute instance may include receiving a request to provision a data volume for a virtual compute instance. The request may specify a size of the data volume, a type of the data volume, and a first input/output operations per second (IOPS) value for the data volume. Further, the method may include determining a recommended IOPS value for the data volume by applying a logic to the specified size, the specified type, and the first IOPS value. Furthermore, the method may include provisioning the data volume for the virtual compute instance with the specified size, the specified type, and the recommended IOPS value.
    Type: Grant
    Filed: September 16, 2024
    Date of Patent: June 9, 2026
    Assignee: VMware LLC
    Inventors: Nitin Ramachandra, Priyank Agarwal, Suchitha Shet, Prasanna Ganapathi, Ravi Kasha
  • Patent number: 12645484
    Abstract: In a vehicle-mounted computer that includes a physical resource including a processor with a plurality of cores and a physical device with a register and generates a plurality of virtual devices by allocating the physical resource through time-division, the processor causes at least one virtual device of the plurality of virtual devices to operate on each of the plurality of cores periodically at a predetermined period and causes another virtual device of the plurality of virtual devices to operate non-periodically, stores the core on which the other virtual device operated, and determines the core on which the other virtual device is to operate, based on whether or not the core on which the other virtual device is to operate will be changed and a change amount of a register value of the physical device.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: June 2, 2026
    Assignees: Auto Networks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Tadahiro Takazawa, Koji Yasuda
  • Patent number: 12639215
    Abstract: A host command to deallocate a memory device is received. A logical-to-physical (L2P) status data structure associated with a logical-to-physical (L2P) data structure is invalidated. The L2P mapping data structure includes a plurality of regions. Each region comprises a set of L2P address mappings and a region identifier identifying a respective region. The L2P status data structure includes a plurality of L2P status entries. An L2P status entry comprises a region identifier identifying a region of the plurality of regions of the L2P mapping data structure and a physical address identifying a location of the region of the L2P mapping data structure stored on the memory device. A host is notified that deallocation of the memory device is completed. Invalidation of the L2P mapping data structure is initiated.
    Type: Grant
    Filed: October 15, 2024
    Date of Patent: May 26, 2026
    Assignee: Micron Technology, Inc.
    Inventors: Andrei Konan, Randall David Barber
  • Patent number: 12632182
    Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The memory management method includes: writing first data into N super physical programming units of a first super physical erasing unit in a plurality of super physical erasing units; generating N first temporary parity codes according to the first data and storing the N first temporary parity codes in a buffer memory; writing second data into M super physical programming units of a second super physical erasing unit in the plurality of super physical erasing units; performing an encoding operation on the second data and the N first temporary parity codes to generate N first parity codes; and writing the N first parity codes into the second super physical erasing unit.
    Type: Grant
    Filed: June 3, 2024
    Date of Patent: May 19, 2026
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Horng-Sheng Yan
  • Patent number: 12619373
    Abstract: The present disclosure relates to method for checking the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprises: storing in a dummy row associated to said memory block at least internal block variables and a known pattern; performing a reading of said dummy row; comparing a result of the reading with the known pattern; trimming the parameters of the reading and/or swapping the used memory block based on the result of the comparing.
    Type: Grant
    Filed: November 26, 2024
    Date of Patent: May 5, 2026
    Inventors: Alberto Troia, Antonino Mondello
  • Patent number: 12613639
    Abstract: The memory device is configured to program and erase data in a memory block according to both an SLC storage scheme and a multiple bits per memory cell (e.g., TLC) storage scheme. In operation, control circuitry receives a command to write data to the memory cells of the memory block in the TLC storage scheme and determine if already data stored in the memory block is in the SLC storage scheme or is in the TLC cell storage scheme. In response to a determination that the data contained in the memory block is in the SLC storage scheme, the control circuitry pre-programs the memory cells of the memory block and then erases the memory cells. In response to a determination that the data contained in the memory block is in the TLC storage scheme, then the control circuitry erases the memory cells without pre-programming.
    Type: Grant
    Filed: April 18, 2024
    Date of Patent: April 28, 2026
    Assignee: Sandisk Technologies, Inc.
    Inventors: Yanwei He, Henry Chin
  • Patent number: 12608159
    Abstract: Gap processing is utilized to reorder out-of-order submissions on the normal submission queue. The controller is able to process logical block addresses (LBAs) that are received through the use of a normal NVMe submission queue (SQ) and a private SQ. The normal NVMe SQ will store the LBAs of commands that may arrive out of sequential order for processing. The private SQ is used to store an LBA that is received after a gap is detected. The private SQ is only read after a command is received on the normal SQ that contains the current First Gap LBA. If no entry in the private SQ is sequentially after the first gap LBA, no processing of the private SQ occurs. If the pulled LBA is next, then the LBA will be processed by the data storage device. If the pulled LBA is not next, then the zone gap processing will send the LBA back to the private SQ.
    Type: Grant
    Filed: February 14, 2024
    Date of Patent: April 21, 2026
    Assignee: Sandisk Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty, David Meyer
  • Patent number: 12602187
    Abstract: Systems and methods for collecting trace data via a memory device are disclosed. One method may include receiving, by the memory device, a command from a computing device; identifying, by the memory device, first data associated with the command; storing, by the memory device, the first data in a first portion of volatile memory of the memory device for reading by the computing device; and accessing, by the memory device, a second portion of the volatile memory, wherein the second portion of the volatile memory is configured to store a copy of second data stored in a non-volatile memory of the memory device.
    Type: Grant
    Filed: April 9, 2024
    Date of Patent: April 14, 2026
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongyang Li, Andrew Chang
  • Patent number: 12591364
    Abstract: The subject application relates to in-situ compression of data in a main memory and storing of the compressed data in the same main memory to improve memory optimization. A hardware logic of a memory device may receive modified pages from a first portion of memory array, cause a page compression accelerator in the hardware logic to compress the received modified pages to generate compressed data, and facilitate storing of the compressed data to a second portion of memory array of the same memory device. By using in-situ data compression, memory optimization in a computing device is improved.
    Type: Grant
    Filed: May 21, 2024
    Date of Patent: March 31, 2026
    Assignee: Micron Technology, Inc.
    Inventors: Saideep Tiku, Poorna Kale
  • Patent number: 12572468
    Abstract: A storage device, including: a nonvolatile memory device comprising a plurality of memory cells; and a controller configured to perform a write operation on at least one write unit included in the plurality of memory cells, and to perform an erase operation on at least one erase unit included in the plurality of memory cells, wherein the controller is further configured to: allocate a plurality of zones to a storage space of the nonvolatile memory device based on a request received from an external host device, select two or more erase units from among a plurality of erase units included in the plurality of memory cells to be allocated to each zone of the plurality of zones, fixedly and sequentially manage logical addresses of data to be written in the plurality of zones, and generate at least two map tables for the each zone.
    Type: Grant
    Filed: August 25, 2023
    Date of Patent: March 10, 2026
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seunghyun Choi, Keunsan Park, Joon-Whan Bae, Jooyoung Hwang, Gyeongmin Kim, Heetak Shin, Junyeong Han
  • Patent number: 12561081
    Abstract: An object of the invention is to reduce a performance decrease in remote copy performed between a second storage system and a first storage system including a plurality of nodes. For each of a plurality of paths between the first and second storage systems, the path is a path that communicably connects any initiator port of the first storage system and any target port of the second storage system. The node includes a first VOL that forms a remote copy pair with a second VOL provided in the second storage system. When sending a command for the remote copy in the remote copy pair to the second storage system, the node selects, unless an abnormality related to the initiator port of the node is detected, the path connected to the initiator port, and sends the command via the selected path.
    Type: Grant
    Filed: February 27, 2024
    Date of Patent: February 24, 2026
    Assignee: HITACHI VANTARA, LTD.
    Inventors: Misato Yoshida, Takahiro Yamamoto
  • Patent number: 12554427
    Abstract: Systems and methods for reducing read application in a virtual storage system are provided. According to one embodiment, read amplification is reduced when AZCS compression is being utilized by avoiding restarting of a read process via a slow path via a RAID layer of the virtual storage system when a data block associated with a read request and obtained via a first fast path read has been found not to be compressed. Instead, a second fast path read may be performed to obtain the corresponding checksum. Alternatively, or additionally, heuristics may be used to predict the odds of the data block being compressed. For example, when information encoded within a PVBN of the data block that identifies the PVBN as being within a compressed AZCS zone has shown to be sufficiently/insufficiently predictive of the data block being compressed, then a flag may be set to enable/disable fast path reads.
    Type: Grant
    Filed: July 22, 2024
    Date of Patent: February 17, 2026
    Assignee: NetApp, Inc.
    Inventors: Ritika, Jagadish Vasudeva, Vani Vully, Raj Kamal, Deepak Dangi, Parag Deshmukh
  • Patent number: 12547336
    Abstract: The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the flash memory module includes a plurality of blocks. The control method includes the steps of: obtaining a read count of a specific block; obtaining a time stamp of the specific block, wherein the time stamp is a write time of the specific block; calculating a time difference between a current system time and the time stamp of the specific block; and using the read count of the specific block and the time difference, and referring to a read count and threshold time mapping table to determine whether to arrange the specific block in a garbage collection pool.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: February 10, 2026
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 12547350
    Abstract: In order to avoid writing duplicates of blocks of data into a storage platform, any virtual disk within the storage platform may have a de-duplication feature enabled. Or, all virtual disks have this feature enabled. For virtual disks with de-duplication enabled, a unique message digest is calculated for every block of data written to that virtual disk. Upon a write, these message digests are consulted in order to determine if a particular block of data has already been written, if so, it is not written again, and if not, it is written. All de-duplication virtual disks are written to a single system virtual disk within the storage platform. De-duplication occurs over the entire storage platform and over all its virtual disks because all message digests are consulted before a write is performed for any virtual disk. A read for a de-duplication virtual desk reads from the system virtual disk.
    Type: Grant
    Filed: August 22, 2024
    Date of Patent: February 10, 2026
    Assignee: Commvault Systems, Inc.
    Inventors: Avinash Lakshman, Gaurav Yadav
  • Patent number: 12541302
    Abstract: In performing a copyback operation, a copyback command for target data that are programmed in a source area based on first voltage levels is received. A hard data read operation and a soft data read operation are performed on the target data based on the copyback command. Memory cells in the source area are classified into normal memory cells and weak memory cells, based on results of the hard data read operation and the soft data read operation. A first copyback program operation in which first data among the target data are stored in a destination area is performed, based on second voltage levels. The first data correspond to the normal memory cells. A second copyback program operation in which second data among the target data are stored in the destination area is performed, based on third voltage levels. The second data correspond to the weak memory cells.
    Type: Grant
    Filed: September 10, 2024
    Date of Patent: February 3, 2026
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myungkyu Kim, Beomkyu Shin, Jungho Park
  • Patent number: 12536113
    Abstract: A page status management method includes collecting statistics on N first memory access commands received in a first time window; determining reception interval information of the N first memory access commands, where the reception interval information indicates denseness of a stream of commands in the first time window; determining active standby time based on the reception interval information; and after a second memory access command accesses a target memory page, if no other memory access command accesses the target memory page within the active standby time, closing the target memory page, where the second memory access command is any memory access command received in a second time window, and the second time window is a time window after the first time window.
    Type: Grant
    Filed: September 19, 2024
    Date of Patent: January 27, 2026
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Zhenjun Liu, Chuanzeng Liang, Erqing Qian, Biwei He
  • Patent number: 12499020
    Abstract: A centralized orchestrator configured to be the only resource managing the distributed LVMs whereby orchestrator is further configured to queue parallel operations on the distributed LVM, making sure only one operation is performed at a time, without a cluster.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: December 16, 2025
    Assignee: VOLUMEZ TECHNOLOGIES LTD.
    Inventor: Jonathan Amit
  • Patent number: 12498885
    Abstract: In accordance with some embodiments of the present disclosure, a method is performed on a memory storage device for updating data stored in the memory storage device. The method includes writing a first stream data to a first portion of memory, wherein the first stream data includes a plurality of substreams, and writing first additional data to a second portion of memory, wherein the first additional data includes data indicative of an update of at least one substream of the first stream data and is no larger than a substream of the plurality of substreams of the first stream data. Concurrent with writing the first additional data, the method also includes writing second additional data to the second portion of memory, wherein the second additional data includes at least one of data indicative of an update of at least one substream of a second stream data, or non-stream data.
    Type: Grant
    Filed: November 16, 2023
    Date of Patent: December 16, 2025
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Sanjay Subbarao, Sriram Natarajan, Weng-Chin Yung, Swapna Galireddy
  • Patent number: 12475032
    Abstract: The present disclosure generally relates to improved consolidation in dual-layer FTL. In preparation for the next control sync, the controller will generate a copy the uRegions uHeaders and will continue updating the uLayer uRegion with new uRun entries. After completing the control sync operation, the controller will then select the best consolidation candidate based on comparing the uRegion uHeaders with their copy and determining the uRegion with the maximum uRuns difference or the greatest number of uRun updates in case the uRun updates difference is less than a threshold. The controller then reads the selected mSets from the flash memory to its cache and merges the updated uRuns with the cached mSets.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: November 18, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Marina Frid, Vered Kelner, Igor Genshaft
  • Patent number: 12474841
    Abstract: When entering low power mode, any commands that are fetched and waiting to be executed are completed. When the data storage device exits low power mode, new commands are fetched. The completing and fetching takes time. Rather than completing all of the commands, some selected commands can be stored in a persistent memory region (PMR) when entering low power mode. The storing in PMR is faster than completing the commands. Furthermore, retrieving the commands from PMR is faster than retrieving new commands from a host device on exiting low power mode. Thus, using PMR results in more efficient use of data storage device bandwidth.
    Type: Grant
    Filed: August 27, 2024
    Date of Patent: November 18, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Amir Segev, Amir Rozen, Shay Benisty