Patents Examined by Eric Cardwell
  • Patent number: 12754686
    Abstract: Systems and methods are described for performing persistent inflight tracking of operations (Ops) within a cross-site storage solution. According to one embodiment, a method comprises maintaining state information regarding a data synchronous replication status for a first storage object of a primary storage cluster and a second storage object of a secondary storage cluster. The method includes performing persistent inflight tracking of I/O operations with a first Op log of the primary storage cluster and a second Op log of the secondary storage cluster, establishing and comparing Op ranges for the first and second Op logs, and determining a relation between the Op range of the first Op log and the Op range of the second Op log to prevent divergence of Ops in the first and second Op logs and to support parallel split of the Ops.
    Type: Grant
    Filed: November 21, 2024
    Date of Patent: October 6, 2026
    Assignee: NetApp, Inc.
    Inventors: Krishna Murthy Chandraiah Setty Narasingarayanapeta, Preetham Shenoy, Divya Kathiresan, Rakesh Bhargava
  • Patent number: 12754768
    Abstract: A system for executing a multi-tenant application includes at least one processor and at least one memory storing program instructions. The multi-tenant application generates one or more page size recommendations and one or more sequential request count recommendations for one or more calls to an external database. The multi-tenant application performs a first call to the external database using a page size which is based on a first page size recommendation, where the page size specifies a number of records to retrieve from the external database. The multi-tenant application also performs, in a sequential manner by the multi-tenant application, the first call and a number of subsequent calls to the external database, where the number of subsequent calls is based on a first sequential request count recommendation. Related methods and computer program products are also provided.
    Type: Grant
    Filed: October 9, 2023
    Date of Patent: October 6, 2026
    Assignee: SAP SE
    Inventor: Apoorv Bhargava
  • Patent number: 12754693
    Abstract: Multiple cache occupation bitmaps are maintained with each successive bitmap having a more focused granularity based upon data hotness or overlay collisions. The bitmap with the least focus is checked first, and if a value of 1 is found for the relevant bit, then a relevant bit of the next, more focused, bitmap that encompasses the address range of the read command is checked. Relevant bits of each additional, more focused bitmap that encompasses the address range for the read command are checked in succession upon finding a value of 1 for the relevant bit in the previous bitmap. Upon the last relevant bit of a bitmap encompassing the address range of the read command having a value of 1 or 0, either a full cache scan is performed or no overlap is present. The bitmaps can be flexibly and dynamically maintained.
    Type: Grant
    Filed: July 11, 2024
    Date of Patent: October 6, 2026
    Assignee: Sandisk Technologies, Inc.
    Inventors: Shay Benisty, Ariel Navon
  • Patent number: 12748706
    Abstract: A computing device may search for a plurality of first physical addresses that are start physical addresses corresponding to a plurality of first virtual addresses from a page table based on a first start virtual address that is a start address of a virtual address space including the plurality of first virtual addresses corresponding to a plurality of first pages for a first storage device, and transmit a first access request for at least one first physical address of the plurality of first physical addresses to the first storage device using a first storage controller.
    Type: Grant
    Filed: June 12, 2024
    Date of Patent: September 29, 2026
    Assignee: SK hynix Inc.
    Inventors: Soo Kyung Choi, Jae Yung Jun, Kwang Sik Shin, Se Eun Oh
  • Patent number: 12724533
    Abstract: A method for data transmission is provided. The method includes, at an initiator computing device, receiving a data payload to be transmitted to a target computing device for storage using the nonvolatile memory express over fabric (NVMe-oF) protocol, wherein the data payload is represented as a plurality of logical blocks. Using a compression engine, the data payload is compressed into a plurality of physical blocks having a smaller total data size than the plurality of logical blocks. A write request is transmitted to the target computing device, the write request including the plurality of physical blocks, and metadata specifying a correspondence between each logical block of the plurality of logical blocks and one or more corresponding physical blocks of the plurality of physical blocks.
    Type: Grant
    Filed: August 22, 2024
    Date of Patent: September 1, 2026
    Assignee: Beijing Volcano Engine Technology Co., Ltd.
    Inventors: Peng Xu, Fei Liu, Kyoungryun Bae, Wei Tang, Jin Kim, Yahui Feng, Prathamesh Amritkar, Peng Liu, Guojun Li
  • Patent number: 12717715
    Abstract: A method includes writing, to a first data structure, indices corresponding to address locations of a logical-to-physical (L2P) data structure that maps a plurality of logical block addresses (LBAs) associated with the L2P data structure, initiating performance of a media management operation involving one or more memory blocks in which data associated with the LBAs is written, and refraining from rewriting particular entries in the L2P table that correspond to LBAs whose index in the first data structure is a particular value during performance of the media management operation.
    Type: Grant
    Filed: January 15, 2025
    Date of Patent: August 25, 2026
    Assignee: Micron Technology, Inc.
    Inventors: Xiangang Luo, Jianmin Huang, Xiaolai Zhu, Deping He, Kulachet Tanpairoj, Hong Lu, Chun Sum Yeung
  • Patent number: 12717484
    Abstract: Methods, systems, and devices for an interface layout for stacked memory architectures are described. A memory interface block may interface a plurality of memory dies to a host controller. The memory interface block may include an interface block coupled with multiple memory dies, which may be stacked on the memory interface block using through-silicon-vias. The memory interface block may include controllers, datapath blocks, and interface blocks associated with each memory die. As such, the memory interface block may perform functions such as queueing, ECC, and performing row repair and column repair procedures. In some examples, a layout for the memory interface block may include pairing controllers for at least two memory devices, such that a pair of controllers may share a command port to a pair of memory dies. Further, the memory interface block may include interfaces to the host controller that are different from the interface to each memory die.
    Type: Grant
    Filed: May 21, 2024
    Date of Patent: August 25, 2026
    Assignee: Micron Technology, Inc.
    Inventors: Nathan A. Eckel, Lance P. Johnson, Paul A. Laberge
  • Patent number: 12704970
    Abstract: A processing device, operatively coupled with a memory device, performs a first programming operation on a first set of cells associated with a first sub-block of a first die of the memory device, wherein each die of the memory device comprises a plurality of sub-blocks. The processing device identifies, based on a first predefined value, a second sub-block of a second die of the memory device on which to perform a second programming operation, wherein the first predefined value is a shift in an index value of the first sub-block of the first die of the memory device. The processing device further performs the second programming operation on a second set of cells associated with the second sub-block of the second die, wherein the second sub-block of the second die is associated with a different index value than the first sub-block of the first die.
    Type: Grant
    Filed: January 2, 2024
    Date of Patent: August 11, 2026
    Assignee: Micron Technology, Inc.
    Inventors: Yu-Chung Lien, Tomer Tzvi Eliash, Zhenming Zhou
  • Patent number: 12693787
    Abstract: A technique manages solid state device (SSD) wear-level. The technique involves storing data on a plurality of SSDs. The technique further involves, based on storing the data on the plurality of SSDs, identifying a particular SSD of the plurality of SSDs as a target SSD. The technique further involves moving write-hot data to the particular SSD identified as the target SSD to increase writing workload on the particular SSD compared to respective writing workloads on other SSDs of the plurality of SSDs. Accordingly, the particular SSD wears out ahead of the other SSDs and avoids multiple SSD failures at the same time which otherwise could result in data unavailability (DU) and/or data loss (DL).
    Type: Grant
    Filed: August 5, 2024
    Date of Patent: July 28, 2026
    Assignee: Dell Products L.P.
    Inventors: Vamsi K. Vankamamidi, Geng Han, Chun Ma
  • Patent number: 12675226
    Abstract: Examples of the present disclosure disclose host and an operation method thereof, a memory system and an operation method thereof, and an electronic apparatus. The host is coupled with a memory system supporting a zone namespace function; the memory system includes a memory device, and the memory device includes K dies; the K dies are divided into N disturbance areas, each disturbance area includes at least one die, and one block in each die in the disturbance area constitutes a zone jointly; K and N are positive integers greater than or equal to 2; the host is configured to: send a command to the memory system to perform a respective operation on zones corresponding to the command at the same time, wherein the zones corresponding to the command belong to different disturbance areas.
    Type: Grant
    Filed: September 21, 2024
    Date of Patent: July 7, 2026
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Mo Cheng, Tianyi Wang
  • Patent number: 12669961
    Abstract: Provided are a computer program product, system, and method for coordinating establishment of source and target copy relationships on primary and secondary servers. A command is received to establish a primary copy relationship of primary source data in the primary storage to copy to primary target data in the primary storage and a secondary copy relationship of secondary source data in the secondary storage to copy to secondary target data in the secondary storage. A determination is made as to whether a part of the secondary target data in a secondary pre-existing copy relationship at the secondary storage can be withdrawn from the secondary pre-existing copy relationship. In response to determining that the part of the secondary target data in the secondary pre-existing copy relationship can be withdrawn, establishing the primary copy relationship for the primary storage and establishing the secondary copy relationship for the secondary storage.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: June 30, 2026
    Assignee: International Business Machines Corporation
    Inventors: Nedlaya Yazzie Francisco, Theresa Mary Brown, Gregory Edward McBride
  • Patent number: 12669936
    Abstract: Methods, systems, and devices for folding operations for improved sequential read performance are described. A memory system may perform a single-die access operation to program data to source data blocks of the memory system. The memory system may reorder the data during folding to destination data blocks of the memory system such that a multi-die access operation may be performed to sequentially read the data from the destination data blocks. For example, data may be programmed to the source data blocks in a first order as part of a single-die access operation, and the data may be folded to the destination data blocks in a second order as part of a single-die access operation, where the supports sequentially reading the data from the destination data blocks as part of a multi-die access operation.
    Type: Grant
    Filed: December 22, 2023
    Date of Patent: June 30, 2026
    Assignee: Micron Technology, Inc.
    Inventors: Nitul Gohain, Nicola Colella, Jameer Mulani
  • Patent number: 12669948
    Abstract: A memory module may include a first storage device, and a second storage device configured to receive information about a first temperature indicating an internal temperature of the first storage device and to change a threshold temperature from a first threshold temperature to a second threshold temperature different from the first threshold temperature based on the information, to enter a mode in which an internal temperature of the second storage device is controlled when the temperature of the second storage device is higher than the threshold temperature.
    Type: Grant
    Filed: January 17, 2024
    Date of Patent: June 30, 2026
    Assignee: SK hynix Inc.
    Inventors: Jeong Ho Jeon, Seok Ho Seo
  • Patent number: 12663933
    Abstract: The present disclosure provides a storage management system, method, device, and machine-readable storage medium, the system including: a controller pool, to interact to-be-stored data and/or to-be-read data with an external device via network communication; a memory pool, to read and write high-speed temporary data and/or high-speed persistent data; an accelerator pool, to call a corresponding accelerator to process and distribute data according to a storage service type associated with data; a storage pool, to store to-be-stored data processed by the accelerator pool and/or read the to-be-read data; and a transmission module, to establish a system transmission network among the controller pool, the memory pool, the accelerator pool and the storage pool.
    Type: Grant
    Filed: December 5, 2024
    Date of Patent: June 23, 2026
    Assignee: NEW H3C INFORMATION TECHNOLOGIES CO., LTD.
    Inventor: Tianjie Zhang
  • Patent number: 12663944
    Abstract: The invention introduces a method for controlling executions of input-output (I/O) commands, performed by a processing unit, which includes: obtaining a current temperature of a device side; fetching I/O commands from a command queue during a fetching time period, and executing the I/O commands to read user data from the flash module, and/or program user data into the flash module in response to the current temperature of the device side exceeding a threshold; calculating a length of an actual execution time period for the I/O commands, and calculating a length of a pause time period according to the length of the actual execution time period after the I/O commands are executed completely; and not fetching and executing any I/O command in the command queue during the pause time period.
    Type: Grant
    Filed: September 24, 2024
    Date of Patent: June 23, 2026
    Assignee: SILICON MOTION, INC.
    Inventors: Ting-Chu Lee, Cheng-Yu Tsai
  • Patent number: 12650773
    Abstract: An example method for provisioning data volume for a virtual compute instance may include receiving a request to provision a data volume for a virtual compute instance. The request may specify a size of the data volume, a type of the data volume, and a first input/output operations per second (IOPS) value for the data volume. Further, the method may include determining a recommended IOPS value for the data volume by applying a logic to the specified size, the specified type, and the first IOPS value. Furthermore, the method may include provisioning the data volume for the virtual compute instance with the specified size, the specified type, and the recommended IOPS value.
    Type: Grant
    Filed: September 16, 2024
    Date of Patent: June 9, 2026
    Assignee: VMware LLC
    Inventors: Nitin Ramachandra, Priyank Agarwal, Suchitha Shet, Prasanna Ganapathi, Ravi Kasha
  • Patent number: 12645484
    Abstract: In a vehicle-mounted computer that includes a physical resource including a processor with a plurality of cores and a physical device with a register and generates a plurality of virtual devices by allocating the physical resource through time-division, the processor causes at least one virtual device of the plurality of virtual devices to operate on each of the plurality of cores periodically at a predetermined period and causes another virtual device of the plurality of virtual devices to operate non-periodically, stores the core on which the other virtual device operated, and determines the core on which the other virtual device is to operate, based on whether or not the core on which the other virtual device is to operate will be changed and a change amount of a register value of the physical device.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: June 2, 2026
    Assignees: Auto Networks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Tadahiro Takazawa, Koji Yasuda
  • Patent number: 12639215
    Abstract: A host command to deallocate a memory device is received. A logical-to-physical (L2P) status data structure associated with a logical-to-physical (L2P) data structure is invalidated. The L2P mapping data structure includes a plurality of regions. Each region comprises a set of L2P address mappings and a region identifier identifying a respective region. The L2P status data structure includes a plurality of L2P status entries. An L2P status entry comprises a region identifier identifying a region of the plurality of regions of the L2P mapping data structure and a physical address identifying a location of the region of the L2P mapping data structure stored on the memory device. A host is notified that deallocation of the memory device is completed. Invalidation of the L2P mapping data structure is initiated.
    Type: Grant
    Filed: October 15, 2024
    Date of Patent: May 26, 2026
    Assignee: Micron Technology, Inc.
    Inventors: Andrei Konan, Randall David Barber
  • Patent number: 12632182
    Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The memory management method includes: writing first data into N super physical programming units of a first super physical erasing unit in a plurality of super physical erasing units; generating N first temporary parity codes according to the first data and storing the N first temporary parity codes in a buffer memory; writing second data into M super physical programming units of a second super physical erasing unit in the plurality of super physical erasing units; performing an encoding operation on the second data and the N first temporary parity codes to generate N first parity codes; and writing the N first parity codes into the second super physical erasing unit.
    Type: Grant
    Filed: June 3, 2024
    Date of Patent: May 19, 2026
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Horng-Sheng Yan
  • Patent number: 12619373
    Abstract: The present disclosure relates to method for checking the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprises: storing in a dummy row associated to said memory block at least internal block variables and a known pattern; performing a reading of said dummy row; comparing a result of the reading with the known pattern; trimming the parameters of the reading and/or swapping the used memory block based on the result of the comparing.
    Type: Grant
    Filed: November 26, 2024
    Date of Patent: May 5, 2026
    Inventors: Alberto Troia, Antonino Mondello