Abstract: Data may be replicated from a host storage system to a target storage system. It may be determined to replicate a first logical storage element on the source storage system to a second logical storage element on the target storage system, wherein the first logical storage element defines a first data portion having a first value. It may be determined that a third logical storage element on the target storage system defines a second data portion having the first value. The first logical storage element may be replicated to the second logical storage element by establishing a deduplication relationship between the second logical storage element and the third logical storage element on the target storage system without transmitting the first data portion from the source storage system to the target storage system.

Abstract: Storage devices can be configured to desirably reduce the number of times a zone reset or erasure occur via the use of one or more paired overwrite memory blocks. These storage devices can include a plurality of memory devices with some of these memory devices designated as overwrite memory devices. A controller within the storage device can be configured to direct the storage device to generate one or more subsets within the memory devices such as zones, pair each of subsets with at least one or more overwrite memory devices, store data sequentially within the subset of memory devices, and store any received overwrite data in the overwrite memory devices in chronological order. Data stored within the subsets of memory devices are not erased and instead of being overwritten directly, are instead pointed via a control table to a location in the overwrite memory devices storing the corresponding overwrite data.

Abstract: Storage devices include a memory array comprised of a plurality of memory devices. As memory array density increases, multi-pass programming is utilized to reduce negative effects to neighboring memory devices. The use of multi-pass programming requires longer access to the data being programmed. To avoid adding additional lower density or controller memory, data within a host memory is accessed multiple times as needed to provide pieces of data to the memory array, which is configured to comply with the utilized multi-pass programming method. The expected order of the multi-pass programming method can be determined to generate one or more memory pipeline instruction processing queues to direct the components of the storage device memory pipeline to access, re-access, and process the host data in a specific order necessary for delivery to the memory array to comply with the utilized multi-pass programming method.

Abstract: Example methods and systems to perform a migration of a virtualized computing instance and its first snapshot hierarchy from a first object store to a second object store have been disclosed. One example method includes identifying a first disk chain of the first snapshot hierarchy having an object running point, identifying a second disk chain of the first snapshot hierarchy different from the first disk chain, and migrating the second disk chain from the first object store to the second object store to form a first branch of a second snapshot hierarchy in the second object store. After the migrating, the example method includes instructing to take a first native snapshot on the object running point in the second object store, instructing to revert the object running point along the first branch and migrating the first disk chain from the first object store to the second object store.

Abstract: Systems, methods, and computer readable storage mediums for performing remote replication including receiving, by a target storage system, an indication that a dataset stored on a source storage system will be replicated to the target storage system; identifying, by the target storage system, portions of the dataset that are not already stored on the target storage system; and initiating, by the target storage system, replication of one or more of the portions of the dataset that are not already stored on the target storage system from a source other than the source storage system.

Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

Abstract: An apparatus comprises at least one processing device. The at least one processing device is configured to obtain storage-side performance information maintained by a storage system in conjunction with processing of input-output operations directed to the storage system by a host device over a network, to dynamically select a particular one of a plurality of distinct load balancing policies available in the host device based at least in part on the obtained storage-side performance information, and to apply the selected load balancing policy in directing additional input-output operations from the host device to the storage system. At least one of the load balancing policies comprises a storage cache aware load balancing policy that causes different ones of the input-output operations to be directed to different cache entities of the storage system based at least in part on cache-related performance metrics of the obtained storage-side performance information.

Abstract: In a method of operating storage devices including a first storage device and a second storage device connected to each other via a host device, a data migration request for a first namespace included in the first storage device is received. A second namespace is generated in the second storage device. The second namespace corresponds to the first namespace. A pointer table that is used to perform a data migration operation corresponding to the data migration request is set. First data and second data are migrated to the second namespace based on the pointer table. The first data is stored in the first namespace. The second data is stored in a first buffer memory included in the first storage device and corresponds to the first namespace. Based on the data migration operation being performed, the second data is directly transmitted from the first buffer memory to the second namespace.

Abstract: Various embodiments set forth techniques for managing and/or accessing metadata associated with a vblock, systems implementing said techniques, and computer-readable media storing instructions for performing said techniques. In some embodiments, one or more computer-readable media store instructions that, when executed by one or more processors, cause the one or more processors to perform steps including receiving a request for metadata associated with a vblock; accessing a merged metadata record associated with the vblock, where the merged metadata record comprises metadata corresponding to metadata in metadata records for all but a last snapshot or a live vblock having a metadata record, and a first identifier of the last snapshot or the live vblock having a metadata record; and returning the requested metadata based on the metadata in the merged metadata record and metadata in the metadata record identified by the first identifier.

Abstract: Systems and methods for predicting whether a nonvolatile memory block is likely capable of being securely erased to be eligible for composing into another composable infrastructure are described. A management module receives a secure-erase command to erase at least one nonvolatile memory block, determines health parameters of the nonvolatile memory block, calculates a failure index based on the health parameters, and, based on the failure index, either securely erases the block of memory or retires the nonvolatile memory block.

Abstract: In order to avoid writing duplicates of blocks of data into a storage platform, any virtual disk within the storage platform may have a de-duplication feature enabled. Or, all virtual disks have this feature enabled. For virtual disks with de-duplication enabled, a unique message digest is calculated for every block of data written to that virtual disk. Upon a write, these message digests are consulted in order to determine if a particular block of data has already been written, if so, it is not written again, and if not, it is written. All de-duplication virtual disks are written to a single system virtual disk within the storage platform. De-duplication occurs over the entire storage platform and over all its virtual disks because all message digests are consulted before a write is performed for any virtual disk. A read for a de-duplication virtual desk reads from the system virtual disk.

Abstract: An apparatus which includes a first solid state drive (SSD) located on an SSD card having a fixed capacity and a first form factor. The apparatus can further include an adapter located on the SSD card to accommodate a second SSD. The second SSD has a second form factor that is different than the first form factor and is removeable from the SSD card. The apparatus can further include a controller located on the SSD card and configured to access the first SSD and the second SSD.

Abstract: Various embodiments described herein provide for using analysis of a sequence of commands (issued by a host system) to manage a memory command component, such as a read engine or a write engine of a memory system.

Abstract: Apparatus and methods are disclosed, including using a memory controller to track a maximum logical saturation over the lifespan of the memory device, where logical saturation is the percentage of capacity of the memory device written with data. A portion of a pool of memory cells of the memory device is reallocated from single level cell (SLC) static cache to SLC dynamic cache storage based at least in part on a value of the maximum logical saturation, the reallocating including writing at least one electrical state to a register, in some examples.

Abstract: Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.

Abstract: An intelligent method of scheduling garbage collection (GC) in a storage system. A GC scheduler obtains capacity utilization and ingest rate of the storage system and calculate therefrom a predicted capacity utilization. When the predicted capacity utilization reaches a threshold, the GC scheduler invokes GC, but otherwise skips GC until such time as predicted capacity utilization reaches the threshold. The ingest rage may be calculated by performing linear fit on past data ingest. The GC scheduler may calculate predicted capacity utilization periodically according to preset period. The GC scheduler may calculate the predicted capacity utilization to a future date beyond the next period. The future date may be at least as far as the next period plus total ingest time.

Abstract: Techniques involve implementing a file system. According to such techniques, a storage system creates a plurality of files in advance, each of which maintains a continuous space to simplify the process of processing read/write requests in the file system. When there is data to be written, an appropriate pre-created file is selected. Further, according to such techniques, a file system address is mapped to a physical address using a memory management unit. In this way, the file system performance is improved greatly.

Abstract: A solid-state drive configured to store persistent digitally encoded data may operate in an initiator mode. When operating in the initiator mode, the solid-state drive may initiate the generation and issuance of a command or a request for another solid-state drive to carry out a data storage related procedure. The command or request generated by the solid-state drive may be communicated directly to another solid-state drive without the communications passing through an intermediate device, such as a host processor.

Abstract: A storage control system is configured to obtain first data associated with a logical data device and to store the first data in a first entry of a log-structured array. The storage control system is further configured to invalidate a second entry of the log-structured array based at least in part on the storage of the first data in the first entry. The second entry comprises second data that was associated with the logical data device prior to obtaining the first data. The storage control system is further configured to determine that a first indication in a first metadata indicates that the invalidated second entry corresponds to a transaction log and to defer reclamation of the second entry based at least in part on the determination that the first indication in the first metadata indicates that the invalidated second entry corresponds to the transaction log.

Abstract: Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.