Abstract: A contact type electret condenser pickup to deliver high anti noise, top talking quality, and comprehensive range of applications includes a casing provided with an accommodation chamber to contain an O-ring, a vibration part, an insulation packing, a back plate retaining ring containing a back plate, a conductive connection ring, and a circuit board horizontally placed in sequence; vibration of a sound of a user is transmitted to the vibration part; then an inertia vibration of the metal sheet changes capacitance between the vibration part and the back plate; the changed vibration is converted through the circuit board set into voltage of alternating signals for output variable according to changes of vibration.
Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.
Type:
Grant
Filed:
August 29, 2008
Date of Patent:
December 20, 2011
Assignee:
International Business Machines Corporation
Abstract: Latchup is prevented from occurring accompanying increasingly finer geometries of a chip. NchMOSFET N1 and PchMOSFET P1 form a CMOS circuit including: NchMOSFET N2 whose gate, drain and back gate are connected to back gate of N1 and PchMOSFET P2 whose gate, drain and back gate are connected to back gate of P1. Source of N2 is connected to source of N1. Source of P2 is connected to source of P1. N2 is always connected between the grounded source of N1 and the back gate of N1, while P2 is connected between source of P1 connected to a power supply and the back gate of P1. Each of N2 and P2 functions as a voltage limiting element (a limiter circuit).
Abstract: There is provided a semiconductor light-emitting element and a method of producing the same including high density and high quality quantum dots emitting light at a wavelength of 1.3 ?m. A semiconductor light-emitting element has a first GaAs layer, a second InAs thin film layer having the plurality of InAs quantum dots formed on the first GaAs layer, a third InGaAs layer formed on the second InAs thin film layer having the plurality of InAs quantum dots, and a fourth GaAs layer formed on the third InGaAs layer, wherein the As source is As2.
Type:
Grant
Filed:
August 27, 2008
Date of Patent:
October 18, 2011
Assignee:
National Institute of Advanced Industrial Science and Technology
Abstract: An object is to provide a method for manufacturing an SOI substrate including a single crystal silicon film whose plane orientation is (100) and a single crystal silicon film whose plane orientation is (110) with high yield. A first single crystal silicon substrate whose plane orientation is (100) is doped with first ions to form a first embrittlement layer. A second single crystal silicon substrate whose plane orientation is (110) is doped with second ions to selectively form a second embrittlement layer. Only part of the first single crystal silicon substrate is separated along the first embrittlement layer by first heat treatment, thereby forming a first single crystal silicon film. A region of the second single crystal silicon substrate, in which the second embrittlement layer is not formed, is removed. Part of the second single crystal silicon substrate is separated along the second embrittlement layer by second heat treatment, thereby forming a second single crystal silicon film.
Type:
Grant
Filed:
November 10, 2009
Date of Patent:
October 4, 2011
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
Abstract: Oxide films are deposited under conditions generating a silicon-rich oxide in which silicon nanoclusters form either during deposition or during subsequent annealing. Such deposition conditions include those producing films with optical indices (n) greater than 1.46. The method of the present invention reduces the TID radiation-induced shifts for the oxides.
Type:
Grant
Filed:
February 28, 2006
Date of Patent:
September 20, 2011
Assignee:
The United States of America as represented by the Secretary of the Navy
Inventors:
Harold L Hughes, Bernard J Mrstik, Reed K Lawrence, Patrick J McMarr