Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Abstract: A thin film transistor is provided, which includes a gate insulating layer covering a gate electrode, a microcrystalline semiconductor layer provided over the gate insulating layer, an amorphous semiconductor layer overlapping the microcrystalline semiconductor layer and the gate insulating layer, and a pair of impurity semiconductor layers which are provided over the amorphous semiconductor layer and to which an impurity element imparting one conductivity type is added to form a source region and a drain region. The gate insulating layer has a step adjacent to a portion in contact with an end portion of the microcrystalline semiconductor layer. A second thickness of the gate insulating layer in a portion outside the microcrystalline semiconductor layer is smaller than a first thickness thereof in a portion in contact with the microcrystalline semiconductor layer.

Abstract: A method for manufacturing a solar cell is presented. The method includes: forming an amorphous silicon layer on a first surface of a light absorbing layer; doping the amorphous silicon layer with a dopant; forming a dopant layer by diffusing the dopant into the amorphous silicon layer with a laser; forming a semiconductor layer by removing the dopant that remains outside the dopant layer; etching the surface of the semiconductor layer by using an etchant; forming a first electrode on the semiconductor layer; and forming a second electrode on a second surface of the light absorbing layer.

Abstract: The present invention is directed to post-deposition, wet etch processes for patterning AuSn solder material and devices fabricated using such processes. The processes can be applied to uniform AuSn layers to generate submicron patterning of thin AuSn layers having a wide variety of features. The use of multiple etching steps that alternate between different mixes of chemicals enables the etch to proceed effectively, and the same or similar processes can be used to etch under bump metallization. The processes are simple, cost-effective, do not contaminate equipment or tools, and are compatible with standard cleanroom fabrication processes.

Abstract: A condenser microphone having a flexure hinge diaphragm and a method of manufacturing the same are provided. The method includes the steps of: forming a lower silicon layer and a first insulating layer; forming an upper silicon layer on the first insulating layer; forming sound holes by patterning the upper silicon layer; forming a second insulating layer and a conductive layer on the upper silicon layer; forming a passivation layer on the conductive layer; forming a sacrificial layer on the passivation layer; depositing a diaphragm on the sacrificial layer, and forming air holes passing through the diaphragm; forming electrode pads on the passivation layer and a region of the diaphragm; and etching the layers to form an air gap between the diaphragm and the upper silicon layer. Consequently, a manufacturing process may improve the sensitivity and reduce the size of the condenser microphone.

Abstract: A method of manufacturing an ohmic contact layer and a method of manufacturing a top emission type nitride-based light emitting device having the ohmic contact layer are provided. The method of manufacturing an ohmic contact layer includes: forming a first conductive material layer on a semiconductor layer; forming a mask layer having a plurality of nano-sized islands on the first conductive material layer; forming a second conductive material layer on the first conductive material layer and the mask layer; and removing the portion of the second conductive material on the islands and the islands through a lift-off process using a solvent. The method ensures the maintenance of good electrical characteristics and an increase of the light extraction efficiency.

Abstract: A method of manufacturing a semiconductor device, in which an amorphous silicon layer is formed into a shape of a gate electrode of a MOS transistor, and then impurity is implanted to a surface of a silicon substrate from a diagonal direction using the amorphous silicon layer as a mask.

Abstract: Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract: By providing a body controlled double channel transistor, increased functionality in combination with enhanced stability may be accomplished. For instance, flip flop circuits usable for static RAM cells may be formed on the basis of the body controlled double channel transistor, thereby reducing the number of transistors required per cell, which may result in increased information density.

Abstract: A chip quality determination method includes the steps of (a) determining the continuity of defective chips in at least four directions of an X-axis and a Y-axis on a wafer based on the wafer test result of determining the acceptability of chips arranged in a matrix in the four directions on the wafer, and dividing the defective chips into one or more defective groups so that successive ones of the defective chips are in the same defective group; (b) calculating a quality determination index of each of one or more determination target wafer periphery neighboring chips among wafer periphery neighboring chips located within a predetermined range from the periphery of the wafer based on the distance from a corresponding one of the defective groups; and (c) determining the quality of the determination target wafer periphery neighboring chips by comparing the quality determination indexes thereof with a preset threshold.

Abstract: A micromini condenser microphone having a flexure hinge-shaped upper diaphragm and a back plate, and a method of manufacturing the same are provided.

Abstract: The present invention provides a semiconductor device which is formed at low cost and has a great versatility, a manufacturing method thereof, and further a semiconductor device with an improved yield, and a manufacturing method thereof. A structure, which has a base including a plurality of depressions having different shapes or sizes, and a plurality of IC chips which are disposed in the depressions and which fit the depressions, is formed. A semiconductor device which selectively includes a function in accordance with an application, by using the base including the plurality of depressions and the IC chips which fit the depressions, can be manufactured at low cost.

Abstract: A gate electrode is formed by forming a first conductive layer containing aluminum as its main component over a substrate, forming a second conductive layer made from a material different from that used for forming the first conductive layer over the first conductive layer; and patterning the first conductive layer and the second conductive layer. Further, the first conductive layer includes one or more selected from carbon, chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel. And the second conductive layer includes one or more selected from chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel, or nitride of these materials.

Abstract: The present invention is a process for forming an air gap within a substrate, the process comprising: providing a substrate; depositing a sacrificial material by deposition of at least one sacrificial material precursor; depositing a composite layer; removale of the porogen material in the composite layer to form a porous layer and contacting the layered substrate with a removal media to substantially remove the sacrificial material and provide the air gaps within the substrate; wherein the at least one sacrificial material precursor is selected from the group consisting of: an organic porogen; silicon, and a polar solvent soluble metal oxide and mixtures thereof.

Abstract: Semiconductor wafers, semiconductor devices, and methods of making semiconductor wafers and devices are provided. Embodiments of the present invention are especially suitable for use with substrate substitution applications, such in the case of fabricating vertical LED. One embodiment of the present invention includes a method of making a semiconductor device, the method comprising providing a substrate; forming a plurality of polishing stops on the substrate; growing one or more buffer layers on the substrate; growing one or more epitaxial layers on the one or more buffer layers; and applying one or more metal layers to the one or more epitaxial layers. Additionally, the steps of affixing a second substrate to the one or more metal layers and removing the base substrate using a mechanical thinning process may be performed.

Abstract: A method for manufacturing a semiconductor package includes the steps of forming first circuit patterns on an upper surface of a carrier substrate. Bumps are formed in recesses defined on the upper surface of the carrier substrate. An insulation layer is formed on the upper surface of the carrier substrate to cover the first circuit patterns. Second circuit patterns are formed on an upper surface of the insulation layer so as to be electrically connected with the first circuit patterns. The carrier substrate is then separated from the insulation layer.

Abstract: In each of a plurality of input channels of an audio mixer, there are provided a fader operator for adjusting a tone volume level, and a send level adjustment section for adjusting a send level of an audio signal to be sent from the channel to individual mixing buses. On an operation panel of the mixer, there are provided a plurality of bus selection switches in corresponding relation to the mixing buses. Once any one of the bus selection switches is depressed once, the mixing bus corresponding to the operated bus selection switch is allocated to a selected send level operator. Activation/deactivation of a Sends On Fader (SOF) function may be instructed by a user depressing any one of the bus selection switches twice in succession.

Abstract: A conductive layer may be fabricated on a semiconductor substrate by loading a silicon substrate in to a chamber whose inside temperature is at a loading temperature in the range of approximately 250° C. to approximately 300° C., increasing the inside temperature of the chamber from the loading temperature to a process temperature, and sequentially stacking a single crystalline silicon layer and a polycrystalline silicon layer over the silicon substrate by supplying a silicon source gas and an impurity source gas in to the chamber, where the chamber may be, for example, a CVD chamber or a LPCVD chamber.

Abstract: Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved.

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.