Abstract: A system is configured to capture a set of interrupts and output the interrupts serially onto an interconnect. The interrupts, which are routed to a destination, may first be packetized such that additional information is associated with the interrupt within the packet.

Abstract: A method, system and computer program product are provided for implementing dynamic cost calculation for a Single Root Input/Output Virtualization (SRIOV) virtual function (VF) in cloud environments. A management function periodically queries the SRIOV adapter for activity statistics for each assigned virtual function. The management function builds a usage heuristic based on the resource usage statistics. The management function calculates dynamic cost for the SRIOV VF based on the resource usage statistics. Calculated dynamic costs for the SRIOV VF are provided to a virtual function user and users are enabled to scale their VF resources. The VF resources are selectively scaled-up and scaled-down responsive to user input based upon VF resource usage.

Abstract: A system may include a first region implemented in programmable circuitry of a programmable integrated circuit. The first region may include predefined interface circuitry configured to communicate with a host processor. The system may include a second region implemented in the programmable circuitry of the programmable integrated circuit. The second region may include a first hardware accelerated kernel of an OpenCL application. The system may include a first monitor circuit implemented within the first region or the second region. The first hardware accelerated kernel and the first monitor circuit may be coupled to the interface circuitry of the first region. The first monitor circuit may be operable responsive to control signals received from the host processor of a platform through the interface circuitry to store operation data for the first region or the first hardware accelerated kernel.

Abstract: An embodiment of the invention provides a method for optimizing flash device accesses, comprising: interleaving and striping, in tandem, for a transfer of data the other portions of the data.

Abstract: A USB Type-C secondary data channel communication system includes a controller system coupled to a first USB Type-C connector. The controller system determines a second USB Type-C connector orientation when a second USB Type-C connector is connected to the first USB Type-C connector. The controller system then communicates with a connected system through a first data channel available through the second USB Type-C connector and determines that the connected system provides a second data channel mode. In response to determining the connected system provides the second data channel mode, the controller system uses the second USB Type-C connector orientation to configure the provisioning of first data through the first data channel and second data through a second data channel that is available through the second USB Type-C connector. Different data communications may then be provided to the connected system using the first and second data channels.

Abstract: A system-on-chip including non-hopping bus interfaces and a hopping bus. The non-hopping bus interfaces include a first non-hopping bus interface and a second non-hopping bus interface. The first non-hopping bus interface is configured to, based on a first protocol, receive information. The hopping bus includes intra-chip adaptors. The intra-chip adaptors are connected in series and respectively to the non-hopping bus interfaces. The intra-chip adaptors are configured to (i) according to a second protocol, convert the information into a first format for transmission over the hopping bus, and (ii) transfer the information in the first format over the hopping bus and between the intra-chip adaptors. The second protocol is different than the first protocol. The second non-hopping bus interface is configured to receive the information from the hopping bus based on the transmission of the information over the hopping bus.

Abstract: In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of providing the guest operating system with direct access to a hardware device coupled to the virtualized computer system via a communication interface, the method including: (a) obtaining first configuration register information corresponding to the hardware device, the hardware device connected to the virtualized computer system via the communication interface; (b) creating a passthrough device by copying at least part of the first configuration register information to generate second configuration register information corresponding to the passthrough device; and (c) enabling the guest operating system to directly access the hardware device corresponding to the passthrough device by providing access to the second configuration register information of the passthrough device.

Abstract: This document describes techniques (300, 400) and apparatuses (100, 500, 600, 700) for in-band peripheral authentication. These techniques (300, 400) and apparatuses (100, 500, 600, 700) may communicate via a non-media channel allowing host device (102) to authenticate peripheral (106), enable an enhanced operational mode of the host device (102), and/or provide content configured for the peripheral (106) without the use of out-of-band signaling.

Abstract: In some embodiments, the present disclosure provides techniques for concurrently exchanging USB 2.0 information, SuperSpeed information, and four lanes of DisplayPort information via a single USB Type-C connection. In some embodiments, this may be accomplished in part by multiplexing signals such as the USB 2.0 signals and the DisplayPort AUX signal to fewer than a standard number of conductors in order to free up other conductors for the third and fourth lanes of DisplayPort information. In some embodiments, a standard USB Type-C receptacle, plug, and cable are used. In some embodiments, a modified receptacle, plug, and/or cable are provided.

Abstract: Method, apparatus, and system of detecting a hot-plug event. The hot-plug event detection may be done in-band or out-of-band. The in-band detection is performed by a state machine and the out-of-band detection is performed by a logic. A circuitry is to detect a hot-plug event when inserting or removing a device from an extension bus of the plurality of extension bus slots. The circuit is to generate a hot-plug message to notify the hot-plug event. The circuitry including the state machine, the logic and a register to provide at least two bits to mask at least two states of the state machine.

Abstract: A method, system and computer program product for providing a guest with access to a virtual storage on a physical storage using a peripheral component interface hub. In one embodiment, the method comprises the guest sending to the peripheral component interface hub a request to access the physical storage, the request including physical addresses of the physical storage, and the peripheral component interface hub sending specified information about the request to a hypervisor. This method further comprises the hypervisor determining whether to grant or to reject the request; and when the hypervisor grants the request, the hypervisor sending a configuration command to the peripheral component interface hub. This command includes a mapping of addresses from the physical storage to addresses from the virtual storage. In an embodiment, the peripheral component interface hub uses this mapping to replace the addresses in the request with translated virtual addresses.

Abstract: A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.

Abstract: A combination patch panel and distribution amplifier within a single housing composed of a plurality of card modules which may have a data format interface with a configurable input/output module known as small footprint plugables for the transmission and distribution of signals, data, and the like, in either serial digital mode, internet protocol mode or other signals, each card module configurable to provide for any front panel jack functioning as a repeater output from external source, input distribution amplifier, output distribution amplifier, or destination jack.

Abstract: A serial low-power inter-chip media bus communications link is deployed in apparatus having multiple Integrated Circuit devices. Communications capabilities of a device coupled to the communications link may be determined and configuration or framing message may be sent to the first device based on the capabilities. The messages may be transmitted on a primary data line of the communications link with a clock used to control timing of transmission on at least the primary data line. The communications capabilities can include information identifying a number of data wires supported by or coupled to the device. A first device may be configured to communicate with a second device over a secondary data line, which may be reserved for such direct communication. Communications on the secondary data line may be synchronized using the clock signal and may be controlled by a different protocol than the protocol used for the primary data line.

Abstract: Systems and methods for low voltage secure digital (SD) interfaces are disclosed. Embodiments of the present disclosure relate to systems and voltage for a lower voltage SD or SD Input/Output (SDIO) interface such as two integrated circuits. In particular, a SD or SDIO interface may be established between two SD compliant devices. While the SD compliant devices may otherwise comply with the SD standard, the voltage levels for signals passed between the SD compliant devices may be below 1.8 volts that the standard mandates. This reduced voltage is possible because the distances involved for interchip communication or the short distances involved for mobile terminal to peripheral connection are short enough that the reduced voltage is sufficient to still provide the desired signal strength at the receiver.

Abstract: Techniques for tracking, by a host system, virtual machine (VM) memory modified by a physical input/output (I/O) device that supports I/O virtualization are provided. In one embodiment, a hypervisor of the host system can receive a hardware interrupt from the physical I/O device, where the hardware interrupt indicates that a virtual function (VF) of the physical I/O device has completed a direct memory access (DMA) write to a guest memory space of a VM running on the host system. In response to the hardware interrupt, the hypervisor can invoke a function implemented by a physical function (PF) driver of the physical I/O device, where the function is configured to inspect the VF's state in order to identify memory portions modified by the DMA write. The hypervisor can then mark, in a hypervisor-level page table, one or more memory pages corresponding to the identified memory portions as dirty pages.

Abstract: Migrating interrupts from a source I/O adapter of a computing system to a destination I/O adapter of the computing system, includes: collecting, by a hypervisor of the computing system, interrupt mapping information, where the hypervisor supports operation of a logical partition executing and the logical partition is configured to receive interrupts from the source I/O adapter; configuring, by the hypervisor, the destination I/O adapter with the interrupt mapping information collected by the hypervisor; placing, by the hypervisor, the destination I/O adapter and the source I/O in an error state; deconfiguring the source I/O adapter from the logical partition; and enabling the logical partition and destination I/O adapter to recover from the error state.

Abstract: Techniques related to filtering hot plug signals are described herein. The techniques include receiving a first hot plug detect (HPD) signals and a second HPD signal from an external display device. A time period between receiving the first and second HPD signals is determined, and the first and second HPD signals are filtered based on the determined time period.

Abstract: Described is an improved storage architecture. In a particular aspect an improved storage architecture with increased throughput to Ethernet storage modules due to elimination of data path handling from a main control CPU is set forth. Other method and apparatus are described therein, including a scalable Ethernet storage module particularly suited for usage with the improved storage architecture described herein.

Abstract: Systems and methods for analyzing a PCIe network using a graph-theory based analysis are disclosed. A management CPU is coupled to the root complex of the PCIe system and is operable to survey potential CPU-resource combinations in a PCIe system and assign a group of PCIe resources to a CPU. A first switch and a second switch are coupled to the root node, and a first CPU and a first group of PCIe resources are coupled to the first switch. The management CPU assigns a group of PCIe resources to a CPU based on the isolation of the first and second CPUs or a distance between the first and second CPUs and the groups of PCIe resources. According to some embodiments, for potential pairs of devices and NTB/CPUs, the distance between components is assessed, possible alternative paths are identified, and the isolation of the pair is determined.