Abstract: Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a register renaming table to determine if the particular functional unit has recently accessed the source register and thus is likely to comprise an entry for the source register in its register file cache. In particular, the register renaming table comprises entries for physical registers that indicate what functional units have accessed the physical register. If the particular functional unit has not accessed the particular physical register the migration unit migrates data to the register file cache associated with the particular functional unit.

Abstract: A communication device provides wireless communication between a controller in a motor vehicle and a network having at least one device external to the motor vehicle. The controller includes a computation device with at least two processor cores. Data interchange between the communication device and a first processor core takes place exclusively via a second of the processor cores.

Abstract: A system and method are disclosed for guest-programmable relocation of system tables in a virtualized computer system. In accordance with one embodiment, a hypervisor that is executed by a computer system obtains a first base address of a first portion of memory, where the first base address is in an address space of a guest of a virtual machine, and where the first base address is for a set of one or more system tables that is currently exposed by the hypervisor at a second portion of memory having a second base address in the address space of the guest. The hypervisor then generates a new version of the set of one or more system tables that is exposed to the guest at the first base address.

Abstract: Systems and methods for implementing remote direct memory access (RDMA) with copy-on-write support. An example method may comprise: registering, with an RDMA adapter, by a first computer system, a mapping of a first virtual address to a first physical address, for transmitting a memory page identified by the first virtual address to a second computer system; registering, with the RDMA adapter, a mapping of a second virtual address to the first physical address; detecting an attempt to modify the memory page; copying the memory page to a second physical address; and registering, with the RDMA adapter, a mapping of a first virtual address to the second physical address.

Abstract: Present invention disclose a hardware accelerator and a chip, and the hardware accelerator includes: an interface circuit and an accelerator core coupled to the interface circuit, where the interface circuit is configured to receive a first task request, perform decoding on the first task request to acquire identifier information, and configure, according to the identifier information, the first task request to be in an FIFO queue that matches the identifier information; a scheduling controller is configured to determine, from at least two channel groups, one or more target channel groups that have at least one to-be-processed second task request in an nth period, receive a time parameter that is fed back by the accelerator core and corresponding to the target channel group, and schedule the at least one second task request in the one or more target channel groups according to the time parameter and a weighted round robin algorithm.

Abstract: A serial peripheral interface is configurable to operate in a I2S transmission mode. The interface has a transmission unit connected with external pins for data, bit clock, and left/right clock signal, a first-in-first-out (FIFO) buffer with a plurality of memory lines, and a control unit operable to read data portions from two memory lines, to assemble them into a transmission word, and to forward the assembled transmission word to the transmission unit, wherein the transmission unit is configured to serially transmit the assembled transmission word through the external data pin.

Abstract: Systems and methods are provided for expanding the available memory of a storage controller. The systems and methods utilize a PCIe memory controller connected to the backend interface of the storage controller. Memory of the PCIe memory controller is memory mapped to controller memory of the storage controller. The PCIe connection allows the storage controller to access the memory of the PCIe memory controller with latencies similar to that of the controller memory.

Abstract: A method for updating lower module information in a battery module structure in which an upper controller controls and manages a lower module configured of a plurality of battery modules and lower battery managers connected to each of the battery modules by communicating with each of the lower battery managers. The method includes when the lower module is additionally connected, recognizing, by the upper controller, the addition of the lower module by exchanging a message with the added lower module. The added lower module is registered by assigning a new unique ID to the added lower module by exchanging the message with the added lower module by the upper controller.

Abstract: A receiver includes an analog-to-digital converter (ADC) module that receives a test signal via a transmission channel and provides a time domain representation of the test signal as received by the receiver, and a processor that determines a time domain representation of an impedance of the transmission channel based on the time domain representation of the test signal.

Abstract: An integrated circuit device has a first processing unit, a second processing unit, an external interface, and a control program controlling the first processing unit and the second processing unit, and in communication with the external interface. The first processing unit is configured to respond to a reset signal from the external interface by transmitting an answer-to-reset (ATR) to the external interface. When the first processing unit implements an initialization process, the control program makes a determination as to whether a shutdown state flag is set. In response to detecting the shutdown state flag set, the control program controls the second processing unit to transmit to the external interface diagnostic data of the integrated circuit device.

Abstract: In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed.

Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower.

Abstract: A bi-synchronous electronic device may include a FIFO memory circuit configured to store data, and a first digital circuit coupled to the FIFO memory circuit and configured to operate based upon a first clock signal and a write pointer, write a data burst to the FIFO memory circuit, thereby causing a jump in the write pointer to a new position, and write a burst indicator associated with the new position in the FIFO memory circuit. The bi-synchronous electronic device may include a second digital circuit coupled to the FIFO memory circuit and configured to operate based upon a second clock signal different from the first clock signal, read from the FIFO memory circuit based upon a read pointer, and synchronize the read pointer to the write pointer based upon the burst indicator.

Abstract: Migrating interrupts from a source I/O adapter of a computing system to a destination I/O adapter of the computing system, includes: collecting, by a hypervisor of the computing system, interrupt mapping information, where the hypervisor supports operation of a logical partition executing and the logical partition is configured to receive interrupts from the source I/O adapter; configuring, by the hypervisor, the destination I/O adapter with the interrupt mapping information collected by the hypervisor; placing, by the hypervisor, the destination I/O adapter and the source I/O in an error state; deconfiguring the source I/O adapter from the logical partition; and enabling the logical partition and destination I/O adapter to recover from the error state.

Abstract: A link layer of a serial protocol is modified to perform early primitive detection. An early primitive detector unit compares an undecoded bit sequence to that corresponding to a particular primitive. A primitive notification is generated in response to identifying a match. Latency is reduced compared with performing link layer decoding and then identifying primitives.

Abstract: The semiconductor device includes a command generator, an information signal storage unit, a termination signal generator and a code generator. The command generator generates a mode register write command signal, a start command signal and a termination command signal from external command signals. The information signal storage unit extracts information signals from the external command signals to store the information signals and output the information signals. The termination signal generator generates a termination signal in response to the information signals. The code generator generates code signals to control a timing of a control signal.

Abstract: In general, embodiments of the present disclosure are directed to techniques for configuring a mobile device according to detection of one or more peripheral devices in an environment using short-range wireless communication. In one example, a method includes, receiving, by a computing device that communicates with a peripheral device using short-range wireless communication, a unique identifier of the peripheral device. If the computing device recognizes the unique identifier of the peripheral device, the computing device may determine a configuration operation based on the unique identifier that changes a current operating state of at least one application executing on the computing device to a different operating state. If the computing device does not recognize the unique identifier of the peripheral device, the computing device may send a lookup request to a network resource external to the computing device that requests data specifying the configuration operation for the computing device.

Abstract: A host receives information related to garbage collection of a storage device, and the host controls selective execution of garbage collection by the storage device according to the received information.

Abstract: Systems, methods, circuits and computer-readable mediums for peripheral sequencing using an access sequence are disclosed. In some implementations, a control register and status register in a peripheral are initialized with control data for selecting peripheral registers of the peripheral to be refreshed during an access sequence. For each peripheral register to be refreshed during the access sequence: a data register of the peripheral register is accessed; the peripheral register is refreshed; and the status register is updated with a current status of the access sequence. The access sequence is determined to be completed based on contents of the status register.

Abstract: One embodiment relates to an integrated circuit which includes a method of dynamically adjusting a receive buffer in an integrated circuit. A fixed-size buffer circuit of the receive buffer is used to buffer data received by way of a serial interface circuit. The performance of the serial interface circuit are monitored. The receive buffer is dynamically extended based on said performance. Other embodiments, aspects, and features are also disclosed.