Patents Examined by Eric T Loonan
  • Patent number: 11157411
    Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: October 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sanjeev Ghai, Guy L. Guthrie, Stephen J. Powell, William J. Starke
  • Patent number: 11132213
    Abstract: Systems and methods are described for transforming a data set within a data source into a series of task calls to an on-demand code execution environment. The environment can utilize pre-initialized virtual machine instances to enable execution of user-specified code in a rapid manner, without delays typically caused by initialization of the virtual machine instances, and are often used to process data in near-real time, as it is created. However, limitations in computing resources may inhibit a user from utilizing an on-demand code execution environment to simultaneously process a large, existing data set. The present application provides a task generation system that can iteratively retrieve data items from an existing data set and generate corresponding task calls to the on-demand computing environment. The calls can be ordered to address dependencies of the data items, such as when a first data item depends on prior processing of a second data item.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: September 28, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Timothy Allen Wagner, Marc John Brooker, Ajay Nair
  • Patent number: 11127468
    Abstract: Some embodiments include a method for addressing an integrated circuit for a non-volatile memory of the EEPROM type on a bus of the I2C type. The memory includes J hardware-identification pins, with J being an integer lying between 1 and 3, which are assigned respective potentials defining an assignment code on J bits. The method includes a first mode of addressing used selectively when the assignment code is equal to a fixed reference code on J bits, and a second mode of addressing used selectively when the assignment code is different from the reference code. In the first mode, the memory plane of the non-volatile memory is addressed by a memory address contained in the last low-order bits of the slave address and in the first N bytes received. In the second mode, the memory plane is addressed by a memory address contained in the first N+1 bytes received.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: September 21, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Fran├žois Tailliet, Marc Battista
  • Patent number: 11099748
    Abstract: A radiation hardened, digital to analog converter includes first and second serial communication circuits, a common bus interface configured to connect the first and second serial communication circuits to first and second digital serial communication buses, respectively, and a digital to analog converter circuit, where the first and second serial communication circuits are configured to receive data over the first and second digital serial communication buses, respectively, for use by the digital to analog converter circuit.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: August 24, 2021
    Assignee: United States of America as represented by the Administrator of NASA
    Inventors: James E. Fraction, Andrzej T. Jackowski
  • Patent number: 11093397
    Abstract: Use of a survival queue to manage a container-based flash cache is disclosed. In various embodiments, a corresponding survival time is associated with each of a plurality of containers stored in a flash cache, each container comprising a plurality of data blocks. The survival time may be determined based at least in part on a calculated proportion of relatively recently accessed data blocks associated with the container is associated with the container. A container to evict from the flash cache is selected based at least in part on a determination that the corresponding survival time of the selected container has expired.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: August 17, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Frederick Douglis, Cheng Li, Philip Shilane, Grant Wallace
  • Patent number: 11086898
    Abstract: Methods and apparatus for token-based admission control for replicated writes are disclosed. Data objects are divided into partitions, and corresponding to each partition, at least a master replica and a slave replica are stored. A determination as to whether to accept a write request directed to the partition is made based at least in part on one or more of (a) available throughput capacity at the master replica, and (b) an indication, obtained using a token-based protocol, of available throughput capacity at the slave replica. If the write request is accepted, one or more data modification operations are initiated.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: August 10, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Kiran-Kumar Muniswamy-Reddy, Bjorn Patrick Swift, Miguel Mascarenhas Filipe, Timothy Andrew Rath, Stefano Stefani, Yijun Lu, Wei Xiao, Stuart Henry Seelye Marshall, James R. Hamilton
  • Patent number: 11087797
    Abstract: There is provided a tape recording apparatus system capable of improving writing performance and maintaining tape recording density, for a multiple data writing request accompanied by a lot of synchronization requests from a host. The system is a tape storage system including two or more tape drives each of which has a tape mounted thereon and is provided with a buffer divided in fixed-length segments, and connected to a host that sends multiple data and a synchronization request at a predetermined timing to these tape drives.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: August 10, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Atsushi Abe, Takashi Katagiri, Motoko Oe, Setsuko Masuda, Yutaka Oishi, Noriko Yamamoto, Katsumi Yoshimura
  • Patent number: 11020855
    Abstract: Provided is a storage device including: a first storage region comprising a plurality of sensor regions for the plurality of the sensors; a second storage region into which a data set is written, the data set being generated by reading, from the respective plurality of sensor regions, sampling data of a sensor having a longest sampling period among the plurality of sensors for one period and sampling data of other sensors for a period corresponding to the period in which the sampling data of the sensor for the one period is generated and integrating the sampling data; and a control unit configured to write the sampling data of the plurality of sensors into the plurality of sensor regions, respectively, in a ring buffer format and generate the data set at a predetermined timing and write the data set into the second storage region in the ring buffer format.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 1, 2021
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takahiro Nakayama, Kazuhiro Mima, Hiroshi Bito
  • Patent number: 10977215
    Abstract: A data de-duplication system includes a storage device that includes multiple data sets, a fixed read-only storage area, and a processing device configured to perform certain functions. The system determines whether each of the multiple data sets has met a common pattern criteria, and if so, identifies the data set as a candidate data set for de-duplication. The common pattern criteria is indicative of whether a chunk data is frequently accessed among multiple users on a cloud. The system stores data in at least one candidate data sets in the fixed storage area. For each of the at least candidate data sets, the system generates a unique pointer that corresponds to a location of the at least one candidate data sets in the fixed storage area. The system further uses the pointers to de-duplicate the at least one candidate data sets.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: April 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ezra Hartz, Heiko Schloesser
  • Patent number: 10970409
    Abstract: Circuits, methods, and apparatus for storing application data, keys, authorization codes, or other information in a volatile memory on an FPGA. A field programmable gate array (FPGA) can include multiple memory blocks and partition those blocks among multiple independent reconfigurable regions. Access to the memory blocks can then be restricted so that only authorized regions have access to particular memory partitions. In addition, each partition can store multiple message authentication codes (MACs) for further controlling access to data in each partition.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: April 6, 2021
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 10969970
    Abstract: According to an embodiment, a database device includes a volatile first storing unit, a non-volatile second storing unit, an access processing unit configured to execute an operation corresponding to an access request for each of a plurality of blocks obtained by dividing data pieces, a backup processing unit configured to write data of each of the plurality of blocks at a backup time to the second storing unit, and a block management unit. The block management unit writes, under certain conditions, data of any block stored in the first storing unit to the second storing unit, and reads data of a block targeted by an access request from the second storing unit to the first storing unit. The backup processing unit writes data of a block that is not yet written to the second storing unit among the plurality of blocks.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: April 6, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Solutions Corporation
    Inventor: Masakazu Hattori
  • Patent number: 10956342
    Abstract: A multi-controller memory system includes a flexible channel memory controller coupled to at least first and second physical interfaces. The second physical interface is also coupled to an auxiliary memory controller. The physical interfaces may be coupled to separate memory modules. In a single-channel control mode, the memory controllers respectively control the memory modules coupled to the first and second physical interface. In a multi-channel control mode, the flexible channel memory controller controls both memory modules while the auxiliary memory controller is inactive. In a single-channel control mode, the memory controllers coordinate restricted memory control commands which access a resource shared by both modules, by one controller transmitting a request signal for the resource to the other controller, awaiting an acknowledgment signal from the other controller, and maintaining transmission of the request signal until the use of the resource is completed.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: March 23, 2021
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: John MacLaren, Jerome J. Johnson, Landon Laws, Anne Hughes
  • Patent number: 10908998
    Abstract: A data storage device comprises a non-volatile semiconductor memory device and a solid-state drive controller communicatively coupled to the non-volatile semiconductor memory device, including a function level reset manager. The function level reset manager can receive a function level reset request from a host system, generate a function level reset bitmap based on the function level reset request, and broadcast the function level reset request to a command processing pipeline. The function level reset bitmap can indicate which functions are in a reset state. Further, the function level reset manager can determine which functions are in the reset state and instruct the command processing pipeline to cancel commands associated with the functions in the reset state.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: February 2, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Zhimin Ding, Sancar K. Olcay
  • Patent number: 10896128
    Abstract: Technology is provided for partitioning a shared unified cache in a multi-processor computer system. The technology can receive a request to allocate a portion of a shared unified cache memory for storing only executable instructions, partition the cache memory into multiple partitions, and allocate one of the partitions for storing only executable instructions. The technology can further determine the size of the portion of the cache memory to be allocated for storing only executable instructions as a function of the size of the multi-processor's L1 instruction cache and the number of cores in the multi-processor.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: January 19, 2021
    Assignee: Facebook, Inc.
    Inventors: Narsing Vijayrao, Keith Adams
  • Patent number: 10891145
    Abstract: Systems and methods are described for transforming a data set within a data source into a series of task calls to an on-demand code execution environment or other distributed code execution environment. Such environments utilize pre-initialized virtual machine instances to enable execution of user-specified code in a rapid manner, without delays typically caused by initialization of the virtual machine instances, and are often used to process data in near-real time, as it is created. However, limitations in computing resources may inhibit a user from utilizing an on-demand code execution environment to simultaneously process a large, existing data set. The present application provides a task generation system that can iteratively retrieve data items from an existing data set and generate corresponding task calls to the on-demand computing environment, while ensuring that at least one task call for each data item within the existing data set is made.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: January 12, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Timothy Allen Wagner, Marc John Brooker, Ajay Nair
  • Patent number: 10884950
    Abstract: Memory management is provided which includes a page replacement process managed by a storage manager and a workload manager. The page replacement process swaps out the content associated with a frame of physical memory to an auxiliary storage in order to provide a free frame. The memory management process includes: determining that the physical memory runs out of free frames; providing priority information from the workload manager to the storage manager, the priority information indicating the priority or business relevance of a certain process; selecting one or more pages to be swapped to the auxiliary storage based on the priority information; and swapping out the contents of the one or more selected pages to the auxiliary storage.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Harris M. Morgenstern, Horst Sinram, Elpida Tzortzatos, Dieter Wellerdiek
  • Patent number: 10877879
    Abstract: Techniques to manage usage of a flash-based storage are disclosed. In various embodiments, the execution time of the flash-based storage is divided into quanta. Within each quantum comprising at least a subset of quanta, flash erasures are allowed without restriction up to a prescribed erasure quota. Erasures are throttled within a slack range bound at a lower end by the erasure quota and at an upper end by an upper bound, including by dividing the slack range into two or more intervals and within each interval applying a corresponding erasure control policy, wherein the respective corresponding erasure control policies applied to successive intervals in the slack range become increasingly strict in a stepwise manner.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: December 29, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Cheng Li, Philip Shilane, Grant Wallace, Frederick Douglis
  • Patent number: 10877669
    Abstract: A system that implements a scaleable data storage service may maintain tables in a data store on behalf of storage service clients. The service may maintain data in partitions stored on respective computing nodes in the system. The service may support multiple throughput models, including a committed throughput model and a best effort throughput model. A service request to create a table may specify that requests directed to the table should be serviced under a committed throughput model and may specify the committed throughput level in terms of logical service request units. The service may reserve low-latency storage and other resources sufficient to meet the specified committed throughput level. A client/user may request a modification to the committed throughput level in anticipation of workload changes, such as an increase or decrease in traffic or data volume. In response, the system may increase or decrease the resources reserved for the table.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: December 29, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Swaminathan Sivasubramanian, Stefano Stefani, Wei Xiao, Timothy Andrew Rath, Rande A. Blackman, Grant A. M. McAlister, Raymond S. Bradford
  • Patent number: 10860474
    Abstract: In an example, a starting address corresponding to a location of particular information within a non-volatile storage memory is determined during an initialization process using a multilevel addressing scheme. Using the multilevel addressing scheme may include performing multiple reads of the storage memory at respective address levels to determine the starting address corresponding to the location of the particular information.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: December 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gianfranco Ferrante, Dionisio Minopoli
  • Patent number: 10846001
    Abstract: A distributed storage schemes manages implementation of QoS targets for IOPs across compute nodes executing applications, primary storage nodes storing a primary copy of a logical storage volume, and clone storage nodes. On the compute node, a maximum priority is assigned to a minimum number of IOPs in a queue within a time window from a time of receipt of a last unexecuted IOP. Other IOPs are assigned a minimum priority. On the storage node, maximum priority IOPs are assigned to high priority queues, from which IOPs are executed first, and low priority IOPs are assigned to low priority queues. Methods for determining the capacity of storage nodes and allocating storage requests are also disclosed.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: November 24, 2020
    Assignee: ROBIN SYSTEMS, INC.
    Inventors: Shravan Kumar Vallala, Dhanashankar Venkatesan